Unlocking JavaScript: V8-RISCV Open Sourced

Why V8 While the software ecosystem of RISC-V has evolved rapidly in the last decade, an important domain of applications, web applications, is still missing from the scene. At the heart of the web technology stack are web browsers, and every major web browser today uses JavaScript (JS) engines with Just-in-time (JIT) compilers. The lack of a mature JS engine that supports RISC-V is a major roadblock to enabling the web stack on RISC-V. Today, every major web browser employs its own JavaScript engine, such as V8 for Chromium-based browsers (e.g. Chrome, Brave), TraceMonkey for Firefox, and JavaScriptCore for Safari. According to Wikipedia, Chromium-based browsers account for two thirds of browser usage shares (in terms of percentage of web sites visited by a particular web browser) in 2020. In addition, Node.js, the dominant server-side JavaScript runtime framework, brings JavaScript beyond browsers and onto the cloud and edge devices as web backends and serverless function platforms. Both Chromium-based browsers and Node.js are powered by V8, the open-source JavaScript engine developed by Google in 2008. As such, V8 is considered the most widely used JS Engine for both client-side and server-side JavaScript.

V8-RISCV Open-Sourced

V8 is a mature, cross-platform JS engine that supports multiple backends including x86, ARM, MIPS and PowerPC. V8 employs the TurboFan compiler to compile JavaScript to machine codes for each target platform. To minimize startup time and memory consumption, JS codes are initially executed in the V8 interpreter, the Ignition Engine. The Ignition engine relies on the Turbofan compiler to generate target-specific bytecode handlers ahead-of-time. This unique design results in a much faster interpreter, but also implies that the porting of the V8 interpreter still requires extending the TurboFan compiler to support a new backend. With a joint effort between Futurewei Technologies and the RIOS lab, v8-riscv, a RISC-V 64-bit backend for V8 was open-sourced in July. V8-riscv enables the complete functionality of V8 (including the Turbofan compiler, the Ignition Engine and the WebAssembly compiler) for any RISC-V ISA that supports RV64I, M, A, F, D and Zifencei extensions. The functional completeness of a V8 port is measured by the coverage of the extensive set of V8 test cases. Currently, v8-riscv passes over 15,000 standard v8 test cases as well as standard benchmarks such as Sunspider and Kraken on HiFive Unleashed running Fedora Developer Rawhide. The open-sourcing of v8-riscv pushes our porting effort to a new phase of community participation. There is still plenty of work ahead in bringing a high-performing V8 engine that leverages the full capability of a highly customizable RISC-V ISA. For the next few months, we would like to focus on upstreaming to V8, improving the performance of the 64-bit backend, and supporting or experimenting with additional RISC-V extensions such as C, V, and the upcoming J extensions. Please refer to our project roadmap and workgroups for more details. We invite any community members who would like to contribute to V8 on RISC-V to join our effort. We already have a good story to share: within the first week of open-sourcing v8-riscv, the PLCT lab of Chinese Academy of Sciences, who has worked on another independent port of V8 for RISC-V, decided to consolidate the porting effort and join v8-riscv.

Beyond V8 and Javascript

With the enablement of V8, porting Node.js to RISC-V is a natural next step. We have some promising early results of bringing up a simple Node-based web server using v8-riscv. The enablement of client-side JavaScript, on the other hand, requires a considerable porting effort on the Chromium browser itself. In addition, along with the RIOS lab PicoRio project, we are exploring hardware support for improving Javascript VM efficiency. As part of the PicoRio project, we look forward to working with the community to bringing Chromium browsers and the full Chromium OS onto RISC-V. With v8-riscv, we bring not one but two languages to RISC-V. The second language is WebAssembly. In 2019, the W3C announced WebAssembly as the fourth official language of the web (among HTML, CSS, and JavaScript) that has support from all W3C-compatible browsers. WebAssembly is a portable, compact and secure Intermediate Representation (IR) designed to bring native applications written in C/C++ or Rust onto the web. Today, WebAssembly is expanding beyond the web and serves as a promising IR for lightweight isolation and trusted execution. With v8-riscv, the young but growing ecosystem of WebAssembly is further unlocked to the RISC-V modular ISA architecture.

Conclusions

Extending a compiler to support a new Instruction Set Architecture (ISA) is a major undertaking. While the RISC-V language toolchains support most popular statically compiled languages (e.g., C, C++, Rust and Go) as well as interpreter-based languages (e.g., Python), support for languages that require JIT compilers (e.g., Java, JS, Hack, Dart) are still largely lacking. By enabling JavaScript on RISC-V, v8-riscv not only removes a critical roadblock to enabling the web technology stack on RISC-V, but also unlocks several mature and fledging ecosystems such as JavaScript, NodeJS and WebAssembly to further enrich the software ecosystem of RISC-V.[/vc_column_text][vc_column_text]About the Authors[/vc_column_text][/vc_column][/vc_row][vc_row type="in_container" full_screen_row_position="middle" column_margin="default" column_direction="default" column_direction_tablet="default" column_direction_phone="default" scene_position="center" text_color="dark" text_align="left" row_border_radius="none" row_border_radius_applies="bg" overlay_strength="0.3" gradient_direction="left_to_right" shape_divider_position="bottom" bg_image_animation="none"][vc_column column_padding="no-extra-padding" column_padding_tablet="inherit" column_padding_phone="inherit" column_padding_position="all" background_color_opacity="1" background_hover_color_opacity="1" column_shadow="none" column_border_radius="none" column_link_target="_self" gradient_direction="left_to_right" overlay_strength="0.3" width="1/4" tablet_width_inherit="default" tablet_text_alignment="default" phone_text_alignment="default" column_border_width="none" column_border_style="solid" bg_image_animation="none"][image_with_animation image_url="21039" animation="Fade In" hover_animation="none" alignment="" border_radius="none" box_shadow="none" image_loading="default" max_width="100%" max_width_mobile="default"][/vc_column][vc_column column_padding="no-extra-padding" column_padding_tablet="inherit" column_padding_phone="inherit" column_padding_position="all" background_color_opacity="1" background_hover_color_opacity="1" column_shadow="none" column_border_radius="none" column_link_target="_self" gradient_direction="left_to_right" overlay_strength="0.3" width="3/4" tablet_width_inherit="default" tablet_text_alignment="default" phone_text_alignment="default" column_border_width="none" column_border_style="solid" bg_image_animation="none"][vc_column_text]Zhangxi Tan is the Co-Director of the RIOS Lab, an Adjunct Professor at TBSI, and the Founder and President of RiVAI Technologies Co. LTD. Prior to these roles, Dr. Tan joined Pure Storage as the company’s first chip designer, and successfully guided the delivery of FlashBladeTM. Dr. Tan holds more than 20 US patents, and he is also the inventor of the FPGA-based architecture simulator (RAMP Gold). Dr. Tan earned Bachelor and Master degrees in electrical engineering and computer science from Tsinghua University; Master and PhD degrees in computer science from University of California, Berkeley, where he was supervised by Prof. David Patterson. [/vc_column_text][/vc_column][/vc_row][vc_row type="in_container" full_screen_row_position="middle" column_margin="default" column_direction="default" column_direction_tablet="default" column_direction_phone="default" scene_position="center" text_color="dark" text_align="left" row_border_radius="none" row_border_radius_applies="bg" overlay_strength="0.3" gradient_direction="left_to_right" shape_divider_position="bottom" bg_image_animation="none"][vc_column column_padding="no-extra-padding" column_padding_tablet="inherit" column_padding_phone="inherit" column_padding_position="all" background_color_opacity="1" background_hover_color_opacity="1" column_shadow="none" column_border_radius="none" column_link_target="_self" gradient_direction="left_to_right" overlay_strength="0.3" width="1/4" tablet_width_inherit="default" tablet_text_alignment="default" phone_text_alignment="default" column_border_width="none" column_border_style="solid" bg_image_animation="none"][image_with_animation image_url="21041" animation="Fade In" hover_animation="none" alignment="" border_radius="none" box_shadow="none" image_loading="default" max_width="100%" max_width_mobile="default"][/vc_column][vc_column column_padding="no-extra-padding" column_padding_tablet="inherit" column_padding_phone="inherit" column_padding_position="all" background_color_opacity="1" background_hover_color_opacity="1" column_shadow="none" column_border_radius="none" column_link_target="_self" gradient_direction="left_to_right" overlay_strength="0.3" width="3/4" tablet_width_inherit="default" tablet_text_alignment="default" phone_text_alignment="default" column_border_width="none" column_border_style="solid" bg_image_animation="none"][vc_column_text]Peng Wu is Technical VP for the Programming Technologies domain at Futurewei Technologies. Previously she founded and served as the head of the Programming Technologies Lab at Huawei, one of the first of its kind in a major Chinese company. Prior to that, she was a research staff member at IBM T.J. Watson research center for over a decade. While she has worked on all aspects of programming systems, compiler has always been her technical home. She was trained in the specialty of parallelizing compiler and did the early work on compilation for SIMD architectures. Throughout her career, she has worked on static compilers, language VMs, JIT, and domain-specific code generators. And her work has spanned across many architectures, from SIMD (IBM Power, PS3 CELL BE engine), Transactional Memory (BG/Q supercomputers), AI accelerators, and most recently to RISC-V. She is currently developing the RISC-V backend for the V8 Javascript engine. She has been active in the PL research community throughout her career, attending technical conferences yearly and serving on numerous program committees. She has published over 30 papers in peer-reviewed conferences including the best paper award in PACT 2012.[/vc_column_text][/vc_column][/vc_row]]]>