RISC-V: A Playground for Game-changing Design Methodologies

I attended the RISC-V Global Forum on September 3, 2020. I must say, the pandemic does not deter the progress of the global RISC-V community in innovating, collaborating and exhibiting their work. I am Shivam Potdar, a senior EE undergraduate from the National Institute of Technology Karnataka, India. I got introduced to RISC-V about a year ago through the course content of CS61C, UC Berkeley. I then got an opportunity, as a Google Summer of Code (GSoC) student with the Free and Open Source Silicon Foundation (FOSSi), to explore several novel technologies, which, coupled with RISC-V, are set to shape the future of our industry. Now it has turned into a never-ending journey for knowledge and exploration.  GSoC is a program funded by Google to encourage students to contribute to open-source projects. Thanks to the inception of RISC-V and organizations like FOSSi, lowRISC, Symbiflow, BeagleBoard.org, etc., open-source hardware projects are seeing increasing involvement. One of the most exciting aspects of RISC-V is that it provides an open playground for new ideas across multiple domains. It has become the go-to for architectural innovations like OpenTitan and for exhibiting new HDLs like Chisel (Rocket chip, SiFive cores), SpinalHDL (VexRiscv), BlueSpec (Shakti processors), etc. I was able to make the most of a summer of mandated isolation by exploring:

• transaction-level modeling with TL-Verilog
• easy design and debug with Makerchip
• open-source hardware and freely available design tools
• open source formal verification
• a heterogeneous ISA manycore platform

I worked on enhancing a RISC-V core named WARP-V, employing a forward-looking design methodology with TL-Verilog and its integration with OpenPiton, an open-source manycore framework written in SystemVerilog. TL-Verilog is a revolutionary extension to SystemVerilog, led by my GSoC mentor, Steve Hoover. It models systems at the transaction level with a timing-abstract, highly parameterizable, flexible, easy-to-learn/debug/document nature, and significant code size reduction. It is neither HLS nor a programming language applied to hardware, but an abstraction with modern features, maintaining the modeling very close to the hardware. Makerchip.com is a free web-based IDE for TL-Verilog, that supports the design, debug, simulation, and Verilog translation all in a browser tab! WARP-V was developed primarily on this platform. SandPiper, the compiler for TL-Verilog, translates it to synthesizable (System)Verilog compatible with open-source and industry-proven design flows.[/vc_column_text][image_with_animation image_url="21849" animation="Fade In" hover_animation="none" alignment="" border_radius="none" box_shadow="none" image_loading="default" max_width="100%" max_width_mobile="default"][vc_column_text]In school, it took me several weeks of designing and debugging to work on a basic MIPS implementation with Verilog / VHDL. On the flip side, I was a TA in two iterations of the RISC-V Microprocessor for You in Thirty Hours (MYTH) workshop, organized by Steve and Kunal Ghosh. About 200 participants, many with no background in digital design, learned RISC-V and contributed 35 TL-Verilog cores to the community in just five days. I’ll be helping again with a similar workshop on 8th October at VSDOpen 2020, covering TL-Verilog in 1.5 hours! WARP-V presents a highly configurable CPU in TL-Verilog supporting various pipeline depths, long-latency instructions, branch prediction, clock-gating, inline assembler, and even multiple ISAs! For RISC-V, the core supports RV32I[M][F], which is also formally verified with riscv-formal. It has also been characterized and tested on AWS FPGAs using Steve’s custom-logic-as-a-service project — 1st CLaaS. OpenPiton is a multicore research platform supporting heterogeneous ISAs by providing the memory subsystem, IO interfaces, caches, and shared resources to the cores. It is compatible with SPARC, RISC-V, and x86, and several peripherals already.  Over the summer, I worked on adding the RISC-V M-type extension in WARP-V, its formal verification, and preparing for OpenPiton integration by supporting long-latency instructions and providing an external memory interface.[/vc_column_text][image_with_animation image_url="21850" animation="Fade In" hover_animation="none" alignment="" border_radius="none" box_shadow="none" image_loading="default" max_width="100%" max_width_mobile="default"][vc_column_text]In just the past few months, I could observe the tremendous pace of growth for RISC-V. The ecosystem is so open and inclusive that I am today a Community Member of RISC-V International, and participating in various online meetups, webinars, and events like the Global Forum. Today, it is possible to perform the entire RTL to GDS flow, including FPGA emulation, simulation, and fabrication with FOSS tools like Symbiflow, Openlane, Yosys, Verilator, and Skywater PDK. The modern methodologies supported by those tools and technologies like TL-Verilog paired with RISC-V will indeed transform the semiconductor industry. Some people aptly denote RISC-V as the Linux of hardware. It is exciting to see the democratization of hardware and the industry’s changing dynamics where now, even a fabless startup can compete with established giants. As a student entering the field soon, the future looks bright for RISC-V. Go RISC-V 🙂[/vc_column_text][/vc_column][/vc_row]]]>