The RISC-V Vector Extension (RVV) Version 1.0 was ratified by RISC-V International in 2021. Since this public debut, there has been growing excitement about vector processing across a wide spectrum of applications since vectors promise to solve multiple current industry design and development challenges. Licensable IP is already commercially available today and more solutions are expected in the marketplace soon as the robust RISC-V ecosystem embraces the advantages of RISC-V vector solutions.
So why the shift to vector, which was once mainly reserved for the world’s most powerful supercomputers? Today’s data driven applications increasingly require multiple cores combined in ways that can create complex and inefficient environments. When you add in capabilities like artificial intelligence, machine learning, or computer vision you introduce additional challenges like managing power consumption, extra data movement, the need for multiple libraries, and issues with generational incompatibility.
Importantly, RISC-V provides a trusted, standard foundation and is supported by a robust, growing ecosystem. This offers the designer tremendous flexibility. To make vector effective it needs to be delivered in an easy-to-program, more efficient environment. RISC-V has tremendous benefits here.
The RISC-V Vector ISA is a very clean and optimized set of instructions, with the base ISA numbering around just 300 instructions, far smaller than a typical packed-SIMD alternative. Crucially these powerful instructions can each do a lot of work. Denser code means more efficient use of the instruction cache, leading to significantly more power efficient computing. Packed-SIMD and GPU implementations can lead to multiple new instructions being required and as a result chip size increases, (as new data types are introduced) and also additional code required to accommodate “corner case” handling, increased code size and resulting bill of materials cost increases as well as greater power consumption.
RISC-V vectors are a powerful and super efficient (in code size, performance, and area) alternative to the inefficient use of packed-SIMD and GPUs for the processing of large datasets. The ISA is efficient and scalable to all reasonable design points. This means it’s equally ideal from low-cost designs to the highest performance applications. To provide this flexibility the ISA needs to be able to support in-order, decoupled, or out-of-order microarchitectures, along with integer, fixed-point and/or floating point data types.
The ability to utilize different vector lengths with the same software code offers scalability and flexibility. Another big advantage is the reduced software complexity. By eliminating the need for multiple accelerators or DSPs users can achieve significant power reductions and much greater efficiency, which is a big focus across every segment today.
A key defining features of the RISC-V Vector ISA is that it is vector length agnostic. Software code that has been written for any RISC-V vector compliant processor will work on any other RISC-V vector processor. This is valuable to the customer from a software reuse perspective.
Imagine a first-generation end-product was designed around a 256-bit length vector register processor, taking advantage of the balance of power, performance, and area for that first design but then, with market success, new requirements evolved for a second generation product that required a longer vector register length processor with 512-bit length vector registers. With RISC-V not only will the software code execute directly the updated system, but the code performance will improve immensely, without having to change even one line of code. For the customer this offers greatly reduced design and development time, and speeds time-to-market for the second-generation product.
RISC-V vector solutions enable the creation of a unified, efficient, and easy to program design, allowing designers to add differentiation to their product to better target demanding and rapidly changing market requirements. As an open standard, much of the code written for RISC-V vectors will be available in the open standard domain. This allows developers to access the large and growing ecosystem of RISC-V based algorithms, along with access to a full range of open standard and commercial grade tools for compilation, modelling, debug and trace. For the developer this access to open source algorithms provides a standardized and stable approach to algorithm development, and reduces time and development costs.
Applications today are being looked at across a wide spectrum from products like security cameras, where AI comes together with a need for low battery consumption, to hyperscale applications, aerospace and automotive. The opportunities are virtually endless,
For those interested in finding out more about the background and history of the RISC-V ISA, there is an introductory video available here, described by one of the inventors, Andrew Waterman. SiFive, which with its SiFive® Intelligence™ X280 and SiFive Performance™ P270 Processors has products available today, has also posted some tutorials and other material to help educate those wanting to understand more about vector solutions here.
It is an exciting time for RISC-V and the momentum will only accelerate further as the ecosystem continues to expand rapidly and awareness of the many benefits of RISC-V vector solutions spreads.