RISC-V was one of the key themes at DAC 2023. We had a RISC-V Zone where six members discussed their latest RISC-V activities, and there were a ton of RISC-V sessions, research manuscripts, and poster presentations in the conference program. One of the standout moments was a panel discussion our CEO Calista Remond hosted with executives from Intel Foundry Services, Imperas, Meta, OpenHW Group, and Ventana. Read on to find out more.
Meta Shared How the Company is Using RISC-V
Himanshu Sanghavi, ASIC engineering manager at Meta, talked about a variety of projects Meta is working on with RISC-V. He said that custom instructions were “a key factor in our decision to go with the RISC-V architecture” since Meta customizes RISC-V cores from IP providers “in order to accelerate compute, reduce energy, and create more flexible ASICs.”
Sanghavi went into more detail: “My team at Meta is developing RISC-V based ASICs for video transcoding, as well as machine learning applications. And these ASICs are running some of the most computationally intensive workloads in our data centers. These are large, very high-performance devices that consists of multiple different processors, hardware accelerators, memory systems, interface IP, all on one die. When we started this effort about four years ago, we evaluated multiple different processor architectures, and decided to go with RISC-V for some of the critical sockets of these SoCs. That choice was driven by the fact that RISC-V is an open architecture and that there were multiple providers of processor IP that implemented this architecture. Fast forward to today, and we now have several working ASICs that use RISC-V processors for both control processing as well as data processing. The latter, in particular, do use custom instructions. Custom instructions that are defined for some specialized computations that are important for our workloads, as well as building custom interfaces between the processor core and the hardware accelerators that reside on the same silicon.”
You can read more in Meta’s recent blog post on its first-generation AI inference accelerator, which uses processor cores based on RISC-V.
Intel Foundry Services Discussed the Value of RISC-V
Bob Brennan, VP, GM at Intel Foundry Services, shared that companies in the RISC-V ecosystem can “make a lot of money.” Brennan explained: “Instead of trying to do a different IP ecosystem and race for their own processors, they’ve kept the value in the processor, they’re creating value in the platform. And then they’re harmonizing the existing IP ecosystem. I believe this will enable rapid adoption of RISC-V cores and will give people the ability to sort of swap in and out different ISAs in the same SoC architecture, which I believe will lower the barrier to entry for RISC-V overall.”
Brennan also discussed how Intel is contributing to the efforts around RISC-V Platforms: “I believe we have 40 plus people working in various working bodies to help with that. Things like security and virtualization and so forth will be done, I believe, in the first half of next year. After the platform specifications or SoC specifications are complete, we’ll then move to a phase of certification and compliance because if it’s not tested, it’s broken. Once we have the platform crisply defined, then we’ll have certification, education, and compliance.”
Ventana Micro Explored What Makes RISC-V Stand Out
Balaji Baktha, CEO of Ventana Micro, mentioned that “one-size-fits-all” architectures can constrict companies’ design freedom since developers “can’t add a lot of value on top of the base ISA.” In comparison, RISC-V makes it easy for companies to add on custom extensions that meet their specific application requirements.
RISC-V International’s Redmond further emphasized the point about the flexibility of RISC-V: “There is no other architecture that allows you the design freedom and flexibility that RISC-V does … When you’re allowed that level of customization, you can really design to the parameters that are important to your workload: power, price, performance, and the unique variables or the workload challenges that you’re facing. We do this as a modular approach, rather than incrementally adding everything into the pot.”
Baktha was also clear about the advantages of the open RISC-V standard for security: “If you look at security at an ISA level, RISC-V is second to none.”
Imperas Addressed the Role of Software in the RISC-V Ecosystem
Simon Davidmann, CEO of Imperas, noted how the semiconductor landscape has changed over the past 15 years since Imperas’ founding. Back then, he knew that “electronic products were going to be defined by their software,” so Imperas was working to provide companies with better tools to “help the process of design, verification, simulation, and developing the software on those from simulation.”
Davidmann then dove into what Imperas is offering the RISC-V ecosystem today: “In the last three years we’ve been doing not only models for virtual platforms where you can develop software on pre-silicon, but also the technology and verification IP, coverage tests and everything to help people with the verification of RISC-V.”
OpenHW Group Explained that RISC-V is Everywhere
Rick O’Connor, President and CEO at OpenHW Group, shared that “there isn’t any software package today in the open source community and probably in the commercial community that does not have RISC-V project activity underway in some way, shape, or form.”
He also said that RISC-V gives companies vendor independence: “When you chose RISC-V, you’re choosing an architecture, you’re not choosing a vendor. There are multiple vendors—commercial, open source, and somewhere in between—design services that can potentially help you with architecting the system.”
Ongoing RISC-V Momentum
As Redmond summed it up, the key takeaway from the panel was that “RISC-V is truly inevitable.” There are more than 10 billion RISC-V cores on the market today and the “depth of investment that RISC-V is garnering from the smallest of startups to the largest multinationals is absolutely incredible,” as Redmond said.
We have many more events coming up, so we encourage you to check them out to hear about the latest RISC-V developments from members across different industries and geographies. Next up is the RISC-V Summit China, taking place Aug. 23-25 in Beijing and virtually. After that we have the RISC-V Summit, which will be held from Nov. 7-8 (plus a Member Day on Nov. 6) in Santa Clara, Calif.
Additionally, there is a lot of great content online from the recent RISC-V Summit Europe! You can browse our YouTube channel to watch the keynotes, panels, and technical sessions from the EU Commission, EuroHPC, European Space Agency (ESA), and many other organizations.