Project Snapshot
Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards and Technology (NIST) advancing to the fourth round of PQC standardization. One of the leading candidates is Hamming Quasi-Cyclic (HQC), which received a significant update on February 23, 2024. This update, which introduces a classical dense-dense multiplication approach, has no known dedicated hardware implementations yet. The innovative Core-V eXtension InterFace (CV-X-IF) is a communication interface for RISC-V processors that significantly facilitates the integration of new instructions to the Instruction Set Architecture (ISA), through tightly connected accelerators. In this paper, we present a TightlY-coupled accelerator for RISC-V for Code-based cryptogrAphy (TYRCA), proposing the first fully tightly-coupled hardware implementation of the HQC-PQC algorithm, leveraging the CV-X-IF. The proposed architecture is implemented on the Xilinx Kintex-7 FPGA. Experimental results demonstrate that TYRCA reduces the execution time by 94% to 96% for HQC128, HQC-192, and HQC-256, showcasing its potential for efficient HQC code-based cryptography.
In Their Own Words
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Meet the Authors
Alessandra Dolmeta
PhD Student in Electronic Engineering at Politecnico di Torino in Italy
Alessandra Dolmeta is currently pursuing the Ph.D. degree with the Electronics and Telecommunications Department, Politecnico di Torino. Her research interests include the design of hardware architectures for Post-Quantum Cryptography integrated into RISC-V, to speed up and optimize PQC algorithms.
Stefano Di Matteo
Research Engineer at CEA-Leti in France
Stefano Di Matteo received his master’s and Ph.D. degrees from the University of Pisa in 2019 and 2023, respectively. He is currently a junior chair in hardware implementation of Post-Quantum Cryptography at CEA in Grenoble. His research interests include hardware implementation of PQC with countermeasures against physical attacks, RISC-V architectures, and Instruction
Emanuele Valea
Researcher in Hardware Security at CEA-LIST in France
Emanuele Valea received the master’s degree in electronic engineering from Politecnico di Torino, Italy, in 2016, and the PhD degree in microelectronics from the University of Montpellier, France, in 2020. He is currently a researcher at CEA LIST, Grenoble, France. His research interests include hardware security and trust, cryptographic primitives for microelectronics and security-related aspects of VLSI testing and reliability.
Maurizio Martina
Professor at Politecnico di Torino in Italy
MAURIZIO MARTINA (Senior Member, IEEE) received the Dr.-Ing. and Ph.D. degrees in electronic engineering and electronic and communications engineering from the Politecnico di Torino, Italy, in 2000 and 2004, respectively. He has been a Professor with the Electronics and Telecommunications Department, Politecnico di Torino, since 2014. He has published more than 100 publications and holds two patents. His research interests include computer architecture and VLSI design of digital integrated circuits for image and video coding, forward error correction, cryptography, and artificial intelligence. He served as an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS and as a Guest Editor of several special issues, including BioCAS 2017 Special Issue in IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS and ISCAS 2023 Special Issue in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS. He has been part of the organizing and technical committee of several IEEE conferences, including BioCAS 2017, AICAS 2020, and PRIME 2023.
Guido Masera
Professor at Politecnico di Torino in Italy
GUIDO MASERA (Senior Member, IEEE) received the Dr.-Ing. (summa cum laude) and Ph.D. degrees in electronic engineering from the Politecnico di Torino, Italy. He has been a Professor with the Electronics and Telecommunications Department, Politecnico di Torino, since 1992. His research interests include several aspects in the design of digital integrated circuits and systems, with a special emphasis on high-performance architectures for communications, forward error correction, image and video coding, cryptography, and hardware accelerators for machine learning. He has more than 200 publications, two patents, and was a designer of several ASIC components. He is an Associate Editor of Electronics (MDPI) and a Former Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, and the IET Circuits, Devices & Systems
Carmona Mikael
Head of Hardware Security at CEA-LIST in France
Mikael Carmona is an engineer (Grenoble INP, 2007), agrégé in mathematics (2007), and PhD in signal processing (Grenoble INP, 2011). Researcher at CEA-Leti from 2011 to 2015 in the field of sensor networks, he co-founded the start-up Morphosense as CTO. He mainly contributes to the establishment and execution of the company’s Technological, Product and Operational roadmaps. In 2021, he joined the Cybersecurity department of CEA-Leti and operates in the fields of post-quantum cryptography and random number generators. He took charge of the Component Security Laboratory from 2022 to 2025. He is currently Head of the Cybersecurity department of CEA-Leti.
Loiseau Antoine
Researcher engineer at CEA-Leti in France
Antoine Loiseau is a researcher engineer and PhD in cryptography (Ecole de Mines de Saint-Etienne, 2019). He has been an engineer in cryptography from 2014-2017 for different companies like Inside Secure or Maxim Integrated. Researcher at CEA-Leti since 2017 in the field of cryptography for embedded systems and side channel security, he contributes to different research program for Post-Quantum Cryptography and supervises PhD students in the field.