Grande Risco 5
Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.
Cores
RISCY-SEECS
RISCY-SEECS is a 5-stage, single-issue, in-order CPU which implements the 32-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA...
AI Cores
At OpenMachine, we specialize in high-performance AI engines tailored for your chip, chiplet, RISC-V SoC, ASIC, and FPGA needs. Based in San Francisco and backed by Mozilla, we are committed...
Indian Institute of Science, Bangalore DESE
I2SRV64-SS (64-bit Superscalar Out-of-Order RISC-V Processor) This is a synthesizable and parameterizable RV64GC RISC-V core written in the Verilog hardware construction language, implemented and tested on Xilinx Virtex-7 FPGA VC707...
naitoultit Nordine
Exchange
Risco 5
Risco 5 is an open source processor core that implements the RV32I instruction set of the RISC-V architecture. It was developed for academic use and as the main core in...
first-riscv
cores