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Server-class RISC-V Core Unveiled by Ventana at RISC-V Summit | Aaron Carman, All About Circuits
Efficient Trace In RISC-V | Ed Sperling, Semiconductor Engineering
How RISC-V has become a viable third processor architecture | Dean Takahashi, Venture Beat
RISC-V Adds Support For Persistent Memory Devices In Linux 6.2 | Michael Larabel, Phoronix
Europe to Dish out €270 Million to Build RISC-V Hardware and Software | Agam Shah, HPC Wire
Imagination’s RISC-V gambit reaches its next level | Majeed Ahmad, EDN“RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes | Jeff Child, All About Circuits
New CAES, IAR Systems Partnership Brings NOEL-V Support to IAR Embedded Workbench
Qualcomm talks up RISC-V, roasts ‘legacy architecture’ amid war with Arm | Dylan Martin, The RegisterSolutions Disclosed at RISC-V Summit: Security, Verification, and More | Jake Hertz, All About Circuits
A Growing Ecosystem for Intel Pathfinder for RISC-V | Intel Pathfinder for RISC-V, EE Times India
New Dev Platforms Bring RISC-V to the Forefront of Innovation (Part 2) | Cabe Atwell, Electronic Design
SiFive X280 RISC-V Processor Gets Scalability, Trust Updates | Todd R. Weiss, Futurum Research
Espressif Launches ESP Privilege Separation, Giving the ESP32-C3 a Secure Split Personality | Gareth Halfcree, Hackster.io
Digi-Key at Embedded World with OpenHardware Group | Digi-Key, Electronic Specifier
De-RISC: A complete RISC-V based space-grade platform | Wessman, Nils-Johan Malatesta, Fabio Ribes, Stefano Andersson, Jan García Vilanova, Antonio Masmano Tello, Miguel Nicolau Gallego, Vicente Gómez Molinero, Paco Le Rhun, Jimmy Alcaide Portet, Sergi Cabo Pitarch, Guillem Bas Jalón, Francisco Benedicte Illescas, PedroMés, Mazzocchetti, Fabio Abella Ferrer, Jaume
Codasip adds Veridify Secure Boot to RISC-V Processors | Veridify Security
Full RISC-V and CMake support added to NECTO Studio 2.0 IDE from MIKROE | Neil Tyler, New Electronics
Freier Befehlssatz als Basis für GPU | Johannes Hiltscher, Golem
Elektor Magazine at Embedded World 2022 | Elektor Magazine
XtremeEDA to enable IoT security deployment with Crypto Quantique’s solution using Codasip’s RISC-V processor | Design and ReuseRISC-V International emits more open CPU specs | Liam Proven, The Register
ESP32-C5 RISC-V IoT MCU supports dual-band WiFi 6, Bluetooth 5.0 LE | Jean-Luc Aufranc, CNX Software
RISC-V’s CTO on the Art of Herding Cats | Junko Yoshida, The Ojo – Yoshida Report
Server-class RISC-V Core Unveiled by Ventana at RISC-V Summit | Aaron Carman, All About CircuitsIn a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a series of processors positioned to offer…
Efficient Trace In RISC-V | Ed Sperling, Semiconductor EngineeringSystems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks…
How RISC-V has become a viable third processor architecture | Dean Takahashi, Venture BeatThe economy and the event business aren’t strong, but the RISC-V Summit drew about 1,000 people to San Jose, California, this week to hear the latest on…
RISC-V Adds Support For Persistent Memory Devices In Linux 6.2 | Michael Larabel, PhoronixThe RISC-V processor architecture changes were merged this week for the Linux 6.2 cycle. While RISC-V has been seeing a lot of new kernel development in recent…
Europe to Dish out €270 Million to Build RISC-V Hardware and Software | Agam Shah, HPC WireThe European Union will release €270 million in funds as it tries to attain technology independence by building chips based on the open RISC-V instruction…
Imagination’s RISC-V gambit reaches its next level | Majeed Ahmad, EDNImagination Technologies, a supplier of GPUs, artificial intelligence (AI) accelerators and CPU cores, has consolidated its commitment to the rapidly expanding open-standard RISC-V ecosystem by…
“RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes | Jeff Child, All About CircuitsAt the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world. The RISC-V Summit, running from December 12…
New CAES, IAR Systems Partnership Brings NOEL-V Support to IAR Embedded WorkbenchColorado Springs, Colo. and Stockholm, Sweden — IAR Systems, a leader in software and services for embedded development, and CAES Gaisler Products, a leader in fault-tolerant processor development,…
Qualcomm talks up RISC-V, roasts ‘legacy architecture’ amid war with Arm | Dylan Martin, The RegisterCOMMENT As Qualcomm tries to fight off a lawsuit from Arm demanding Qualcomm destroy its custom cores, the Snapdragon giant has signaled it may have a…
Solutions Disclosed at RISC-V Summit: Security, Verification, and More | Jake Hertz, All About CircuitsAt this year’s RISC-V Summit, stakeholders rolled out solutions revolving around verification, security, and software-defined SoCs. This week is the annual RISC-V Summit in San Jose, CA,…
A Growing Ecosystem for Intel Pathfinder for RISC-V | Intel Pathfinder for RISC-V, EE Times IndiaIntel Pathfinder for RISC-V has launched an exciting array of new features as well as continues to grow a healthy ecosystem around the initiative. Designed…
New Dev Platforms Bring RISC-V to the Forefront of Innovation (Part 2) | Cabe Atwell, Electronic DesignPart 2 looks at more companies that are on track to adopt the RISC-V architecture for new applications ranging from robotics to home automation. This…
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SiFive X280 RISC-V Processor Gets Scalability, Trust Updates | Todd R. Weiss, Futurum ResearchThe News: The latest SiFive X280 RISC-V processor is getting several significant feature updates, including increased scalability up to a 16-core cache-coherent environment, new SiFive…
Espressif Launches ESP Privilege Separation, Giving the ESP32-C3 a Secure Split Personality | Gareth Halfcree, Hackster.ioEspressif has announced a shiny new feature for its ESP32 microcontroller family, starting with the ESP32-C3: privilege separation, designed boost security by keeping user applications…
Digi-Key at Embedded World with OpenHardware Group | Digi-Key, Electronic SpecifierAt Embedded World 2022, on the Digi-Key booth, Paige West speaks with Rick O’Connor, President, and CEO at OpenHardware Group about the company's RISC-V-based CORE-V…
De-RISC: A complete RISC-V based space-grade platform | Wessman, Nils-Johan Malatesta, Fabio Ribes, Stefano Andersson, Jan García Vilanova, Antonio Masmano Tello, Miguel Nicolau Gallego, Vicente Gómez Molinero, Paco Le Rhun, Jimmy Alcaide Portet, Sergi Cabo Pitarch, Guillem Bas Jalón, Francisco Benedicte Illescas, PedroMés, Mazzocchetti, Fabio Abella Ferrer, JaumeThe H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain…
Codasip adds Veridify Secure Boot to RISC-V Processors | Veridify SecurityCodasip, the leader in customizable RISC-V processor IP and processor design automation, today announced that quantum-resistant secure tools from Veridify Security Inc. are now available…
Full RISC-V and CMake support added to NECTO Studio 2.0 IDE from MIKROE | Neil Tyler, New ElectronicsVersion 2.0 adds full RISC-V support and CMake project-native support, plus significant Editor, Designer & Code Model improvements. The NECTO Studio 2.0 is a complete,…
Freier Befehlssatz als Basis für GPU | Johannes Hiltscher, GolemSeit 2009 entwickelt Think Silicon in Griechenland Grafikhardware. Auf der Embedded World 2022 in Nürnberg stellt das Unternehmen seine Produkte vor. Während die Nema-GPUs für…
Elektor Magazine at Embedded World 2022 | Elektor MagazineDownload the digital version featuring RISC-V.
XtremeEDA to enable IoT security deployment with Crypto Quantique’s solution using Codasip’s RISC-V processor | Design and ReuseXtremeEDA is a leading North American design and functional verification services provider to the ASIC, SoC, and FPGA hardware industry today announced that it has…
RISC-V International emits more open CPU specs | Liam Proven, The RegisterRISC-V International has grown its pile of royalty-free, open specifications, with additional documents covering firmware, hypervisors, and more. RISC-V – pronounced "risk five", and not…
ESP32-C5 RISC-V IoT MCU supports dual-band WiFi 6, Bluetooth 5.0 LE | Jean-Luc Aufranc, CNX SoftwareEspressif Systems ESP32-C5 is an upcoming wireless RISC-V microcontroller for IoT applications that supports dual-band (2.4 & 5.0 GHz) WiFi 6 connectivity as well as…
RISC-V’s CTO on the Art of Herding Cats | Junko Yoshida, The Ojo – Yoshida ReportThe measure of success for an open-source community such as RISC-V can be memberships, number of shipped products or revenues generated by its member companies.…