Blog

In this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how chip designers design various chips, such as simple embedded microcontrollers…

By: Matej Antonijevic (TASKING) Developers who have struggled with achieving real-time performance and security in embedded systems can now look forward to unprecedented capabilities thanks to Microchip's PolarFire® System-on-Chip Field-Programmable…

By: Frank Riemenschneider, Senior Marketing Engineer at Lauterbach GmbH Microchip's PolarFire® System-on-Chip Field-Programmable Gate Array (SoC FPGA) family implements a total of five SiFive U54 and SiFive E51 64-bit RISC-V…

By Wenbo Yin, Vice President of IC Design, TetraMem Inc. Introduction The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications has driven an unprecedented demand…

NX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores San Jose, CA – Sep. 11, 2024— Rivos Inc., a RISC-V Premier…

The path to success for an IT career is often paved with curiosity, dedication and a willingness to evolve. Victor Labián Carro, RVFA, now a Customer Engineer at Axelera AI,…

Brazil is making significant strides in developing artificial intelligence (AI) infrastructure, focusing primarily on High-Performance Computing (HPC), semiconductor technology, and large language models (LLMs). The country’s 4 billion USD initiatives…

The weather might have been scorching, but the networking at Hot Chips was on fire! RISC-V was front and center, showcasing member boards, and fielding questions and engaging with RISC-V…

Four software leaders were honored at RISC-V Summit Europe 2024 for their remarkable contributions to the RISC-V Community. Let’s celebrate their induction into the RISC-V Hall of Fame and explore…