What’s New

Dec 20, 2024

Exploring RISC-V ISA Developments and Technical Highlights from 2024

Dec 19, 2024

RISC-V 2024: A Year of Global Growth and Innovation

Dec 18, 2024

[VIDEO] Why the ESP32 C6 DevKit is Perfect for RISC-V Learning

Dec 17, 2024

Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores

Dec 17, 2024

My Journey with the RISC-V Mentorship | Sailing Downstream II

Dec 16, 2024

Accelerating SoC Development: A Collaborative Approach by Tenstorrent and Ashling

Dec 16, 2024

Gaisler to build 7nm RISC-V chip for space

Dec 16, 2024

[VIDEO] Explore the RISC-V in action and how it’s shaping the future of computing.

Dec 13, 2024

XuanTie Co-Processor Interface Solution: A Bridge to Efficient Collaborative Computing

Dec 13, 2024

Jmem Tek unveils first quantum-secure RISC-V chip

Dec 12, 2024

RISC-V CEO Calista Redmond resigns after 5+ years of progress

Dec 12, 2024

British startup launches low-power RISC-V processor design to address the twin problems of memory and energy; promises up to 50% faster calculation speeds

Dec 12, 2024

Tenstorrent powers first automotive RISC-V AI accelerator chiplet

Dec 11, 2024

Semidynamics RISC-V AI IP selected for LLM applications

Dec 11, 2024

SiFive Empowers AI at Scale with RISC-V Innovation

Dec 11, 2024

TWAIN Working Group joins RISC-V International community to develop secure IoT document scanning solutions

Dec 11, 2024

SiFive HiFive Premier P550 RISC-V Price Lowered, Ubuntu 24.04 Support Ready

Dec 9, 2024

Semidynamics RISC-V AI IP selected for LLM applications

Dec 4, 2024

SiFive Empowers AI at Scale with RISC-V Innovation

Dec 4, 2024

[VIDEO] RISC-V Drives the Future: From Software-Defined Vehicles to ADAS to AI (MIPS Podcast)

Dec 2, 2024

Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M

Nov 22, 2024

Enhancing the Future of AI/ML with Attached Matrix Extension

Nov 20, 2024

How RISC-V standards are changing the world [Q&A]

Nov 20, 2024

Interview with Calista Redmond, CEO, RISC-V International

Nov 20, 2024

Meet Andrea Gallo, RVFA: A Senior IT Leader’s Career Pivot

Nov 19, 2024

RISC-V for HPC at SC24

Nov 18, 2024

Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC

Nov 15, 2024

Openchip, NEC and Barcelona Supercomputing Center studying Collaboration to develop Next Generation Supercomputers based on RISC-V

Nov 15, 2024

Triton kernel performance on RISC-V CPU

Nov 14, 2024

DeepComputing Launches Early Access Program for DC-ROMA RISC-V Mainboard for Framework Laptop 13

Nov 12, 2024

VIDEO: RISC-V Design Innovations with Custom Extensions | Synopsys

Nov 12, 2024

MIPS releases RISC-V CPU for autonomous vehicles

Nov 11, 2024

The Convergence of Functional with Safety, Security and PPA Verification

Nov 8, 2024

Stream Computing Provides Smart Community Services Based on RISC-V Computing Power and LLMs

Nov 7, 2024

Stream Computing RISC-V Matrix Extension Open Source Project Upgrades to Version 0.5, Supporting Vector+Matrix Implementation

Nov 6, 2024

Highlights from the RISC-V Summit 2024

Nov 6, 2024

Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoT

Nov 4, 2024

How to Share Your Work and See What Others Are Building On RISC-V

Oct 31, 2024

Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference

Oct 30, 2024

Interview with RISC-V International: High-Performance Chips, AI, Ecosystem Fragmentation, and The Future

Oct 30, 2024

RISC-V Oozes Confidence with RVA23 Profile Ratification

Oct 30, 2024

4 Highlights From the RISC-V Summit North America

Oct 30, 2024

DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop

Oct 29, 2024

RISC-V User-Space Pointer Masking Appears Ready For Linux 6.13

Oct 29, 2024

Denso seals Quadric deal for RISC-V AI core

Oct 29, 2024

RISC-V CPU demoed with RX 7900 XTX GPU in Debian Linux — AMD flagship GPU paired with Milk-V Megrez board and SiFive P550 cores

Oct 29, 2024

RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source Innovations

Oct 28, 2024

Codasip Unveils L730 Automotive-Grade Embedded RISC-V Core

Oct 28, 2024

Life Lessons from the First Half-Century of My Career

Oct 25, 2024

Nvidia to ship a billion of RISC-V cores in 2024

Oct 25, 2024

Nvidia projected to ship roughly a billion RISC-V cores in its products by year’s end

Oct 23, 2024

RISC-V reaches milestone with RVA23 profile ratification

Oct 23, 2024

RVA23 Profile ratification bolsters RISC-V software ecosystem

Oct 23, 2024

Ashling and Embecosm Announce Optimized Software Development Toolchain for Akeana at RISC-V Summit North America, 2024

Oct 21, 2024

SiFive HiFive Premier P550 Development Boards Now Shipping

Oct 21, 2024

SEGGER’s Ozone offers enhanced debugging with RISC-V Semihosting

Oct 21, 2024

RISC-V Announces Ratification of the RVA23 Profile Standard

Oct 11, 2024

Chile’s First Steps with RISC-V: Paving the Way for Technological Innovation

Oct 11, 2024

著名的 Box86/Box64 模拟器现在有了更好的 RISC-V RVV 1.0 支持，性能提升显著（英文转载）

Oct 11, 2024

RISC-V Summit North America 2024: Keynotes and Industry Tracks

Oct 9, 2024

Optimizing the RISC-V Backend

Oct 9, 2024

Are IoT Hardware Vendors Finally Going Open Source?

Oct 9, 2024

Software-defined processors: the promise of RISC-V

Oct 9, 2024

Don’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!

Oct 8, 2024

LDRA extends RISC-V support, adds QNX

Oct 8, 2024

CEO interview: Chips Act boost for RISC-V

Oct 8, 2024

Synopsys RISC-V ARC-V processor IP gets Lauterbach debug and trace

Oct 8, 2024

Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEE

Oct 8, 2024

AI/ML Innovations at RISC-V Summit North America: A Track to Watch

Oct 3, 2024

Introducing fast RISC-V interrupts support in Renode for real time applications

Oct 3, 2024

KVM expansion card utilizes RISC-V CPU architecture for enhanced remote PC management — Sipeed NanoKVM-PCIe now available for pre-order starting at $40

Oct 2, 2024

RISC-V Summit to Feature, AI, Auto, RTOS and Many More Key Topics

Oct 1, 2024

Join Us for the RISC-V Hackathon at Summit North America 2024!

Sep 30, 2024

[VIDEO] An Open-Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards

Sep 30, 2024

[VIDEO] Accelerate your adoption of RISC-V with CORE-V-VERIF

Sep 30, 2024

Eclipse 上游初步支持 RISC-V，每日构建镜像已经可以下载试用

Sep 27, 2024

RISC-V Processor Design – Free YouTube Course by Maven Silicon

Sep 27, 2024

Get Started With Real-Time Systems Using Microchip’s PolarFire® SoC FPGA and TASKING Debug and Analyze Tools

Sep 27, 2024

Debugging of PolarFire® SoC FPGAs Made Easy with Lauterbach’s TRACE32® Tools

Sep 27, 2024

Box64 Adds Initial Support for RISC-V Vector 1.0 (RVV) Extension, Achieves up to 300% Performance Boost, Code Now Open-Source and Merged Upstream

Sep 26, 2024

TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

Sep 26, 2024

TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

Sep 25, 2024

Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC

Sep 25, 2024

Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC

Sep 24, 2024

Andes Technology is Expanding RISC-V’s Horizons in High-Performance Computing Applications

Sep 24, 2024

[VIDEO] Accelerating RISC-V testbench development with open source RISC-V RTL and emulation

Sep 24, 2024

[VIDEO] A Holistic Approach to RISC-V Processor Verification

Sep 24, 2024

[VIDEO] The Future of Compute

Sep 24, 2024

Box64 初步支持 RISC-V Vector 1.0 (RVV) 扩展，最高 300% 性能提升，代码已开源并合入上游（upstream）

Sep 24, 2024

Codeplay Brings RISC-V Support to the oneAPI Construction Kit

Sep 23, 2024

RISC-V is Built for Artificial Intelligence and SiFive Solutions for AI

Sep 23, 2024

SiFive unveils RISC-V chip design for high-performance AI workloads

Sep 23, 2024

[VIDEO] RISC-V Taipei Day 2024 – Reshape the Future with AI

Sep 23, 2024

VyperCore plans 5nm RISC-V server chip and card

Sep 21, 2024

Bitluni’s Magnetic LED Matrix Build Showcases Clever RISC-V Programming

Sep 18, 2024

How RISC-V Changes the Global Landscape of AI and ML

Sep 18, 2024

SiFive Highlights Key Inflection Points Driving RISC-V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration

Sep 18, 2024

Accelerating RISC-V Processor Verification: A Co-Simulation Strategy

Sep 18, 2024

Lauterbach adds debug and trace support for Renesas 32-bit-RISC-V microcontrollers

Sep 18, 2024

[PODCAST] Pioneering RISC-V and Defining Software-Defined Vehicles

Sep 17, 2024

Leveraging a Passion for Logic into a RISC-V Career

Sep 16, 2024

Tales from Beyond the Register Map

Sep 16, 2024

EDACafe Bunker Broadcast with Calista Redmond

Sep 16, 2024

How RISC-V Changes the Global Landscape of AI and ML

Sep 16, 2024

3 steps to shrinking your code size, your costs, and your power consumption

Sep 13, 2024

Olimex’s One-Euro RVPC Single-Board Computer Goes Up for Sale Next Week

Sep 13, 2024

[VIDEO] The Saturn Vector Unit: Design of a Fully Compliant Open-Source RISC-V Vector Unit (Jerry Zhao)

Sep 12, 2024

RISC-V International Newsletter – September 2024

Sep 10, 2024

TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

Sep 10, 2024

Semidynamics on major recruitment drive for RISC-V software engineers

Sep 9, 2024

Advancing AI the Brazilian Way: Fostering Innovation Through Collaboration and Open Standards

Sep 6, 2024

Hot Chips and Even Hotter Connections: RISC-V is Everywhere!

Sep 6, 2024

Wine Down Friday with RISC-V’s Calista Redmond

Sep 5, 2024

Trailblazers: Board of Directors Software Award Winners 2024

Sep 4, 2024

RISC-V Builds the Backbone of Three New Consumer Devices

Sep 3, 2024

STMicroelectronics Joins Quintauris as Sixth Shareholder

Sep 3, 2024

Orange Pi Embraces RISC-V with the Raspberry Pi-Like Orange Pi RV Single-Board Compute

Sep 3, 2024

RISC-V Enables Performant and Flexible AI and ML Compute

Sep 2, 2024

SiFive and Arkmicro Accelerate RISC-V Adoption in Automotive Electronics with SiFive’s Automotive IP for the High-end SoC Market

Aug 30, 2024

Jesse Taube Gets Linux Up and Running on the Raspberry Pi RP2350’s Hazard3 RISC-V Cores

Aug 30, 2024

RISC-V International N-Trace TG Milestone

Aug 30, 2024

Resiltech To Develop Test Libraries for Andes ASIL-D RISC-V Processor IP

Aug 29, 2024

Exploring the Amazing RISC-V Summit China 2024

Aug 29, 2024

Resiltech and Andes Technology Announce Collaboration to Deliver Advanced STL Solutions for Andes Automotive-Grade RISC-V Processor IP

Aug 29, 2024

RISC-V World Tour; Munich, Hangzhou, Santa Clara…

Aug 28, 2024

SEALSQ Testing Its QS7001 RISC V Quantum-Resistant Platform

Aug 28, 2024

C28 PQShield and SiFive Collaborate to Advance Post-Quantum Cryptography in RISC-V

Aug 28, 2024

Introducing the Newly Elected RISC-V Board of Directors Officers and Members

Aug 27, 2024

RISC-V SoC Design Workshop by Maven Silicon in Malaysia & Singapore

Aug 27, 2024

DeepComputing Opens Pre-Orders for the SpacemIT K1 RISC-V-Powered DC-ROMA RISC-V Pad II Tablet

Aug 27, 2024

Geniatech actively lays out RISC-V ecosystem to accelerate industrial IoT development

Aug 27, 2024

reCamera modular AI camera features SG2002 RISC-V AI SoC, supports interchangeable image sensors and baseboards

Aug 27, 2024

RISC-V Summit North America T-Shirt Design Contest—And the Winner Is…!

Aug 27, 2024

XiangShan High-Performance RISC-V Processors at Hot Chips 2024

Aug 27, 2024

Tenstorrent’s Blackhole Chips Boast 768 RISC-V Cores and Almost as Many FLOPS

Aug 26, 2024

CHERIoT: A Study in CHERI

Aug 23, 2024

Join the ranks of RISC-V Advocates!

Aug 22, 2024

Infineon Harnesses the Power of RISC-V for Next-Generation Automotive MCU Innovation

Aug 22, 2024

Featured Work: Microarchitecture Security: The Spectre Affair

Aug 21, 2024

New RISC-V Innovations Lead AI to Open Standard

Aug 21, 2024

[VIDEO] Join us for This Year’s RISC-V Summit

Aug 20, 2024

Unlocking the Potential of Your RISC-V Laptop: The DC-ROMA Laptop II

Aug 20, 2024

SEALSQ introduces new RISC-V secure hardware platform for IoT security

Aug 20, 2024

DeepComputing Announces the Launch of the DC-ROMA RISC-V Pad II!

Aug 20, 2024

Exploring the RISC-V Summit 2024: Technical Sessions Announced

Aug 20, 2024

Microchip unveils PIC64 family of RISC-V multicore processor chips for Earth and for space

Aug 19, 2024

[VIDEO] Checking Out The Teensy Tiny RISC-V NanoKVM!

Aug 16, 2024

Harnessing power of RISC-V, Generative AI: Expert hardware security architect Avani Dave’s vision

Aug 14, 2024

RISC-V cluster IP for data centre SoCs and chiplets

Aug 14, 2024

SiFive moves into RISC-V datacentre AI processor IP

Aug 14, 2024

Semiconductor Symposium Puts Spotlight on RISC V, HPC

Aug 14, 2024

Akeana exits stealth mode with comprehensive RISC-V processor portfolio

Aug 14, 2024

Trailblazers: Board of Directors Technical Award Winners 2024

Aug 14, 2024

SiFive Announces New High-performance RISC-V Datacenter Processor for Demanding AI Workloads

Aug 13, 2024

With $100M raised, Akeana unveils new RISC-V chip designs

Aug 13, 2024

Raspberry Pi Launches New RP2350 MCU and Pico 2 Dev Board with RISC-V Support

Aug 13, 2024

Akeana exits stealth mode with comprehensive RISC-V processor portfolio, challenging the semiconductor industry status quo

Aug 13, 2024

SpacemiT Key Stone K1 AI CPU has been adapted to the Fedora

Aug 12, 2024

[VIDEO] Synopsys & TASKING RISC-V Solutions for Safety & Security Critical Automotive Apps

Aug 12, 2024

deepin 23丨RISC-V New Era Leading Desktop Operating System Innovation

Aug 12, 2024

More than 1,300 Attendees Expected at RISC-V Summit China Next Week

Aug 12, 2024

[VIDEO] What Are the Benefits of RISC-V?

Aug 9, 2024

[VIDEO] Raspberry Pi RP2350 – New Microcontroller Chip with Arm CPUs and RISC-V CPUs 🤯

Aug 9, 2024

Raspberry Pi launches its first RISC-V multicore chip

Aug 8, 2024

Microchip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applications

Aug 8, 2024

Raspberry Pi Launch New RP2350 Microcontroller and Pico 2 Development Board with RISC-V Support

Aug 6, 2024

RISC-V 中国峰会议程初版已在官网公布，8月12日形成最终版

Aug 6, 2024

Open source System on Module with Microchip PolarFire SoC

Aug 2, 2024

[VIDEO] Developing the RISC-V Framework Laptop Mainboard

Aug 2, 2024

Canonical Adds Microchip’s New PIC64GX to Its List of Ubuntu-Supported RISC-V Platforms

Jul 31, 2024

Defining RISC-V CPUs in Renode simulation with custom instructions and extensions

Jul 29, 2024

Debugging of RISC-V-Based Chips Made Easy

Jul 26, 2024

Leveraging Safety Processor Expertise to Develop RISC-V Based Automotive Implementations

Jul 26, 2024

Wuhan Sets Up Open-Source RISC-V Innovation Hub for Next-Gen Chips

Jul 26, 2024

Lauterbach Supports Microchip’s PIC64GX RISC-V® MPUs

Jul 26, 2024

New Launch: Advanced RISC-V Courses | Maven Silicon

Jul 24, 2024

Ashling announces RiscFree™ C/C++ SDK support for Microchip Technologies’ PIC64GX RISC-V ® -based multicore MPUs

Jul 24, 2024

Imagination Technologies announces new capital investment from Fortress Investment Group

Jul 22, 2024

How ChipFlow is Making the Impossible Possible

Jul 22, 2024

Microchip Unveils Industry’s Highest Performance 64-bit HPSC Microprocessor (MPU) Family for a New Era of Autonomous Space Computing

Jul 22, 2024

Ashling announces RiscFree™ C/C++ SDK support for India’s C-DAC VEGA RISC-V-based Multi-core Microprocessors

Jul 22, 2024

Trillions of Cycles per Day: How SiFive Boosts IP and Software Validation with Synopsys HAPS Prototyping System

Jul 19, 2024

How Early Power Analysis Drives Energy-Efficient RISC-V Designs

Jul 19, 2024

Axelera AI Raises $68 Million Series B Funding to Accelerate Next-Generation Artificial Intelligence

Jul 18, 2024

RISC-V Shows Ambitious Prospects in Europe

Jul 18, 2024

Tenstorrent’s RISC-V-based Wormhole AI accelerators are available for pre-order today — pre-built workstations start at $12,000

Jul 17, 2024

Unpacking the CanMV K230 RISC-V board

Jul 16, 2024

RISC-V power controller adds flash memory

Jul 16, 2024

DAC 2024 – Showcasing the future of RISC-V through EDA

Jul 16, 2024

Navigating the RISC-V Ecosystem

Jul 12, 2024

Microchip starts 64bit PIC64 family with RISC-V

Jul 12, 2024

RT-Thread: Pioneering Real-Time Operating System for RISC-V

Jul 12, 2024

RISC-V, the Linux of the chip world, is starting to produce technological breakthroughs

Jul 11, 2024

RISC-V Fosters Collaboration in the Chip Race

Jul 11, 2024

[VIDEO] RISC V Ecosystem Panel | Open Source is Transforming AI and Hardware

Jul 11, 2024

[VIDEO] RISC V Ecosystem Panel | Unlocking the RISC V Application Processor Potential

Jul 11, 2024

SEALSQ RISC-V Semiconductors is Pioneering Sustainability Through Decentralized Processing

Jul 10, 2024

Microchip Technology Expands Processing Portfolio to Include Multi-Core 64-bit Microprocessors

Jul 9, 2024

Microchip Unveils Industry’s Highest Performance 64-bit HPSC Microprocessor (MPU) Family for a New Era of Autonomous Space Computing

Jul 9, 2024

Microchip Now Offers Full Microprocessor Spectrum, From 8- to 64-bit MPUs

Jul 9, 2024

Breker Brings RISC-V Verification to the Next Level #61DAC

Jul 9, 2024

Eight core RISC-V processor and TSN switch for AI space designs

Jul 9, 2024

Microchip starts 64bit PIC64 family with RISC-V

Jul 9, 2024

RISC-V Thrives Through Research, International Collaboration

Jul 8, 2024

Stealth startup Vybium developing European RISC-V AI accelerator

Jul 8, 2024

[VIDEO] M5: RISC-V Instruction Set Architecture | RISC CPU Performance Explained

Jul 3, 2024

DAC 61: EDA addressing growing system complexity

Jul 2, 2024

Introducing the Mini-ITX motherboard ‘Milk-V Jupiter’ equipped with a RISC-V processor

Jul 1, 2024

Desk of Ladyada – It’s a RISC-V kinda weekend #DeskOfLadyada #Adafruit

Jul 1, 2024

RISC-V Summit Europe 2024

Jul 1, 2024

METASAT Project Celebrates 18 Months of Innovation: Key Developments in Satellite Technology

Jun 30, 2024

[VIDEO] RISC-V NAS: BPI-F3 & OpenMediaVault

Jun 28, 2024

Stream Computing partners with VRULL and Software Ecosystems Solutions to build a richer software ecosystem for RISC-V AI application

Jun 28, 2024

Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich

Jun 27, 2024

RISC-V Summit Europe News—Processor IP, Verification Tools, and More

Jun 27, 2024

SiFive Essential Product Family Expanded at the RISC-V Summit Europe

Jun 27, 2024

RISC-V Verification: From Simulation To Formal

Jun 26, 2024

SiFive announces 4th-gen of popular essential product line to spur innovation across embedded applications

Jun 26, 2024

Accelerate RISC-V Verification Using Synopsys Cloud

Jun 26, 2024

Accelerate RISC-V Verification Using Synopsys Cloud

Jun 25, 2024

Developers Use RISC-V Stack Without Worrying About Local SRAMs, DMAs

Jun 25, 2024

ESWIN Computing Pairs SiFive CPU, Imagination GPU and In House NPU in Latest RISC-V Edge Computing SoC

Jun 25, 2024

RISC-V Summit: SiFive’s 4th generation embedded cores

Jun 25, 2024

DAC 2024 Day One: Designing Chiplets and AI with RISC-V

Jun 25, 2024

Semidynamics benchmarks 7bn parameter model on RISC-V AI IP

Jun 25, 2024

X-Silicon Introduces the World’s First Vulkan Driver Implementation for RISC-V, Enabling an entire Ecosystem of 3D Graphics, AI and Compute for Low-Power, Mobile, Edge and IOT Devices

Jun 25, 2024

RISC-V Summit Europe is Underway with 700+ Attendees Representing 40 Countries

Jun 25, 2024

SiFive Announces 4th Generation of Popular Essential Product Line to Spur Innovation Across Embedded Applications

Jun 25, 2024

Semidynamics benchmarks 7bn parameter model on RISC-V AI IP

Jun 25, 2024

Ashling announces RiscFree™ C/C++ SDK support for Renesas’s RISC-V-based R9AG021 MCUs

Jun 24, 2024

Industry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities

Jun 24, 2024

RISC-V International Names Andrea Gallo as VP, Technology

Jun 24, 2024

Ventana CEO to Deliver a Keynote at RISC-V Summit Europe

Jun 24, 2024

RISC-V International Names Andrea Gallo as VP, Technology

Jun 23, 2024

AI, Collaboration, Security and More: Women Speak on Key Topics at RISC-V Summit International

Jun 21, 2024

[VIDEO] Road to testing applications on RISC-V with QEMU and Fedora – DevConf.CZ 2024

Jun 21, 2024

Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024

Jun 20, 2024

RISC-V in Brazil: Leading the Open Compute Era in Latin America

Jun 20, 2024

Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage

Jun 20, 2024

Companies Rally RISC-V Support for AI and HPC Applications

Jun 20, 2024

[VIDEO] M1: RISC-V Overview | The Ultimate Guide to RISC-V Architecture

Jun 20, 2024

Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems

Jun 19, 2024

Sipeed Univels the Lichee Book 4A, a Notebook for the “RISC-V Explorer”

Jun 18, 2024

Functional safety static analysis tool for RISC-V

Jun 18, 2024

A RISC-V World First Independently Developed RISC-V Mainboard for a Framework Laptop from DeepComputing

Jun 17, 2024

[VIDEO] RISC-V Con 2024: “Leveraging RISC-V for hardware software co-design of low power AI accelerators”

Jun 16, 2024

[VIDEO] Banana Pi BPI-F3: Octa Core RISC-V SBC Running Bianbu OS

Jun 14, 2024

World’s first RISC-V Laptop gets a MASSIVE upgrade and equips with Ubuntu

Jun 13, 2024

[VIDEO] OpenHW Group CORE-V RISC-V open-source cores with CEO Florian ‘Flo’ Wohlrab at Computex 2024 Update

Jun 13, 2024

Lauterbach presents leading debug solutions at the RISC-V Summit in Munich

Jun 13, 2024

World’s first RISC-V Laptop gets a MASSIVE upgrade and equips with Ubuntu

Jun 13, 2024

Axiomise Heads to RISC-V Summit Europe June 25-27 in Munich

Jun 12, 2024

Codasip introduces best-in-class RISC-V core for power-efficient applications

Jun 11, 2024

[VIDEO] ANDES RISC-V CON Silicon Valley 2024

Jun 11, 2024

Arteris Selected by Esperanto Technologies to Integrate RISC-V Processors for High-Performance AI and Machine Learning Solutions

Jun 10, 2024

[VIDEO] Progress in Standardizing Cryptography Extensions for RISC-V Processors

Jun 10, 2024

First 32-bit low-power MCU with in-house RISC-V CPU core

Jun 10, 2024

RISC-V International Newsletter – June 2024

Jun 10, 2024

HPC on RISC-V a hot topic at the International Supercomputing Conference, Hamburg

Jun 7, 2024

SpacemiT Muse Pi is a single-board PC with SpacemiT M1 8-core RISC-V processor

Jun 7, 2024

My Top 10 Reasons to Attend RISC-V Summit Europe

Jun 6, 2024

Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel

Jun 6, 2024

Designing with RISC-V Using ChipInventor

Jun 5, 2024

RISC-V Summit China 2024: Details Now Available on Call for Proposals and Sponsorships

Jun 3, 2024

Getting started with RISC-V! | Soham Kulkarni | MumbaiFOSS 2024

Jun 3, 2024

Navigating the RISC-V landscape: unveiling the Embeetle IDE

Jun 3, 2024

Calligo Technologies Unveils Revolutionary World’s First Posit-enabled RISC-V CPU for General Purpose Computing

Jun 3, 2024

Rain AI Unveils Andes Technology as Its RISC-V Partner

Jun 1, 2024

2024 RISC-V中国峰会赞助方案公布，赞助预定渠道6月8日全球统一开启

Jun 1, 2024

2024 RISC-V 中国峰会演讲征集（CFP）

May 31, 2024

Andes Technology announces new SoC and development board

May 31, 2024

Seeking Sponsors for RISC-V Day Tokyo 2024!

May 30, 2024

Andes Technology Announced the QiLai SoC and the Voyager Development Board

May 30, 2024

Building a DIY 256-Core RISC-V computer

May 30, 2024

[VIDEO] The Magic of RISC-V Vector Processing

May 30, 2024

Exciting Announcements: Unveiling the Agenda for the 2024 RT-Thread Global Tech Conference!

May 30, 2024

UNVEILING THE TASKING RISC-V COMPILER | A Breakthrough regarding the development of FuSa and Cybersecurity compliant Software.

May 29, 2024

World’s first RISC-V multi-mode LTE chipset for 450MHz

May 28, 2024

Canonical releases Ubuntu 24.04 Server image for Milk-V Mars RISC-V SBC

May 28, 2024

Canonical enables Ubuntu on Milk-V Mars, a credit-card-sized RISC-V SBC

May 24, 2024

SEALSQ RISC-V Chips Adoption is Predicted to Get AI Boost Making it a Viable Competitor to Traditional GPUs

May 23, 2024

[VIDEO] FSCK 2024 – RISC-V – The Only Architecture You’ll Ever Need

May 21, 2024

[VIDEO] Master RISC-V Processors with Bluespec for Achronix FPGAs | Complete Guide & Insights

May 21, 2024

Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption

May 20, 2024

Edge AI to help RISC-V to take 25% of processor market

May 20, 2024

[VIDEO] How to bring up SYSGO’s PikeOS on a PolarFire® RISC-V SoC | SYSGO & Microchip

May 20, 2024

RISC-V adoption predicted to get AI boost — forecast shows 50% growth every year until 2030 for the open-standard ISA

May 17, 2024

Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem

May 17, 2024

RISC-V adoption will be accelerated by AI, according to new Omdia research

May 17, 2024

Keynote: Charting the AI-Powered Transformation in the Semiconductor Industry

May 15, 2024

Global and China Automotive RISC-V Chips Research Report 2024: Market Gains Momentum as Industry Trends Toward Customization and High-Performance Applications – ResearchAndMarkets.com

May 15, 2024

Esperanto Technologies and Rapidus Partner to Enable More Energy-Efficient Designs for the Coming “Post GPU Era”

May 15, 2024

May 14, 2024

14 Years of RISC-V: A Journey of Innovation and Firsts

May 14, 2024

Benchmarking The First RISC-V Cloud Server: Scaleway EM-RV1 Performance

May 14, 2024

New Automotive Grade Linux Platform Release Adds Cloud-Native Functionality, RISC-V Architecture and Flutter-Based Applications

May 13, 2024

Frontgrade Gaisler Leads the Way in RISC-V Processor Development for Space Applications

May 13, 2024

Custom RISC-V cores for GPS augmentation

May 13, 2024

Mindgrove Brings First Indigenously-Designed RISC-V MCU to India

May 9, 2024

New Automotive Grade Linux Platform Release Adds Cloud-Native Functionality, RISC-V Architecture and Flutter-Based Applications

May 9, 2024

Recent developments in the Zephyr port for RISC-V

May 2, 2024

The Rise of RISC-V and ISO 26262 Compliance

May 1, 2024

X- Silicon Announces a NEW Low-Power Open-Standard Vulkan-Enabled C-GPU™ – a RISC-V Vector CPU Infused with GPU ISA and AI/ML acceleration in a Single Processor Core

May 1, 2024

Radiation-Tolerant RISC-V FPGA for Linux in space

Apr 29, 2024

MEDIA ALERT: Calista Redmond, CEO of RISC-V International, to Speak at ESD Alliance 2024 CEO Executive Outlook

Apr 27, 2024

RISC-V 对技术和创新的影响

Apr 25, 2024

RISC-V Impact on Technology and Innovation

Apr 24, 2024

RISC-V for All!

Apr 23, 2024

Cooperation and Competition Behind the Scenes in the RISC-V Community

Apr 22, 2024

Here’s why RISC-V is so important

Apr 22, 2024

Exploring the Top Highlights of the RISC-V Booth at embedded world 2024

Apr 20, 2024

[VIDEO] Applications for the RISC-V Revolution – The Electropages Podcast with Bluespec, Inc

Apr 18, 2024

Compiler toolset for RISC-V in safety and security-critical automotive applications

Apr 18, 2024

Celebrating Women in the Global RISC-V Community

Apr 17, 2024

A Striped Bus Architecture for Minimizing Multi-Core Interference

Apr 17, 2024

SYSGO Supports RISC-V with its Embedded Linux ELinOS Version 7.2

Apr 15, 2024

RISC-V: Democratizing Innovation in CPU Design

Apr 15, 2024

BSC and Brazil’s Instituto ELDORADO Collaborate to Advance RISC-V Development for HPC and AI

Apr 15, 2024

IoT & Embedded Technology Report

Apr 12, 2024

High Degree of Specification Activity Helps with Further RISC-V Adoption

Apr 12, 2024

Unlocking the future of India’s semiconductor landscape with RISC-V Innovation

Apr 11, 2024

Enhancing the RISC-V Ecosystem with S2C Prototyping Solution

Apr 11, 2024

Ventana and Canonical collaborate on enabling enterprise data center, high-performance and AI computing on RISC-V

Apr 11, 2024

embedded world 2024 Best in Show Winners

Apr 11, 2024

[VIDEO] RISC-V CEO interview: Calista Redmond talks future of RISC-V markets at Embedded World 2024

Apr 10, 2024

Introducing SoM1-SOC: The Most Powerful SoM Based on PolarFire® SoC FPGA

Apr 10, 2024

Integrated IP Core Generation Workflow for Microchip SoC FPGAs With MathWorks®

Apr 9, 2024

RISC-V compiler toolset targets automotive functional safety

Apr 9, 2024

Imagination Reveals RISC-V Processor at Embedded World 2024

Apr 9, 2024

SiFive Unveils the HiFive Premier P550, the First Commercially Available Out-of-order RISC-V Development Board

Apr 9, 2024

Meeting RISC-V Demands: S2C’s Tailored Offerings

Apr 8, 2024

Imagination’s new Catapult CPU is driving RISC-V device adoption

Apr 8, 2024

IAR, Nuclei, and MachineWare Join Forces To Speed Up Innovation in RISC-V ASIL Compliant Automotive Solution

Apr 8, 2024

Imagination’s New Catapult CPU Is Driving RISC-V Device Adoption

Apr 7, 2024

RISC-V Cryptography Evolution: High Assurance and Post-Quantum Cryptography (RWC 2024)

Apr 7, 2024

[VIDEO] RISC-V 2024 Update: RISE, AI Accelerators & More

Apr 5, 2024

Semidynamics launches AI IP based on single ISA and one toolchain

Apr 5, 2024

Visit RISC-V at embedded world 2024!

Apr 4, 2024

RISC-V International details recent ratifications

Apr 4, 2024

RISC-V International Reaches Ratification Milestone

Apr 4, 2024

MIPS Expands RISC-V Ecosystem Support to Enable Early Software Development for Multi-threaded Cores

Apr 4, 2024

RISC-V Technical Leadership Update

Apr 4, 2024

RISC-V International Achieves Milestone with Ratification of 40 Specifications in Two Years

Apr 3, 2024

Java 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse Adoptium

Apr 3, 2024

Empower Innovation with Numato Lab’s EagleCore™ PolarFire® SoC FPGA SOM

Apr 3, 2024

MontaVista Software: Carrier Grade eXpress (CGX) 4.0 on Microchip PolarFire® SoC FPGA

Apr 2, 2024

YuzukiHD’s Eight-Core Avaota-A1 Includes a 2 TOPS NPU, RISC-V “Remote CPU,” and Connectivity Aplenty

Apr 1, 2024

[VIDEO] Why Does Formal Verification Matter for Semiconductors?

Apr 1, 2024

[VIDEO] From Specs to Verilog: AI assisted logic design on a RISC-V implementation

Mar 29, 2024

Signaloid C0-microSD A compact yet powerful FPGA development board in a microSD form factor

Mar 28, 2024

IAR sets the standard with class-leading support for Renesas’ first general-purpose RISC-V MCUs

Mar 27, 2024

RISC-V SSD controller provides 14GB/s transfers without a cooling solution

Mar 27, 2024

RISC-V International to Showcase the Latest RISC-V Developments at embedded world 2024

Mar 26, 2024

Ensuring Integrity: The Role of SoC Security in Today’s Digital World

Mar 26, 2024

RISC-V PCIe 5 SSD controller for the rest of us hits 14GB/s

Mar 26, 2024

RISC-V Unleashes Your Imagination

Mar 26, 2024

[VIDEO] Open source lightweight interpreter made in a day

Mar 26, 2024

Achronix FPGAs Add Support for Bluespec’s Linux-capable RISC-V Soft Processors to Enable Scalable Processing

Mar 26, 2024

Renesas Introduces Industry’s First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core

Mar 26, 2024

Podcast EP212: A View of the RISC-V Landscape with Synopsys’ Matt Gutierrez

Mar 25, 2024

Andes Technology: Pioneering the Future of RISC-V CPU IP

Mar 25, 2024

Quad core RISC-V FPGA is automotive qualified

Mar 22, 2024

Tenstorrent and MosChip Partner on High Performant RISC-V Design

Mar 21, 2024

BRAZIL AND EUROPE SIGN INNOVATIVE PROJECT WITH RISC-V TECHNOLOGY FOR HPC

Mar 20, 2024

MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI Compute

Mar 20, 2024

StarFive’s RISC-V Based JH-7110 Intelligent Vision Processing Platform Adopted VeriSilicon’s Display Processor IP

Mar 20, 2024

A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications

Mar 15, 2024

[VIDEO] BeagleV-Fire Out of Box Experience | RISC-V & FPGA | Microchip PolarFire | BeagleBoard.org

Mar 15, 2024

Advanced RISC-V Training Course | Maven Silicon – RISC-V Global Training Partner

Mar 15, 2024

RISC-V International Newsletter – March 2024

Mar 15, 2024

Introducing the RISC-V Enterprise Software Ecosystem Dashboard

Mar 14, 2024

Global and China Automotive RISC-V Chip Industry Research Report 2024: Customized Chips May Become the Future Trend, and RISC-V will Challenge ARM

Mar 14, 2024

Securing software execution with CHERI on a Codasip A730 RISC-V core

Mar 14, 2024

SiFive Upgrades Automotive Security for the RISC-V Ecosystem with New ISO/SAE 21434 Certification

Mar 13, 2024

Canaan’s RISC-V based edge AIoT SoC adopted VeriSilicon’s ISP and GPU IPs

Mar 13, 2024

Tenstorrent and MosChip Partner on High Performant RISC-V Design

Mar 13, 2024

embedded world 2024: Codasip demonstrates CHERI memory protection

Mar 12, 2024

People to Watch 2024 – Calista Redmond

Mar 12, 2024

Andes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable Spirit

Mar 11, 2024

What is RISC-V and Why Has it Become Important for Java?

Mar 11, 2024

Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

Mar 8, 2024

Tiempo Secure announces TESIC RISC-V Secure Element IP and development kit

Mar 8, 2024

Here’s Your Sneak Peek at SNUG Silicon Valley 2024

Mar 8, 2024

Spotlighting Women in the Global RISC-V Community this International Women’s Day

Mar 7, 2024

Next Euro HPC Chip Coming Next Year Will Be in 2026 EU Exascale System

Mar 6, 2024

[VIDEO] RISC-V for Edge AI Applications

Mar 6, 2024

From vision to reality in RISC-V: Interview with Karel Masarik

Mar 6, 2024

How the RISC-V ISA Offers Greater Design Freedom and Flexibility

Mar 6, 2024

Understanding RISC-V: The Open Standard Instruction Set Architecture

Mar 5, 2024

[VIDEO] HAPS high-performance RISC-V prototyping with asynchronous clocks | Synopsys

Mar 5, 2024

Free tool enables customers to fully configure RISC-V cores

Mar 5, 2024

[VIDEO] SBT C Suite Spotlight: Calista Redmond, CEO of RISC V International – Full Conversation

Mar 4, 2024

VeriSilicon’s industry-leading embedded GPU IP powers HPMicro’s high-performance HPM6800 series RISC-V MCU

Mar 1, 2024

Imsys develops RISC-V core, looks to AI in space

Feb 29, 2024

Scaleway launches its RISC-V servers in the cloud, a world first and a firm commitment to technological independence

Feb 29, 2024

1.8 Billion Heterogenous AI Chipsets by 2030, 129 Million RISC-V AI Shipments by 2030 and 36 Other Transformative Technology Stats You Need to Know

Feb 28, 2024

Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV

Feb 27, 2024

Soccer, Chips, RISC-V and Brazil

Feb 27, 2024

Tenstorrent Scores Big Design Win With Japan’s LTSC To Enable Leading-Edge 2nm AI Accelerator

Feb 27, 2024

[PODCAST] Leading the RISC-V Revolution, SiFive Aims to Take the Computing Industry Throne

Feb 27, 2024

Tenstorrent RISC-V and Chiplet Technology Selected to Build the Future of AI in Japan

Feb 26, 2024

Porting and Optimizing Android ART on XuanTie C910

Feb 26, 2024

Developing and testing heterogeneous space-grade systems with Renode

Feb 23, 2024

Ashling’s RiscFree™ SDK Toolchain now available with support for MIPS RISC-V ISA compatible P8700 and I8500 CPUs

Feb 22, 2024

Andes Technology and MetaSilicon Collaborate to Build the World’s First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC

Feb 22, 2024

Andes Technology and MetaSilicon Collaborate to Build the World’s First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC

Feb 21, 2024

Feb 20, 2024

Dr Tadej Murovič, Codasip | RISC-V and Codasip Revolutionizing the Future of Processor Design

Feb 20, 2024

BeagleV-Fire Unboxing – Running Linux 6.1 Kernel on RISC-V!

Feb 20, 2024

2024 Outlook With Laura Long of Axiomise

Feb 19, 2024

Announcing The Fourth International Workshop on RISC-V for HPC

Feb 15, 2024

RISC-V Is Inevitable and Reshaping the Future of Compute | Andy Moore

Feb 14, 2024

RISC-V Processors Addressing Edge AI Devices To Reach 129 Million Shipments by 2030

Feb 13, 2024

Red Hat and RISC-V: To the far edge and beyond

Feb 13, 2024

Integrating ROS 2 With Microchip’s PolarFire® SoC FPGA

Feb 12, 2024

OPC UA on PolarFire SoC: Enabling Industrial Edge Solutions

Feb 5, 2024

【Andes Webinar】Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series

Feb 5, 2024

Effectively hiding sensitive data with RISC-V Zk and custom instructions

Feb 5, 2024

Navigating the RISC-V Revolution in Europe

Feb 5, 2024

Catching up with MEEP: Bringing forward the development of tomorrow’s European exascale supercomputing

Feb 5, 2024

Banana Pi BPI-F3 is a single-board PC with an 8-core RISC-V processor, dual Ethernet and PCIe 2.1

Feb 5, 2024

Klepsydra AI and Frontgrade Gaisler Collaborate to Expand Microprocessing Versatility in Space Missions Through AI

Feb 1, 2024

Ashling announces Ashling’s RiscFree™ C/C++ SDK support for Codasip’s RISC-V-based L31 Core

Feb 1, 2024

Codasip achieves certification for automotive functional safety and cybersecurity

Jan 31, 2024

RISC-V Based Architecture Integrates Complex Memory Tasks to Processor

Jan 31, 2024

BellSoft releases Liberica JDK 21 for RISC-V with support

Jan 31, 2024

RISC-V Open-Source Architecture Redefining The Future Of Computing

Jan 29, 2024

EDACafe Industry Predictions for 2024 – RISC-V

Jan 26, 2024

Dutch startup Innatera unveils T1: a game-changing RISC-V neural-type MCU in the edge AI sensor market

Jan 25, 2024

RISC-V Open-Source Architecture Redefining The Future Of Computing

Jan 25, 2024

EDA Back On Investors’ Radar

Jan 24, 2024

RISC-V With Linux 6.8 Restores XIP Kernel Support

Jan 24, 2024

Frontgrade Gaisler and RISC-V’s Space Journey

Jan 24, 2024

StarFive RISC-V SoC’s Camera Subsystem Driver Added To Linux 6.8

Jan 24, 2024

VyperCore shows RTL simulation of RISC-V core, plans hardware

Jan 24, 2024

Debugging complex RISC-V processors

Jan 21, 2024

[Video] Milk-V Duo 256M – Tri-Core AI SBC that runs Linux!

Jan 17, 2024

COMPUTE THE MANDELBROT SET WITH A CUSTOM RISC-V CPU

Jan 17, 2024

YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in Barcelona

Jan 17, 2024

Franck Bernard, Bosch – The RISC-V opportunity in Automotive Electronics

Jan 17, 2024

Charlie Su, Andes Technology – RISC-V is Firing on All Cylinders

Jan 16, 2024

Video: Leveraging the RISC-V efficient trace (E-Trace) standard

Jan 16, 2024

The Application of RISC-V Extensions to Automotive Zonal Controllers – Marc Canel

Jan 16, 2024

Using Virtual Platforms to Shift Left Automotive Software Development – Jon Taylor & Koji Adachi

Jan 12, 2024

ONiO looks to kill the IoT battery with RISC-V microcontroller

Jan 11, 2024

What is RISC-V and why is it important?

Jan 11, 2024

CES: MIPS CEO Sameer Wasson sees RISC-V as path to freedom

Jan 11, 2024

SEGGER’s new Embedded Studio: One IDE for both Arm and RISC-V

Jan 11, 2024

DFRobot Brings RISC-V and Matter Compatibility to Its FireBeetle 2 Board with New ESP32-C6 Variant

Jan 11, 2024

Andes Introduces RISC-V Out-of-Order Superscalar Multicore Processor

Jan 9, 2024

BeagleV-Fire Board Blends RISC-V and FPGA

Jan 8, 2024

China researchers report 256 core, chiplet-based processor

Jan 8, 2024

Andes Technology and Spacetouch Collaborate to Unveil High-Tech Edge-Side AI Audio Processor Featuring the Powerful RISC-V AndesCore™ D25F

Jan 8, 2024

The SHD Group Has Released a Complimentary Version of the 2024 RISC-V Market Analysis Report Containing Current Market Data and Future Projections

Jan 8, 2024

The Rise of RISC-V – Analyzing Market Trends and Ecosystem Dynamics

Jan 4, 2024

Andes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65

Jan 4, 2024

WCH RISC-V microcontrollers can now be programmed with the Arduino IDE

Jan 4, 2024

Expanding RISC-V support in Renode with Bit-Manipulation extensions

Jan 3, 2024

Five Leading Semiconductor Industry Players Incorporate New Company, Quintauris, to Drive RISC-V Ecosystem Forward

Jan 2, 2024

Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

Jan 2, 2024

[VIDEO] Synopsys ARC-V RISC-V Processor IP | Synopsys

Dec 25, 2023

RISC-V 双周报第72期：OpenAI自研RISC-V架构芯片，国内各项竞赛频现RV赛道(20231215)

Dec 23, 2023

RISC-V hardware ecosystem gets strong industry support – Qualcomm joins with four other industry players to form Quintauris

Dec 21, 2023

RISC-V International Newsletter – December 2023

Dec 20, 2023

World’s first RISC-V handheld gaming system announced — retro gaming platform uses Linux

Dec 20, 2023

RISC-V is Creating a ‘Linux Movement’ in Hardware

Dec 20, 2023

RISC-V Summit report: Meta leads the way for custom processors

Dec 19, 2023

RISC-V Summit Buzz – Launchpad Showcase Highlights Smaller Company Innovation

Dec 15, 2023

Five years of SERVing

Dec 14, 2023

Open-Source Chip Design Takes Hold in Silicon Valley

Dec 14, 2023

Sameer Wasson’s Vision for MIPS/RISC-V

Dec 14, 2023

Sipeed Takes RISC-V Into the Gaming Arena with the Nintendo Switch-Like Lichee Pocket 4A

Dec 13, 2023

The Top 10 RISC-V Milestones & Highlights from 2023

Dec 13, 2023

BSC presents Sargantana, the first open-source chips designed in Spain

Dec 12, 2023

RISC-V and Arteris: Shaping the Future of Chip Design

Dec 12, 2023

Developing and testing with Renode in heterogeneous, multi-node automotive use cases

Dec 12, 2023

Solving bus and software deadlock problems in complex SoCs

Dec 11, 2023

Andes Awards Imperas 2023 Partner of the Year

Dec 11, 2023

Reviewing the 2023 RISC-V Summit

Dec 8, 2023

[PODCAST] A Tour of the RISC-V Movement and SiFive’s Contributions with Jack Kang

Dec 8, 2023

[VIDEO] The RISC-V Revolution

Dec 8, 2023

RISC-V Summit 2023: RISC-V is Here for Developers!

Dec 5, 2023

Renesas Champions the RISC-V Cause With Its Own 32-bit RISC-V CPU

Dec 5, 2023

[VIDEO] RISC-V Summit 2023 – Recap from OpenHW Group

Dec 5, 2023

[PODCAST] Current State of RISC-V Architecture | Calista Redmond

Dec 5, 2023

RISC-V’s embedded foray with a 32-bit MCU development

Dec 5, 2023

RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization

Dec 5, 2023

RISC-V to the Core: New Horizons

Dec 5, 2023

Canonical joins the RISC-V Software Ecosystem (RISE)

Dec 4, 2023

RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®

Dec 1, 2023

META SEES LITTLE RISK IN RISC-V CUSTOM ACCELERATORS

Dec 1, 2023

World’s First RISC-V Pad with LTE Launched by DeepComputing at RISC-V Summit 2023

Nov 30, 2023

Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition

Nov 30, 2023

Enabling Secure Open Source ML Products with Open Se Cura

Nov 28, 2023

IAR Unveils the TCO Calculator: A Breakthrough for Embedded Engineering

Nov 28, 2023

Customization? Yes! After tape-out? Yes!

Nov 28, 2023

Integrating PikeOS with Microchip’s RISC-V based PolarFire® SoC FPGA | PikeOS: A Versatile Hypervisor-RTOS

Nov 23, 2023

Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption

Nov 22, 2023

AMD’s fastest gaming GPU now works with RISC-V CPUs, AMD Radeon RX 7900 XTX open source Linux drivers available

Nov 16, 2023

[Case Study] SuperTest – helping TrustInSoft guarantee its customers 100% bug-free source code

Nov 15, 2023

Quick Time-To-Market with a Compact and Powerful Microchip PolarFire® SoC FPGA System on Module

Nov 14, 2023

RISC-V Gains Momentum As EDA & AI Chip Design Leader Announces New IP

Nov 14, 2023

RISC-V Rollouts Abound at This Week’s North America RISC-V Summit

Nov 14, 2023

[VIDEO] RISC-V Taipei Day: Trends In Ai & Automotive

Nov 14, 2023

[VIDEO] 023 RISC-V Taipei Day: Extending RISC-V Intelligence From Cloud To Edge

Nov 14, 2023

[VIDEO] 2023 RISC-V Taipei Day: Scalable RISC-V For Digital Transformation

Nov 14, 2023

[VIDEO] 2023 RISC-V Taipei Day: Bridging The Divide – Unifying RISC-V Through Binary Translation

Nov 14, 2023

[VIDEO] 2023 RISC-V Taipei Day: RISC-V is Leading Technology in the World

Nov 14, 2023

2023 RISC-V Taipei Day: RISC-V is Inevitable

Nov 14, 2023

Andes Technology Partners with WITTENSTEIN high integrity systems (WHIS) to Build Safety-Critical Solutions with RISC-V Processors

Nov 14, 2023

Understanding RISC-V: The Open Standard Instruction Set Architecture

Nov 14, 2023

Integrating PikeOS With Microchip’s RISC-V Based PolarFire® SoC FPGA

Nov 14, 2023

[VIDEO] Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips

Nov 9, 2023

RISC-V Summit 2023: Embedded Editor Report, Day 2

Nov 9, 2023

RISC-V: Projected Growth to Over 16 Billion Chips by 2030

Nov 8, 2023

RISC-V Summit 2023: Embedded Editor Report

Nov 8, 2023

Ventana’s 192-Core RISC-V CPU Takes Aim At AMD Epyc Genoa And Bergamo

Nov 8, 2023

OpenHW Group Announces CORE-V CVA6 Platform Project for RISC-V Software Development & Testing

Nov 8, 2023

New RISC-V processors address demand for open source and performance

Nov 8, 2023

Synopsys Moves To RISC-V To Help SoC Developers

Nov 7, 2023

RISC-V Summit North America 2023: Best in Show Nominees

Nov 7, 2023

More Than 16 Billion RISC-V Chips Forecasted by 2030

Nov 7, 2023

Ventana and Imagination Partner to Deliver World’s Highest Performance RISC-V CPU & GPU Solutions

Nov 7, 2023

Ventana Introduces Veyron V2 — World’s Highest Performance Data Center-Class RISC-V Processor and Platform

Nov 7, 2023

Synopsys Expands Its ARC Processor IP Portfolio with New RISC-V Family

Nov 7, 2023

OpenHW Group Announces CORE-V CVA6 Platform Project for RISC-V Software Development & Testing

Nov 7, 2023

BeagleBoard.org Makes FPGA and RISC-V Accessible with New BeagleV-Fire Single Board Computer at $150

Nov 7, 2023

Ashling announce RiscFree™ C/C++ SDK support for the newly launched Synopsys ARC-V RISC-V ISA based Processors

Nov 7, 2023

RISC-V International Marks Banner Year for RISC-V Adoption, Technical Momentum, and Community Engagement

Nov 7, 2023

Accelerating the Open Source Software Ecosystem with RISC-V Labs

Nov 7, 2023

High performance GPU cores for cloud gaming with RISC-V

Nov 7, 2023

The Rise of RISC-V: From University Lab to Global Force in Silicon Design

Nov 7, 2023

Ubilite Licenses RISC-V Application Processor IP Core from CAST

Nov 6, 2023

Andes and Vector Propel RISC-V AUTOSAR Software Innovations for the Automotive Industry

Nov 3, 2023

What is RISC-V? CTO Mark Himelstein Explains Its Role in Computer Science – The Electropages Podcast

Nov 3, 2023

Tenstorrent and Imperas Set to Provide Model of RISC-V Core

Nov 3, 2023

Debugging RISC-V processors using E-Trace

Nov 2, 2023

RISC-V International Newsletter – November 2023

Nov 2, 2023

Imperas RISC-V solutions for developers – accelerating RISC-V

Nov 2, 2023

Hyperion Core Joins RISC-V International as a Strategic Member

Nov 2, 2023

Ashling RISC-V Summit Product Announcements

Nov 2, 2023

S2C’s FPGA Prototyping Accelerates Iterations of XiangShan RISC-V Processor

Nov 1, 2023

Qamcom boosts RISC-V beyond the edge with QERV

Nov 1, 2023

Sophgo Licenses SiFive RISC‑V Processor Cores to Drive High-Performance AI Computing Innovation

Nov 1, 2023

Imperas RISC-V Solutions for Developers – Accelerating RISC-V

Nov 1, 2023

Imperas RISC-V Solutions for Developers – Accelerating RISC-V

Oct 31, 2023

RISC-V Is Here! RISC-V Summit North America Showcases Innovation, Products, Boards, Community

Oct 31, 2023

Codasip Announces First Commercial Implementation of CHERI Memory Protection

Oct 31, 2023

Codasip delivers processor security to actively prevent the most common cyberattacks

Oct 31, 2023

RISC-V is Here! RISC-V Summit North America Showcases Innovation, Products, Boards, Community

Oct 31, 2023

[PODCAST] The Growth and Impact of RISC-V and a Peek at the Upcoming RISC-V Summit with Calista Redmond by Daniel Nenni

Oct 30, 2023

The Road to the RISC-V Summit: Microchip

Oct 30, 2023

Tenstorrent Teams with Imperas to Provide Model of the Tenstorrent Ascalon RISC-V Core

Oct 30, 2023

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor

Oct 30, 2023

Google will release Android RISC-V emulators to test apps in 2024

Oct 30, 2023

Hyperion Core Joins RISC-V International as a Strategic Member

Oct 30, 2023

Android and RISC-V: What you need to know to be ready

Oct 29, 2023

CHIPS Alliance Technology Update

Oct 27, 2023

Top 5 Facts about RISC-V – Tom’s Top Five

Oct 26, 2023

On the EVE of the RISC-V Summit North America

Oct 26, 2023

Ashling and InCore announce Ashling’s RiscFree™ C/C++ SDK support for InCore’s RISC-V-based Azurite Cores.

Oct 25, 2023

Microchip Showcases Expanded RISC-V-Based Solutions, Partnerships and System Design Tools at 2023 RISC-V Summit

Oct 25, 2023

Harnessing the RISC-V Wave: The Future is Now

Oct 25, 2023

First fully coherent RISC-V Tensor unit for AI chip design

Oct 24, 2023

Semidynamics launches first fully-coherent RISC-V Tensor unit to supercharge AI applications

Oct 20, 2023

Codasip announces next-generation RISC-V processor family for Custom Compute

Oct 20, 2023

Tenstorrent’s vision for the AI Revolution: Conversation with Chief CPU Architect Lien Wei-han

Oct 20, 2023

Research Consortium sets Standards in the Field of Open Source Hardware: Open Tools used for a Security Chip

Oct 19, 2023

What is RISC-V and how will it redefine your next-gen wearable tech?

Oct 18, 2023

Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor Technology

Oct 17, 2023

Qualcomm to Bring RISC-V Based Wearable Platform to Wear OS by Google

Oct 17, 2023

Qualcomm Adopts RISC-V for Next-Gen Snapdragon Wear Platform

Oct 17, 2023

SharpRISCV Overview: A Browser-Based RISC-V Assembler for Seamless Learning and Exploration

Oct 17, 2023

Codasip announces next-generation RISC-V processor family for Custom Compute

Oct 17, 2023

Codasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyone

Oct 16, 2023

SiFive Rolls Out RISC-V Cores Aimed at Generative AI and ML

Oct 13, 2023

Journeying Beyond AI: Unleashing the Art of Verification

Oct 11, 2023

SiFive unveils two new high-performance RISC-V processors

Oct 11, 2023

SiFive Announces Differentiated Solutions for Generative AI and ML Applications Leading RISC-V into a New Era of High-Performance Innovation

Oct 11, 2023

DPI support in Renode for HDL co-simulation with Verilator and Questa

Oct 10, 2023

Semidynamics and Signature IP Expand Multi-Core RISC-V and CHI Options

Oct 10, 2023

RISC-V：由全球社区支持的开放标准，为所有人提供开放计算

Oct 9, 2023

RISC-V: An Open Standard – Backed by a Global Community – to Enable Open Computing for All

Oct 9, 2023

Embedded Computing Design Announces Innovative Content Opportunities for RISC-V Summit

Oct 6, 2023

Exploring RISC-V Assembly in the Web Browser with SharpRISCV

Oct 6, 2023

Trikarenos is a RISC-V chip for miniaturized space missions

Oct 5, 2023

Linux Patches Updated For 64-Core RISC-V Milk-V Pioneer mATX Board

Oct 5, 2023

Boffins propose RISC-V microcontroller to power cubesats

Oct 5, 2023

RISC-V video editing tested on a Lichee Pi 4A mini PC

Oct 4, 2023

RISC-V: Pioneering Windows Assembly – A New Era in Computing

Oct 4, 2023

SemiDynamics teams for multicore RISC-V chiplet boost

Oct 4, 2023

Samsung To Build Next-Gen Tenstorrent AI Chiplet Leveraging RISC-V Architecture

Oct 3, 2023

Tenstorrent Selects Samsung Foundry to Manufacture Next-Generation AI Chiplet

Oct 3, 2023

Semidynamics and SignatureIP create a fully tested RISC-V multi-core environment and CHI interconnect

Oct 1, 2023

[VIDEO] RISC-V Video Editing & 500th Episode

Sep 28, 2023

Acura, part of HID, Collaborates with Von Braun Labs and #Data to Develop a RISC-V Based ASIC for Access Control and Free-Flow Tolling

Sep 27, 2023

Automated Kernel Testing on RISC-V Hardware

Sep 26, 2023

Ashling’s RiscFree™ SDK Now Supports RISC-V® Processor Cores from CAST

Sep 25, 2023

It’s not just about the core, it’s also about the system

Sep 23, 2023

Chipmakers, Researchers, and Hobbyists Show Off the Many Faces of RISC-V

Sep 22, 2023

OpenHW Group Appoints Florian ‘Flo’ Wohlrab as New CEO to Spearhead Open-Source Ecosystem Advancement

Sep 21, 2023

Accelerating RISC-V development with network-on-chip IP

Sep 21, 2023

How to Design a RISC-V Space Microprocessor

Sep 21, 2023

RISC-V International Newsletter – September 2023

Sep 20, 2023

Claude (AI) Codes a RISC-V Core in TL-Verilog

Sep 20, 2023

Nordic Semiconductor proves world-leading processing efficiency with the revolutionary nRF54H20 SoC

Sep 19, 2023

New RISC-V Market Report Will Provide 5-Year Growth Projections for Semiconductor Devices and Insights on the Enabling Ecosystem

Sep 19, 2023

New RISC-V Market Report Will Provide 5-Year Growth Projections for Semiconductor Devices and Insights on the Enabling Ecosystem

Sep 15, 2023

[VIDEO] Pointers in RISC-V Assembly

Sep 15, 2023

Esperanto Technologies Introduces First Generative AI Appliance Based on RISC-V, Enabling Developers to Easily Create and Deploy Purpose-Built Vertical Applications

Sep 13, 2023

Esperanto Technologies Introduces First Generative AI Appliance Based on RISC-V, Enabling Developers to Easily Create and Deploy Purpose-Built Vertical Applications

Sep 13, 2023

Bluespec’s accelerate-HLS leverages RISC-V to simplify and speed the development of HLS applications

Sep 12, 2023

Bluespec’s Accelerate-HLS Leverages RISC-V to Simplify and Speed the Development of HLS Applications

Sep 12, 2023

Configurable LLDB for (not only) embedded RISC-V processors

Sep 11, 2023

Andes Announces General Availability of the New AndesCore™ RISC-V Multicore Vector Processor AX45MPV

Sep 8, 2023

What is RISC-V, and why we’re unlocking its potential

Sep 8, 2023

Codasip collaborates with Siemens to deliver trace solution for custom processors

Sep 7, 2023

Andes Announces General Availability of the New AndesCore™ RISC-V Multicore Vector Processor AX45MPV

Sep 7, 2023

DeepComputing Has Made Great Processes in New Hardware Devices and Software Solutions

Sep 5, 2023

RISC-V Summit China: Experts praise open source architecture for driving tech innovation and change

Sep 5, 2023

Codasip collaborates with Siemens to deliver trace solution for custom processors

Aug 31, 2023

Introducing the RISC-V Board of Directors Elected Officers

Aug 31, 2023

GOWIN Semiconductor & Andes Technology Corp. Announce The First Ever RISC-V CPU and Subsystem Embedded 22nm SoC FPGA

Aug 30, 2023

SiFive unveils P870 high-performance core, discusses future of RISC-V

Aug 30, 2023

RISC-V co-design using trace-based simulation with Renode and TBM

Aug 28, 2023

Sipeed unveils RISC-V tablet, portable Linux console, and cluster

Aug 28, 2023

Nuclei , the World’s First RISC-V CPU IP Vendor to Accomplish ISO 26262 ASIL-D Product Certificate

Aug 28, 2023

Think and Tinker your own IoT solutions

Aug 27, 2023

RISC-V Public Beta Platform Release · Database Adaptation Evaluation On RISC-V server

Aug 27, 2023

Debugging a RISC-V processor requires integrated hardware and software tools

Aug 24, 2023

LIVE WEBINAR: Accelerating Compute-Bound Algorithms with Andes Custom Extensions (ACE) and Flex Logix Embedded FPGA Array

Aug 24, 2023

RISC-V – Part 2 : Ambitious Aims

Aug 24, 2023

RISC-V Summit China 2023 kicks off in Beijing

Aug 24, 2023

RISC-V Customization Gets A Standing Ovation

Aug 24, 2023

Cloud-V: Accelerating RISC-V Software Development with 10xEngineers

Aug 22, 2023

Milk-V Launches Milk-V Vega, the World’s First RISC-V Open Source 10 Gigabit Ethernet Switch

Aug 22, 2023

OpenHW announces tape out of RISC-V-based CORE-V MCU Devkit

Aug 22, 2023

Valtrix to Exhibit at RISC-V Summit China August 23-25

Aug 21, 2023

RISC-V Specialist Milk-V Jumps Into the Network Market with the New 10-gig-E Vega Switch

Aug 20, 2023

Lichee Pi 4A RISC-V Desktop Gets Unboxed, Offers Strong Linux Performance

Aug 20, 2023

New Emulator Lets Some x86-64 Games Run on RISC-V Dev Board

Aug 17, 2023

Oral History of Mark Himelstein | CTO of RISC-V International

Aug 17, 2023

OpenHW Group Delivering RISC-V CORE-V MCU Dev. Kits

Aug 17, 2023

World’s First RISC-V Laptop Roma Officially Delivered: 8GB RAM and Pre-installed with Domestic OS

Aug 16, 2023

OpenHW Group Announces Tape Out of RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software

Aug 16, 2023

OpenHW Group Announces Tape Out of RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software

Aug 15, 2023

Cool PolarFire® SoC FPGA Based System On Modules by ARIES Embedded

Aug 14, 2023

Collaboration looks to build AI Accelerator chip with analogue in-memory computing

Aug 14, 2023

Leading semi players join forces to accelerate RISC-V

Aug 14, 2023

RISC-V Expanding In China

Aug 11, 2023

Andes Technology And TetraMem Collaborate To Build Groundbreaking AI Accelerator Chip With Analog In-Memory Computing

Aug 10, 2023

XuanTie RISC-V Contest on Innovation of Applications

Aug 10, 2023

AI and RISC-V chip company Tenstorrent raises $100m from Hyundai, Kia, and Samsung

Aug 9, 2023

Big chip players join forces to form another RISC-V venture

Aug 7, 2023

Forlinx announces RISC-V SoM based on StarFive JH7110

Aug 7, 2023

Terapines ZCC Toolchain Fully Supports Andes RISC-V Processors

Aug 4, 2023

Chip makers team up to take on Arm with RISC-V

Aug 4, 2023

AI chip startup Tenstorrent lands $100M investment from Hyundai and Samsung

Aug 4, 2023

Why Innovation in Analog IP is so Important for the RISC-V Ecosystem

Aug 2, 2023

Confidence In AI Startup Tenstorrent Spurs $100M Funding Round By Hyundai And Samsung

Aug 2, 2023

RISC-V AI Startup Tenstorrent Gets Another $100M Infusion From Samsung And Hyundai

Aug 2, 2023

IIT Madras invites Applications for Symposium on ‘Future of India’s Electronics and Computers’

Aug 2, 2023

Krakatoa Technologies Celebrates Key Milestone as RISC-V Core Startup with Big Order from PT Andreal Industri Primatama

Aug 1, 2023

RISC-V Summit China 2023 | August 23-25

Aug 1, 2023

Terapines ZCC Toolchain Fully Supports Andes RISC-V Processors

Jul 31, 2023

Terapines ZCC Toolchain Fully Supports Andes RISC-V Processors

Jul 31, 2023

Esperanto Merging HPC and ML in Upcoming RISC-V Processor

Jul 28, 2023

RISC-V Finds Its Foothold in a Rapidly Evolving Processor Ecosystem

Jul 28, 2023

AMD Readies “New Stuff” For Linux 6.6 Graphics Driver, AMDGPU DC For RISC-V

Jul 28, 2023

Semidynamics Released its 4-way Atrevido 423 RISC-V Core

Jul 28, 2023

Witnessing the Power of RISC-V at My First DAC

Jul 28, 2023

Semidynamics Released its 4-way Atrevido 423 RISC-V Core

Jul 28, 2023

AMD Readies “New Stuff” For Linux 6.6 Graphics Driver, AMDGPU DC For RISC-V

Jul 28, 2023

RISC-V Finds Its Foothold in a Rapidly Evolving Processor Ecosystem

Jul 27, 2023

Re-Targetable LLVM C/C++ Compiler For RISC-V

Jul 27, 2023

Re-Targetable LLVM C/C++ Compiler For RISC-V

Jul 26, 2023

Semidynamics announces fully customisable, 4-way Atrevido 423 RISC-V core for big data applications

Jul 26, 2023

The release of the first two mass-produced development boards – AOSP powered by TH1520 SoC

Jul 24, 2023

Vitra-XS Debug & Trace Probe

Jul 24, 2023

Debian GNU/Linux Is Now Officially Supported on the RISC-V Architecture

Jul 24, 2023

Leveraging RISC-V architecture to boost economic development

Jul 24, 2023

Why Maven Silicon for Upskilling Your Chip Design Workforce?

Jul 24, 2023

Ashling RiscFree™ C/C++ SDK support for the Zephyr Real-Time Operating System (RTOS)

Jul 21, 2023

Ashling announce RiscFree™ support for MachineWare’s SIM-V RISC-V Instruction Set Simulator.

Jul 21, 2023

Semidynamics announces fully customisable, 4-way, Atrevido 423 RISC-V core

Jul 20, 2023

RiscFree C/C++ support for Lattice RISC_V soft IP cores

Jul 20, 2023

Semidynamics announces, 4-way, Atrevido 423 RISC-V core

Jul 20, 2023

RISC-V Fast-Forwards, Breaks Ground for Auto Innovations

Jul 20, 2023

Want Tailormade Screamingly-High-Performance RISC-V64 IP?

Jul 20, 2023

Fully customisable 4-way RISC-V core for big data

Jul 20, 2023

The Power of RISC-V: DAC Panel with Intel, Imperas, Meta, OpenHW Group & Ventana

Jul 20, 2023

ANDLA DEBUTS FOR AI ACCELERATION

Jul 19, 2023

The Growing Momentum of RISC-V in Europe

Jul 19, 2023

YOLOX for Object Detection

Jul 19, 2023

SiFive’s WorldGuard Security Platform Now Available to the Entire RISC-V Ecosystem

Jul 18, 2023

Making the most of the 60th DAC

Jul 18, 2023

Polos CH32Vxx 32-bit RISC-V MCU boards starts at $1.99

Jul 17, 2023

Startups Help RISC-V Reshape Computer Architecture

Jul 17, 2023

RISC-V Fast-Forwards, Breaks Ground for Auto Innovations

Jul 17, 2023

The industry’s first RISC-V IoT security chip, “Towngas Chip”, had sold over 1,000,000 pieces

Jul 17, 2023

THIS RISC-V CPU GAMES IN RUST FROM INSIDE THE GAME

Jul 17, 2023

DAC 2023: RISC-V is not in the future, it’s now

Jul 14, 2023

PODCAST: RISC-V International, Today and Tomorrow with Calista Redmond

Jul 14, 2023

Ashling announces RiscFree™ C/C++ SDK support for Lattice RISC-V MCU CPU Soft IP Cores

Jul 13, 2023

VIDEO: DAC 2023, Day 3: ‘CHIPS Acts,’ RISC-V, More AI

Jul 13, 2023

AnalogLamb Announces RISC-V Polos Development Boards, Starting at Just $1.99

Jul 13, 2023

BeagleV®-Ahead single board computer available from Farnell

Jul 13, 2023

The Incredible Growth of RISC-V in India

Jul 12, 2023

BeagleBoard.org Moves Along with its BeagleV-Ahead

Jul 12, 2023

BeagleV-Ahead is a single-board RISC-V computer that’s compatible with BeagleBone add-ons

Jul 11, 2023

BeagleV-Ahead RISC-V computer from BeagleBoard.org available now under $150

Jul 11, 2023

Bluespec’s newest RISC-V chip adds customization capabilities for edge workloads

Jul 11, 2023

VIDEO: A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs

Jul 11, 2023

Towards a RISC-V Open Platform for Next-generation Automotive ECUs

Jul 11, 2023

Imperas details verification of automotive AI RISC-V vector processor IP

Jul 11, 2023

Open Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR Core

Jul 10, 2023

LicheePi 4A RISC-V SBC gets 16GB/128GB version, metal enclosure, 10.1-inch display, and more accessories

Jul 10, 2023

Upcoming low cost RISC-V breakout boards start at $1.99

Jul 10, 2023

Cadence and Imperas Support NSITEXE in the Development of Advanced RISC V Vector Processor IP for Automotive AI Applications

Jul 9, 2023

Takeaways From the First RISC-V Summit Europe

Jul 7, 2023

VIDEO: Running LVGL Application on RT-Smart MicroKernel OS with RISC-V

Jul 7, 2023

The growth of RISC-V across industries

Jul 7, 2023

Imperas Helps Navigate the Journey to RISC-V Based Silicon at DAC 2023

Jul 6, 2023

Takeaways From the First RISC-V Summit Europe

Jul 6, 2023

RISC-V Summit Europe 2023: Highlights from Barcelona

Jul 6, 2023

The Next Revolution in the Microchip Industry

Jul 6, 2023

HPCpodcast: An Architecture Update from RISC-V International CTO Mark Himelstein

Jul 6, 2023

Power, automotive and AI markets highly interested in RISC-V

Jul 5, 2023

It’s all about RISC-V code size

Jul 5, 2023

Bluespec’s MCUX RISC-V Processor Ideal for FPGAs and ASICs

Jul 3, 2023

VIDEO: EUPILOT: Europe’s HPC and AI pre-exascale accelerator demonstrator

Jul 3, 2023

Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests

Jul 3, 2023

VMware join hands with Samsung, AMD, RISC-V for confidential computing

Jul 3, 2023

Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests

Jul 3, 2023

VMware, Other Tech Giants Announce Push for Confidential Computing Standards

Jun 30, 2023

Customizable RISC-V processor is vendor-independent

Jun 30, 2023

Chinese Researchers Used AI to Design RISC-V CPU in Under 5 Hours

Jun 30, 2023

VMware, AMD, Samsung and RISC-V push for confidential computing standards

Jun 29, 2023

VMware partners with Samsung, AMD and RISC-V to accelerate confidential computing

Jun 28, 2023

The Call for Papers for RISC-V Summit China 2023 is Open

Jun 28, 2023

China Mobile releases two self-developed RISC-V communications chips

Jun 28, 2023

The European Project Creating Extensible, Energy-Efficient RISC-V CPUs

Jun 26, 2023

Tailor Made RISC-V Performance – eeNews interview with Roger Espasa/Semidynamics

Jun 25, 2023

GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations

Jun 22, 2023

Addition of Single Precision Floating Point (F) extension in NucleusRV: RISC-V based RV32-IMC Core

Jun 21, 2023

In Her Own Words: Calista Redmond, casual Fridays and collaboration

Jun 20, 2023

RISC-V Europe Summit Debuts Among Signs of Significant Growth in Advanced IoT Applications

Jun 20, 2023

RISC-V: The Game-Changer In Microprocessor Investments. Here’s 3 Companies Riding The Wave.

Jun 19, 2023

Could RISC-V Disrupt the 8086-Arm Hegemony?

Jun 19, 2023

When tapas meet tech: Barcelona’s RISC-V Summit feeds our appetite for innovation

Jun 16, 2023

XMOS Joins RISC-V Ecosystem

Jun 16, 2023

Semidynamics announces largest, fully customisable Vector Unit in the RISC-V market, delivering up to 2048b of computation per cycle for unprecedented data handling

Jun 16, 2023

XMOS Joins RISC-V Ecosystem

Jun 15, 2023

The Next Revolution in the Microchip Industry

Jun 15, 2023

Secure-IC & NSITEXE extend strategic partnership to provide security solutions for Cyber-Physical Systems (CPS)

Jun 15, 2023

What is RISC-V?

Jun 14, 2023

Integrating Tile Link UH in the Caravan Framework: A Journey of Enhanced Functionality

Jun 13, 2023

RISC-V rises to software ecosystem challenge

Jun 13, 2023

DFRobot Launches the All-In-One UNIHIKER, a Single-Board Arm Computer with Display and RISC-V MCU

Jun 13, 2023

Milk-V Unveils Its Third RISC-V Board in a Month: The $9 Dual-Core Linux-Capable Milk-V Duo

Jun 9, 2023

RISC-V gathers pace in Europe

Jun 8, 2023

Startup plans customizable RISC-V edge AI speech processor | Nick Flaherty, EE News Europe

Jun 8, 2023

Imagination, GHS team for RTOS and tools on RISC-V CPUs | Nick Flaherty, EENews Europe

Jun 8, 2023

Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit Europe

Jun 7, 2023

Interview with Calista Redmond – RISC-V summit Barcelona

Jun 7, 2023

Configurable 64-bit RISC-V IP Targets Machine Learning, Other Advanced Apps | Alix Paultre, Electronic Design

Jun 7, 2023

Computing at the Ultimate Edge – Space | Wisse Hettinga, EENews Europe

Jun 7, 2023

Safety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPU

Jun 6, 2023

The RISC-V Report – interviewing the key players (2017-2023)

Jun 5, 2023

Agile Analog launches first complete RISC-V analog IP subsystem

Jun 5, 2023

Complete RISC-V analog IP subsystem targets IoT | Jean-Pierre Joosting, EE News Europe

Jun 5, 2023

Newly Revealed RISC-V Vector Unit Could Be Used for AI, HPC, GPU Applications | Anton Shilov, Tom’s Hardware

Jun 5, 2023

SOPHGO Donates 50 RISC-V Motherboards – Learn More About the Pioneer Box

Jun 5, 2023

Ventana to Deliver Keynote at RISC-V Summit Europe | Yahoo! Finance

Jun 5, 2023

Adding RISC-V Vector Cryptography Extension support to QEMU

Jun 3, 2023

Consortium’s Move Will Boost RISC-V Ecosystem, Thankfully | Steve Leibson , EE Times

Jun 3, 2023

Alibaba’s T-Head joins global initiative to develop RISC-V software ecosystem, along with Intel, Qualcomm and Nvidia | Ann Cao, South China Morning Post

Jun 3, 2023

Milk-V Duo is a $9.00 RISC-V tiny embedded computer | Giorgio Mendoza , Linux Gizmos

Jun 2, 2023

RISE project gives RISC-V an open source software lift | Nitin Dahad, Embedded.com

Jun 2, 2023

RISE to boost development of open source RISC-V software

Jun 2, 2023

UltraRISC Selects Valtrix STING for Verification of RISC-V SoC Designs

Jun 2, 2023

Compiler test update boosts Andes RISC-V in automotive

Jun 2, 2023

Adding RISC-V Vector Cryptography Extension support to QEMU

Jun 1, 2023

Linux Foundation and pals – including Intel – back software ecosystem around RISC-V | Dan Robinson, The Register

Jun 1, 2023

Semidynamics launches configurable RISC-V vector unit | Nick Flaherty, EENews Europe

Jun 1, 2023

Axiomise Launches Next-Generation formalISA App for RISC-V Processors

Jun 1, 2023

NOEL-V Processor’s Security Extensions for Safe and Secure Computing

Jun 1, 2023

Andes Technology N25F RISC-V Processor Enables Performance and Low Power for Phison X1 Enterprise SSD Controller

May 31, 2023

RISC-V International Newsletter – May/June 2023

May 31, 2023

The Linux Foundation Europe launches RISE, the RISC-V Software Ecosystem project

May 31, 2023

The RISE Of RISC-V: Accelerating Adoption Through Collaboration And Coordination

May 31, 2023

MIPS Leverages Siemens’ Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor

May 30, 2023

MIPS Leverages Siemens’ Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor

May 30, 2023

AndeSentry™ Collaborative Framework Enables Comprehensive RISC-V Security Solutions

May 30, 2023

Milk-V Surprises with a Second RISC-V SBC — Physically Compatible with the Raspberry Pi 3 Model B

May 30, 2023

Tenstorrent Partners with LG to Build AI and RISC-V Chiplets for Smart TVs of the Future

May 26, 2023

SiFive Announces Exclusive China Event Series

May 25, 2023

Axelera AI increases its Series A funding round to $50m for RISC-V edge AI chip

May 25, 2023

NOEL-V: A RISC-V Processor for High-Performance Space Applications

May 24, 2023

RISC-V: An Open Standard Instruction Set Architecture

May 24, 2023

SiFive Gives WorldGuard to RISC-V International to Make this Robust Security Model More Accessible to the RISC-V Community

May 23, 2023

Imagination launches IMG CXM, the smallest GPU to bring effortless user interfaces into homes

May 22, 2023

RISC-V Announces Agenda for 2023 RISC-V Summit Europe

May 22, 2023

Esperanto Technologies Expands Global Partner Network

May 22, 2023

RISC-V and the Future of Machine Learning Computing

May 20, 2023

Meta details its first custom RISC-V AI silicon

May 19, 2023

Ubuntu on VisionFive 2 RISC-V single board computer

May 19, 2023

Milk-V’s Pioneer Is a Tall Glass of Cold RISC-V with 64 Cores, Up to 128GB of RAM

May 18, 2023

MTIA v1: Meta’s first-generation AI inference accelerator

May 18, 2023

China’s semiconductor developers eye shift to RISC-V architecture amid growing chip demand in cars, data centres and AI, executive says

May 18, 2023

Co-developing RISC-V AI solutions using Vector Extensions in Renode with Kenning

May 18, 2023

T-Head Prototypes Innovative Hardware Support for Virtual IOMMU

May 15, 2023

Yunhao Zhang’s Egos-2000 Packs an Entire RISC-V Operating System Into Just 2,000 Lines of Code

May 15, 2023

India’s RISC-V startup InCore receives funding from Sequoia Capital

May 15, 2023

Andes Technology Announces The New Product Line, AndesAIRE™, Ultimately Efficient AI/ML Solutions For Edge And End-Point Inference

May 15, 2023

[INTERVIEW] Calista Redmond, RISC-V International | Open Source Summit NA 2023

May 15, 2023

Yunhao Zhang’s Egos-2000 Packs an Entire RISC-V Operating System Into Just 2,000 Lines of Code

May 15, 2023

How to Speed Up the Emulating Process with Pydrofoil | Carl Friedrich and Matti Picus

May 15, 2023

Chip War Without Soldiers

May 13, 2023

“Risc” V Opportunity: How The Custom Silicon Wave Will Benefit India’s Semiconductor Ambitions

May 12, 2023

Esperanto Sees A Bright Future For RISC-V In AI And HPC

May 11, 2023

Ubuntu Now Available on the World’s First High-Performance RISC-V SBC with GPU

May 11, 2023

Canonical enables Ubuntu on StarFive’s VisionFive 2 RISC-V single board computer

May 11, 2023

Compiler test update boosts Andes RISC-V in automotive

May 10, 2023

[WEBINAR] Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA Optimization

May 10, 2023

Art Swift, President and CEO of Esperanto Technologies, on RISC-V, HPC, AI, and Generative AI.

May 10, 2023

Canonical enables Ubuntu on StarFive’s VisionFive 2 RISC-V single board computer

May 10, 2023

Launch of the New Horizon Europe Project SYCLOPS

May 5, 2023

Sipeed Teases a $40 Single-Board Computer with Fully-Ratified RISC-V Vector Extensions

May 5, 2023

[PODCAST] Memory Allocation, Digital-Friendly Analog and Configurable 64-bit RISC-V

May 4, 2023

RISC-V ratifies compressed instruction extensions

May 3, 2023

Wearable Payment Solution Based On T-Head Security Technologies

May 2, 2023

Community Growth in India through Vegathon Events | RISC-V International

May 2, 2023

Tenstorrent Selects Arteris IP for HPC RISC-V Chiplets

May 2, 2023

Charles Lohr Turns a $0.10 RISC-V Microcontroller Into a “Software-Defined Flyback” for Nixie Tubes

May 2, 2023

Tenstorrent Selects Arteris IP for AI HPC and Datacenter RISC-V Chiplets

May 2, 2023

Menta, Codasip join RISC-V 3D neuromorphic AI project

May 1, 2023

Making Developers the Protagonists: 2023 RT-Thread Global Tech Conference Registration Opens.

Apr 26, 2023

RISC-V’s Worldwide Expansion and Andes Technology’s Contribution

Apr 26, 2023

RISC-V: Dividing efficiently across different hardware

Apr 24, 2023

Esperanto runs generative-AI on RISC-V

Apr 19, 2023

Esperanto Technologies Announces RISC-V Industry Milestone of Generative AI Models Running on ET-SoC-1; Access to be Made Available to the RISC-V Research Community

Apr 19, 2023

Secure RISC-V accelerator startup VyperCore raises £4 million

Apr 19, 2023

Esperanto Technologies Announces RISC-V Industry Milestone of Generative AI Models Running on ET-SoC-1; Access to be Made Available to the RISC-V Research Community

Apr 19, 2023

Semidynamics Unveils First Customizable RISC-V Cores for End Users

Apr 18, 2023

Accelerate Your Success by Joining RISC-V Membership

Apr 18, 2023

Raising RISC-V processor quality with formal verification

Apr 17, 2023

Spanish startup performs RISC-V open core surgery

Apr 17, 2023

Process agnostic fully customisable RISC-V IP cores

Apr 13, 2023

Scientists Broke a Major Computer Design Barrier — And It Could Change Tech As We Know It

Apr 6, 2023

10 Breakthrough Technologies That Will Profoundly Affect Our Lives

Apr 6, 2023

PINE64 Star64: New single-board computer orderable with RISC-V processor

Apr 6, 2023

India RISC-V gets lift from Tenstorrent JV with Bodhi Computing

Apr 6, 2023

Taking control of data centres is a low-RISC move

Apr 5, 2023

Star64 Is Now Available to Order as PINE64’s First RISC-V SBC

Apr 5, 2023

Tenstorrent Announces Strategic RISC-V Ecosystem Development Partnership with Bodhi Computing Bodhi Computing

Apr 3, 2023

Adapting OpenTitan for open source FPGA prototyping and tooling development

Apr 3, 2023

[PODCAST] Making Formal Verification the New Normal in IoT with Ashish Darbari – Founder, Axiomise | The IoT Podcast

Apr 2, 2023

Announcing the Nerds Talking to Nerds About RISC-V event hosted by Tenstorrent | Tenstorrent

Mar 31, 2023

A dual-core TEE security solution based on E902

Mar 30, 2023

Renesas launches RISC-V voice recognition chip

Mar 28, 2023

Canonical Enables Ubuntu on Microchip’s PolarFire® SoC FPGA

Mar 26, 2023

LLVM 17 Lands Initial Support For RISC-V Vector Crypto Extension ISA

Mar 24, 2023

Catch up with the best of the RISC-V booth from Embedded World 2023

Mar 23, 2023

Embedded World 2023: It’s Time To Architect All Ambitions With Custom Compute

Mar 23, 2023

RISC-V Disrupting EDA

Mar 22, 2023

Top Ten Fallacies About RISC-V

Mar 21, 2023

Tiempo Secure brings additional security features to the RISC-V ecosystem

Mar 21, 2023

The Evolving Automotive Experience Made Possible by RISC-V

Mar 14, 2023

Tenstorrent Opens Office In Japan To Capitalize On RISC-V + AI

Mar 14, 2023

ASUS Unveils The Tinker V As Their First RISC-V Board

Mar 14, 2023

Asus Tinker Board V is the first one with 64-bit RISC-V processor

Mar 14, 2023

Chip Industry’s Technical Paper Roundup: Mar. 14

Mar 14, 2023

Ashling and Imagination announce Ashling’s RiscFree™ C/C++ SDK support for RISC-V-based Catapult family.

Mar 13, 2023

Imperas in RISC-V three way deal

Mar 13, 2023

Trio support RISC-V development from SoC concept to deployment

Mar 13, 2023

Imperas Collaborates with MIPS and Ashling to Accelerate RISC-V Application Software Development from SoC Concept to Deployment

Mar 13, 2023

Why we’ve levelled up on RISC-V

Mar 10, 2023

MachineWare at Embedded World 2023

Mar 10, 2023

Empowering RISC-V with open source innovation from Ubuntu

Mar 10, 2023

First Xuantie Partner Conference in China Highlights Growth Momentum of Thriving RISC-V Community

Mar 9, 2023

What to see at Embedded World 2023

Mar 8, 2023

Canonical enables Ubuntu on Microchip’s PolarFire® SoC FPGA Icicle Kit RISC-V board

Mar 8, 2023

Ubuntu Now Officially Supports Microchip’s PolarFire SoC FPGA Icicle Kit RISC-V Board

Mar 7, 2023

RISC-V Webinar with Andes and Imperas: “RISC-V Design Innovations with Custom Extensions.”

Mar 6, 2023

China accelerates drive for scientific self-sufficiency

Mar 6, 2023

Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community |

Mar 3, 2023

Alibaba’s T-Head foresees RISC-V to support more advanced scenarios in China

Mar 3, 2023

CAST Enhances RISC-V Processor Line for Low-Power and Functional Safety Applications

Mar 3, 2023

CAST Enhances RISC-V Processor Line for Low-Power and Functional Safety Applications

Mar 2, 2023

RISC-V Newsletter – March 2, 2023

Mar 2, 2023

Alibaba and Ant venture to launch RISC-V chips for payments

Feb 27, 2023

Arteris and SiFive Partner to Accelerate RISC-V SoC Design of Edge AI Applications

Feb 27, 2023

Imperas Collaborates with Synopsys on SystemVerilog based RISC-V Verification

Feb 27, 2023

Semiconductor India future design vision involves Design India RISC-V and ChipIn

Feb 27, 2023

Imperas Collaborates with Synopsys on SystemVerilog based RISC-V Verification

Feb 27, 2023

First-ever RISC-V Summit Europe Will Demonstrate Technical and Commercial Momentum Across Industries

Feb 26, 2023

Now is the Time to Pre-order the Revolutionary Risc-v Laptops – Don’t Miss Out on This Cutting Edge Technology!

Feb 24, 2023

RISC-V With Linux 6.3 Lands Optimized String Functions Via Zbb Extension

Feb 24, 2023

Picocom looks to 6G with RISC-V

Feb 24, 2023

Imperas RISC-V verification for Ventana Micro

Feb 24, 2023

Maven Silicon’s RISC-V Processor IP Verification Flow

Feb 23, 2023

Ventana Micro Selects Imperas Solutions for RISC-V Processor Verification

Feb 23, 2023

Maven Silicon’s RISC-V Processor IP Verification Flow

Feb 23, 2023

Ventana Micro Selects Imperas Solutions for RISC-V Processor Verification

Feb 22, 2023

MuseLab’s nanoCH32V003 Puts a 32-bit RISC-V Core on Your Breadboard for Just $1.50

Feb 22, 2023

Microsoft .NET Runtime Lands Initial Code For RISC-V Support

Feb 22, 2023

CH32V003 RISC-V MCU gets $1.5 development board, open source GCC toolchain and flasher utility

Feb 21, 2023

Porting NuttX Real-Time Operating System on PolarFire® SoC FPGA

Feb 18, 2023

The nanoCH32V003 is a RISC-V dev board available for $1.50

Feb 16, 2023

Linux Kernel Address Space Layout Randomization “KASLR” For RISC-V

Feb 14, 2023

Andes and IAR Systems Together Enable Leading Vendor ILITEK to Accelerate the Development of its ISO 26262 Ready TDDI SoC ILI6600A

Feb 14, 2023

ChromeOS now runs on top of Linux and, er, Zephyr …

Feb 14, 2023

Announcing The First International Workshop for HPC based on RISC-V

Feb 13, 2023

IAR Unveils an Updated Brand and Name Change to Support Strategic Mission

Feb 13, 2023

A Closer Look at Security Verification for RISC-V Processors

Feb 13, 2023

RISC-V Linux Patches Start On “zisslpcfi” Support For Control-Flow Integrity

Feb 12, 2023

Hands-on experience with StarFive VisionFive 2 RISC-V SBC using Debian 12

Feb 11, 2023

Open-Source, RISC-V Laptop Will Be Easy to Make and Upgrade

Feb 10, 2023

XuanTie Matrix Multiply Extension Instructions

Feb 10, 2023

TEE SoC Based on RISC-V

Feb 10, 2023

Balthazar – An open-source hardware modular RISC-V, Arm, or FPGA laptop

Feb 9, 2023

The Balthazar laptop: An all-European RISC-V Free Hardware computer

Feb 9, 2023

Is RISC-V Ready For Supercomputing?

Feb 9, 2023

Xen hypervisor port to RISC-V moving – slowly, but moving

Feb 8, 2023

Could RISC-V become a force in high performance computing?

Feb 8, 2023

Could RISC-V become a force in high performance computing?

Feb 7, 2023

CPU RTL co-simulation in Renode

Feb 3, 2023

GreenWaves Technologies announces a €20M financing

Feb 2, 2023

THE First RISC-V Shot Across The Datacenter Bow

Feb 1, 2023

VisionFive 2 RISC-V SBC – A Raspberry Pi Killer?

Jan 30, 2023

FOSDEM 2023 schedule – Open-source Embedded, Mobile, IoT, Arm, RISC-V, etc… projects

Jan 30, 2023

NASA Recruits Microchip, SiFive, and RISC-V to Develop 12-Core Processor SoC for Autonomous Space Missions

Jan 30, 2023

Espressif adopts RISC-V for next gen EPS32s, adds Wi-Fi 6 and BT 5

Jan 29, 2023

What’s next for RISC V?

Jan 26, 2023

What Does 2023 Have In Store For Chip Design?

Jan 26, 2023

5 Takeaways From The RISC-V Summit

Jan 26, 2023

5 Takeaways From The RISC-V Summit

Jan 26, 2023

Intel & SiFive Reveal RISC-V Development Board With Quad-Core CPU Based On Intel 4 Process

Jan 25, 2023

Google’s Flutter showcases new graphics capabilities, WebAssembly and RISC-V support

Jan 25, 2023

Xuantie RISC-V TEE solution for MCU

Jan 24, 2023

RISC-V RV32I RTL Verification using UVM | Maven Silicon Blog

Jan 24, 2023

These simple design rules could turn the chip industry on its head

Jan 24, 2023

HiFive Pro P550 “Horse Creek” RISC-V motherboard with 16GB RAM to launch this summer

Jan 24, 2023

Bluespec Teams Up with Synopsys for RISC-V Core Verification Effort

Jan 23, 2023

The Semiconductor Shortage: How RISC-V & Other Technologies are Taking Advantage

Jan 23, 2023

RISC-V Foundation’s Chairman says: “All Your Cores Are Belong to Us”

Jan 23, 2023

SiFive, Intel Announce HiFive Pro P550 MicroATX RISC-V Development Board

Jan 20, 2023

The First DSA Agile Development on Open Xuantie RISC-V processor

Jan 20, 2023

SiFive HiFive Pro P550 dev board coming this summer with Intel “Horse Creek” RISC-V chip

Jan 20, 2023

HPMicro HPM64G0 – A 1 GHz RISC-V microcontroller

Jan 18, 2023

Selecting The Right RISC-V Core | Brian Bailey, Semiconductor Engineering

Jan 17, 2023

Risc-V MCUs have 8 to 20 pins

Jan 17, 2023

Late Night Linux – Episode 212

Jan 16, 2023

Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community

Jan 16, 2023

Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community

Jan 16, 2023

EEVblog 1524 – The 10 CENT RISC V Processor! CH32V003

Jan 16, 2023

Selecting The Right RISC-V Core

Jan 16, 2023

$4 Sipeed M0S Dock IoT development board features BL616 WiFi 6, BLE 5.2, and Zigbee RISC-V microcontroller

Jan 16, 2023

GraalVM Native Image meets RISC-V

Jan 16, 2023

Running Plasma on VisionFive-2

Jan 14, 2023

Kung-Fu Perribot with RISC-V

Jan 14, 2023

Low-cost RISC-V BL616 module supports TinyML

Jan 13, 2023

RISC-V Bytes: Timer Interrupts

Jan 13, 2023

Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool

Jan 13, 2023

Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms

Jan 13, 2023

Andes Unveils Details of its Entry Level D23 RISC-V Processor Core

Jan 12, 2023

The RISC-V Mentorship Program – a 2022 Recap, What’s to Come for 2023, and How to Apply

Jan 12, 2023

Support for Microchip’s RISC-V Platforms in Antmicro’s Open-Source Renode Framework and Beyond

Jan 11, 2023

RISC-V Celebrates Momentum of 2022 and Accelerating Adoption in 2023

Jan 11, 2023

RISC-V Celebrates Momentum of 2022 and Accelerating Adoption in 2023

Jan 11, 2023

Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community

Jan 10, 2023

Andes Webinar 2023 | Andes President and CTO, Dr. Charlie Su, Andes Technology

Jan 10, 2023

RISC-V Reaches a Turning Point | James Sanders and Wayne Lam, CCS Insights

Jan 10, 2023

Removing the Risk from RISC-V using the RISC-V Trace Standard | Peter Shields, Siemens

Jan 10, 2023

El Correo Libre Issue 58 | Gareth Halfacree, FOSSSi Foundation

Jan 10, 2023

Espressif ESP32-P4 – A 400 MHz general-purpose dual-core RISC-V microcontroller | Jean-Luc Aufranc, CNX Software

Jan 10, 2023

Everyone deserves a Pinecil | Chris Person, The Verge

Jan 9, 2023

My open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC Course

Jan 9, 2023

My open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC Course

Jan 9, 2023

Implementation of RISCduino core using a Hierarchical Design Flow | Dinesh Annayya, OpenRoad

Jan 9, 2023

MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un | Steve Leibson, EE Journal

Jan 9, 2023

A chip design that changes everything: 10 Breakthrough Technologies 2023 | Sophia Chen, MIT Technology Review

Jan 9, 2023

RISC-V Hibernation Support / Suspend-To-Disk Nears The Linux Kernel | Michael Larabel, Phoronix

Jan 9, 2023

Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro Olivieri

Jan 7, 2023

TCADer: A Tightly Coupled Accelerator Design framework for heterogeneous system with hardware/software co-design based on RISC-V | Wenqing Li, Tianyi Liu, Ziyuan Xiao HanQi, Weipu Zhu, Jian Wang

Jan 7, 2023

VisionFive 2: RISC-V Quad Core Low Cost SBC | Christopher Barnatt, Explaining Computers

Jan 6, 2023

Podcast EP135: Democratizing HPC & AI | Inspire Semiconductor, Semiwiki.com

Jan 6, 2023

Alexander Williams’ FiveForths Is a “Hand-Written” RISC-V Assembly Forth for Microcontrollers | Gareth Halfacree, Hackster.io

Jan 6, 2023

Week In Review: Design, Low Power | Marie C. Baca, Semiconductor Engineering

Jan 5, 2023

Recommendation for a holistic secure embedded ISA extension | Florian Stolz, Marc Fyrbiak, Pascal Sasdrich, Tim Güneysu

Jan 5, 2023

MangoPi MQ-PRO Review: RISC-V Raspberry Pi Zero Alternative? | Learn Embedded Systems

Jan 5, 2023

Google to Make RISC-V a Major Platform for Android | Robin Mitchell, Electropages

Jan 5, 2023

How Secure Are RISC-V Chips? | Jeff Goldman, Semiconductor Engineering

Jan 5, 2023

Grokking RISC-V Vector Processing | Erik Engheim, ITNext

Jan 5, 2023

Exploring the Benefits of RISC-V ISA for Posit Arithmetic at HiPEAC Conference | Federico – The AI Blog

Jan 5, 2023

News Espressif Reveals ESP32-P4: A High-Performance MCU with Numerous IO-Connectivity and Security Features | Espressif Systems

Jan 5, 2023

Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro Systems

Jan 5, 2023

A Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators | Guillaume Devic, Gilles Sassatelli and Abdoulaye Gamatié

Jan 4, 2023

Run 32-bit applications on 64-bit Linux kernel | LIU Zhiwei, GUO Ren| T-Head Division of Alibaba Cloud

Jan 4, 2023

Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro Systems, Yahoo! Finance

Jan 4, 2023

RISC-V could become a first-class citizen for Android, Pixel 7a hands-on video leaked, and GeForce Now adds a RTX 4080 tier | Brad Linder, Liliputing

Jan 4, 2023

SpacemiT Makes Important Breakthroughs in RISC-V High-Performance Cores | SpacemiT

Jan 3, 2023

Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios | Breker Verification Systems

Jan 3, 2023

Google wants RISC-V to be a “tier-1” Android architecture | Ron Amadeo, Ars Technica

Jan 3, 2023

RISC-V Summit 2022: All Your CPUs Belong to Us | Kevin Krewell, EE Times

Jan 3, 2023

Mouser Now Stocking Renesas Electronics RZ/Five-RISC-V Microprocessor for IoT Endpoint and Industrial Gateway Apps | ELE Times

Jan 3, 2023

RISC-V chip to drive next generation app store of hearables | Nick Flaherty, EENews Europe

Jan 3, 2023

What is the Titan M2 security chip in Google’s Pixel phones? | Calvin Wankhede, Android Authority

Jan 2, 2023

StarFive Releases StarFive StarStudio IDE, which supports both Linux and Baremetal Development | StarFive

Jan 2, 2023

Arm’s push into cars ‘a logical step’ as competition grows from open-source RISC-V | Thomas Macaulay, The Next Web

Jan 1, 2023

How to Deploy a Neural Network on TH1520 | Wenmeng Zhang, Alibaba Cloud

Jan 1, 2023

Standardized Open-Source Processor Architecture | Jon Gabay, Mouser Electronics

Jan 1, 2023

Allwinner D1/D1s Platform Support Moves Closer To Mainline Linux | Michael Larabel, Phoronix

Jan 1, 2023

MProtect: Operating System Memory Management without Access | Caihua Li, Seung-seob Lee, Min Hong Yun, Lin Zhong

Jan 1, 2023

A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance | Yuhao Ju; Jie Gu

Jan 1, 2023

IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms | Kejun Chen; Orlando Arias; Xiaolong Guo; Qingxu Deng; Yier Jin

Jan 1, 2023

McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework | Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou; Bei Yu

Jan 1, 2023

GHAZI: An Open-Source ASIC Implementation of RISC-V based SoC | Zain Rizwan Khan, Wajeh ul Hasan, Zeeshan Rafique, Ali Ahmed Ansari, Syed Roomi Naqvi

Jan 1, 2023

How to reduce the risk when making the shift to RISC-V | Rupert Baines, Codasip

Jan 1, 2023

From RISC-V to 3D NAND Technology—Looking Back at the Trends of 2022 | Kimber Wymore, All About Circuits

Dec 31, 2022

Year 2022 in review – Top 10 posts and statistics | Jean-Luc Aufranc, CNX Software

Dec 29, 2022

RISC-V on the Final Frontier | Embedded Computing Design Staff, Embedded Computing Design

Dec 27, 2022

Bouffalo Lab BL616/BL618 RISC-V MCU supports WiFi 6, Bluetooth 5.2, and Zigbee | Jean-Luc Aufranc, CNX Software

Dec 24, 2022

Lichee RV 86 Panel Getting Started Guide | James A. Chambers, Legendary Technology Blog

Dec 23, 2022

RISC-V Honors Outstanding Technical and Community Contributions for 2022

Dec 22, 2022

BSC Develops 4 Open-Source Hardware Components Based on RISC-V | HPC Wire

Dec 22, 2022

Tencent joins open-source chip design community RISC-V as China seeks to mitigate impact from US sanctions | Che Pan, South China Morning Post

Dec 22, 2022

Adapting To Broad Shifts Essential In 2022 | Brian Bailey, Semiconductor Engineering

Dec 22, 2022

RISC-V Pushes Into The Mainstream | Marie C. Baca and Ed Sperling, Semiconductor Engineering

Dec 20, 2022

XuanTie C908 Accelerates AI with Software and Hardware Fusion

Dec 19, 2022

Server-class RISC-V Core Unveiled by Ventana at RISC-V Summit | Aaron Carman, All About Circuits

Dec 19, 2022

Efficient Trace In RISC-V | Ed Sperling, Semiconductor Engineering

Dec 18, 2022

How RISC-V has become a viable third processor architecture | Dean Takahashi, Venture Beat

Dec 17, 2022

RISC-V Adds Support For Persistent Memory Devices In Linux 6.2 | Michael Larabel, Phoronix

Dec 16, 2022

Europe to Dish out €270 Million to Build RISC-V Hardware and Software | Agam Shah, HPC Wire

Dec 16, 2022

Imagination’s RISC-V gambit reaches its next level | Majeed Ahmad, EDN

Dec 16, 2022

“RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes | Jeff Child, All About Circuits

Dec 16, 2022

New CAES, IAR Systems Partnership Brings NOEL-V Support to IAR Embedded Workbench

Dec 15, 2022

Qualcomm talks up RISC-V, roasts ‘legacy architecture’ amid war with Arm | Dylan Martin, The Register

Dec 15, 2022

Solutions Disclosed at RISC-V Summit: Security, Verification, and More | Jake Hertz, All About Circuits

Dec 15, 2022

A Growing Ecosystem for Intel Pathfinder for RISC-V | Intel Pathfinder for RISC-V, EE Times India

Dec 15, 2022

New Dev Platforms Bring RISC-V to the Forefront of Innovation (Part 2) | Cabe Atwell, Electronic Design

Dec 15, 2022

Finally, A Company Shows That You Can Have A High-Performance RISC-V Solution With RAS Capabilities | Patrick Moorhead, Forbes

Dec 15, 2022

Alibaba’s T-Head chip unit demonstrates Android compatibility on RISC-V chips | TechNode

Dec 14, 2022

Sokol Flex OS supports RISC-V | David Manners, Electronics Weekly

Dec 14, 2022

Sipeed Teases a RISC-V System-on-Module That “Beats the Raspberry Pi 4” in Performance | Gareth Halfacree, Hackster.io

Dec 14, 2022

Imagination extends its commitment to RISC-V with an upgrade to Premier level membership

Dec 14, 2022

Siemens pioneers commercial grade Linux support for the RISC-V architecture

Dec 14, 2022

RISC-V SBC VisionFive 2 Officially Shipped

Dec 13, 2022

CHIPS Alliance Welcomes the Caliptra Open Source Root of Trust Project

Dec 13, 2022

Examining the Top Five Fallacies About RISC-V

Dec 13, 2022

Ventana Introduces Veyron, World’s First Data Center Class RISC-V CPU Product Family

Dec 13, 2022

RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in Market

Dec 13, 2022

Ashling announce availability of their new Vitra-XS Debug & Trace Probe

Dec 12, 2022

XMOS Announces Software-defined SoC Platform Now Compatible with RISC-V

Dec 12, 2022

Codasip Launches SecuRISC5 initiative

Dec 12, 2022

Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification

Dec 8, 2022

Microchip Showcases RISC-V-Based FPGA and Space-Compute Solutions at RISC-V Summit

Dec 8, 2022

Imperas and Imagination Collaborate on Providing Virtual Platform Models for the Catapult RISC-V CPU Family

Dec 7, 2022

Codasip Launches Codasip Labs to Accelerate Advanced Technologies

Dec 7, 2022

Andes Announces RISC-V Multicore 1024-Bit Vector Processor: AX45MPV

Dec 7, 2022

Andes Technology Unveils The AndesCore™ D23, A Feature-Rich, Low-Power And Highly-Secured Entry-Level RISC-V Processor

Dec 7, 2022

Join Andes At RISC-V Summit; Learn The Only ISO 26262 Fully-Compliant RISC-V CPU, The Latest Multicore 4-Way Out-Of-Order Processor & The Multicore 1024-Bit Vector Processor

Dec 7, 2022

Andes Technology And Parasoft Collaborate To Provide Seamless Software Testing Tools For Automotive Functional Safety Applications

Dec 7, 2022

MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors

Dec 6, 2022

Standard Library Expertise at the RISC-V Summit Presented by Solid Sands

Dec 6, 2022

RISC-V Based IoT Platform Development Using Green Hills Software

Dec 5, 2022

INTEL PATHFINDER FOR RISC-V: NEW CAPABILITIES AND A GROWING ECOSYSTEM | Intel Corporation

Dec 5, 2022

RISC-V: An Open-Source Churn In Computational Hardware Electronics – Part 2 | Dr Santhosh Onkar, Swarajya

Dec 5, 2022

Imperas and Andes collaborate to support RISC-V innovations | Andes Technology and Imperas Software

Dec 5, 2022

UniHiker education platform teaches STEM with Mind+ and Jupyter (in China) | Jean-Luc Aufranc, CNX Software

Dec 5, 2022

CEVA joins Intel Pathfinder for RISC-V programme | CEVA, New Electronics

Dec 5, 2022

Sipeed M1s DOCK is a tiny RISC-V dev board for $11 | Brad Linder, Liliputing

Dec 5, 2022

$10.80 RISC-V AIoT module supports Linux | Giorgio Mendoza, Linux Gizmos

Dec 5, 2022

Codasip and Intel bring RISC-V development to higher-education | Codasip

Dec 5, 2022

Is your career at RISK without RISC-V? | P R Sivakumar, Founder and CEO, Maven Silicon

Dec 5, 2022

Simon Davidmann President & CEO of Imperas Software elected as Chair of the OpenHW Verification Task Group

Dec 2, 2022

Solid Sands Announces Major New Enhancements to SuperGuard

Dec 2, 2022

Imperas RISC-V Summit Kickoff Party, December 12 2022

Dec 1, 2022

RISC-V Summit 2022: Future Careers Start Here

Nov 30, 2022

RISC-V Summit 2022: A Journey from Android to Outer Space … and Much More | RISC-V International

Nov 29, 2022

CAES Design Win of RISC-V/NOEL-V IP for Idaho Scientific Secure Processor for US Critical Infrastructure

Nov 29, 2022

Imperas and Andes collaborate to support RISC-V innovations

Nov 28, 2022

Cortus announces two new RISC-V microcontrollers (MCUs) Lotus family

Nov 24, 2022

2022 RISC-V Summit Technical Tutorials Announced | RISC-V International

Nov 22, 2022

RISC-V开发板大派送，CNRV社区助你开启RISC-V创作之旅

Nov 18, 2022

11 Myths About Using Formal Verification

Nov 15, 2022

NASA Uses RISC-V Vector Spec to Soup Up Space Computers | Chenny Wang, EE Times

Nov 10, 2022

Secure-IC acquires Silex Insight’s security business to accelerate its chip-to-cloud plan and develop the next-generation of embedded cybersecurity solutions

Nov 7, 2022

RISC-V Is Thriving: Here’s What You Need To Know | Steve Brown, Semiconductor Engineering

Nov 7, 2022

SiFive launches Performance P670 and P470 RISC-V energy efficient processors | Bogdan Solca, Notebook Check

Nov 7, 2022

Codasip, SiliconArts team on RISC-V ray tracing graphics IP | Nick Flaherty, EE News Europe

Nov 5, 2022

SEGGER introduces streaming trace probe for SiFive RISC-V cores | SEGGER

Nov 4, 2022

Open source TileLink to AHB bridges with dedicated Cocotb extensions | Antmicro

Nov 4, 2022

Lilbits: RISC-V and de-Googled phones, and Qualcomm sees 2024 as the year of the Snapdragon-powered PC | Brad Linder, Liliputing

Nov 4, 2022

Andes unveils AndesCore AX65 Out-of-Order RISC-V core for compute intensive applications | Jean-Luc Aufranc, CNX Software

Nov 3, 2022

Android Open Source Project ports to RISC-V | Nick Flaherty, EE News Europe

Nov 3, 2022

XuanTie C908: High-performance RISC-V Processor Catered to AIoT Industry | Chang Liu, Alibaba Cloud

Nov 2, 2022

SiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions | Jean-Luc Aufranc, CNX Software

Nov 2, 2022

With its New RISC-V Processors, SiFive Bets on Compute Density | Jeff Child, All About Circuits

Nov 2, 2022

SiFive Reveals New RISC-V Chips, the P670 and P470 | Ian Evenden, Tom’s Hardware

Nov 2, 2022

Registration for the In-person RVfpga Session at the 2022 RISC-V Summit is Open. Space is Limited! | Imagination Technologies

Nov 2, 2022

T-Head XuanTie C908 RISC-V core targets AIoT applications | Jean-Luc Aufranc, CNX Software

Nov 2, 2022

DongshanPI-D1s is a RISC-V Development Board for Less Than $20 | Ian Evenden, Tom’s Hardware

Nov 2, 2022

DongshanPI-D1s – An Allwinner D1s RISC-V development board designed to teach programming | Jean-Luc Aufranc, CNX Software

Nov 2, 2022

SiFive releases high-performance processors for small-size, high-volume applications | Judy Lin, DIGITIMES Asia

Nov 1, 2022

High-performance RISC-V cores from SiFive | Steve Bush, Electronics Weekly

Nov 1, 2022

The Android Open Source Project Is Now RISC-V Compatible | Laveesh Kocher, Open Source For You

Nov 1, 2022

SiFive aims for ARM with high performance RISC-V vector cores | Nick Flaherty, EE News Europe

Oct 28, 2022

Ubuntu continues expanding RISC-V support – now, the $17 Sipeed LicheeRV | Tobias Mann, The Register

Oct 27, 2022

5 Good Things About RISC-V | Filip Benna, Semiconductor Engineering

Oct 27, 2022

WCH Launches a Sub-10¢ RISC-V Microcontroller, While a $6.90 Dev Board Gets You Started | Gareth Halfacree, Hackster.io

Oct 26, 2022

uConsole is a modular Arm for RISC-V handheld computer with optional 4G connectivity | Jean-Luc Aufranc

Oct 25, 2022

Ubuntu 22.10 Up And Running On The LicheeRV ~$19 RISC-V Board | Michael Larabel, Phoronix

Oct 25, 2022

Hardware Trojan Inserted Inside A RISC-V Based Automotive Telematics Control Unit | Moschos, Athanasios, Kevin Valakuzhy, and Angelos D. Keromytis, Semiconductor Engineering

Oct 25, 2022

InspireSemi to Ring the Toronto Stock Exchange Closing Bell on October 25 | InspireSemi

Oct 24, 2022

Ventana Micro Brings RISC-V Into The Data Center | Karl Freund, Forbes

Oct 23, 2022

First Patches from Alibaba Cloud Enable Android Open Source Project on RISC-V | Han Mao and David Chen, Alibaba Cloud

Oct 23, 2022

RISC-V Celebrates Upstreaming of Android Open Source Project RISC-V Port | RISC-V International

Oct 22, 2022

10 cents CH32V003 RISC-V MCU offers 2KB SRAM, 16KB flash in SOP8 to QFN20 packages | Jean-Luc Aufranc, CNX Software

Oct 22, 2022

Rise of RISC-V: The computer chip design you need to know about | Stephen Vicinanza, Interesting Engineering

Oct 21, 2022

Google Announces New Open-source OS for RISC-V Chips | Darshil Patel, All About Circuits

Oct 20, 2022

Ubuntu 22.10 Released With Improved Steam App, GNOME 43, RISC-V Support | Ian Evenden, Tom’s Hardware

Oct 18, 2022

Espressif ESP8684 RISC-V WiFi & BLE MCU embeds up to 4MB flash in a 4x4mm package | Jean-Luc Aufranc, CNX Software

Oct 18, 2022

Google comes up with new OS for RISC-V | Nick Farrell, Fudzilla

Oct 17, 2022

‘First’ RISC-V CPU certified compliant with ISO 26262 | Steve Bush, Electronics Weekly

Oct 17, 2022

Ox64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux Gizmos

Oct 17, 2022

Andes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance | Yahoo! Finance

Oct 17, 2022

IAR Systems’ Functional Safety Certified Development Tools for RISC-V support latest SiFive Automotive Solutions | IAR Systems

Oct 17, 2022

IAR boosts its automotive RISC-V support | Nick Flaherty, EE News Europe

Oct 17, 2022

Ox64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux Gizmos

Oct 17, 2022

Google shows off KataOS, a secure operating system written in Rust | Liam Tung, ZDNET

Oct 17, 2022

IAR boosts its automotive RISC-V support | Nick Flaherty, EE News Europe

Oct 17, 2022

Andes claims first RISC-V CPU IP with full ISO 26262 compliance, plans DSP version | Nick Flaherty, EE News Europe

Oct 15, 2022

What Is RISC, What Is RISC V, and How Do They Differ? | Arol Wright, Make Use Of

Oct 14, 2022

First RISC-V laptop uses Alibaba TH1520 SoC | Nitin Dahad, Embedded

Oct 12, 2022

French secure element processor uses RISC-V | Nick Flaherty, EE News Europe

Oct 12, 2022

RISC-V Virtual Prototype | Pieper, P.; Herdt, V.; Drechsler, R., Semiconductor Engineering

Oct 12, 2022

Tiempo Secure becomes a Strategic Member of RISC-V International | Tiempo Secure

Oct 11, 2022

Intel demos “Horse Creek” developer board with SiFive RISC-V CPU, DDR5 RAM and PCIe 5.0 slot | Bogdan Solca, Notebook Check

Oct 11, 2022

RiVAI Technologies Announced New Products in Their RISC-V Vector DSP IP Family: RiVAI V7 And RiVAI V9+ | RiVAI Technologies

Oct 10, 2022

Andes Technology Announces Return of the Annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel | Andes Technology

Oct 10, 2022

Alibaba RISC-V SoC Revealed as Processor for First RISC-V Laptop | Jake Hertz, All About Circuits

Oct 10, 2022

Intel Horse Creek platform showcased with SiFive P550 RISC-V CPU, 8GB DDR5, PCIe Gen5 | Jean-Luc Aufranc, CNX Software

Oct 10, 2022

Pine64’s RISC-V Ox64 Takes On Raspberry Pi Pico W | Ian Evenden, Tom’s Hardware

Oct 10, 2022

PINE64 Unveils the Ox64, a Low-Cost Dual-Core RISC-V Single-Board Computer with Breadboard Support | Gareth Halfacree. Hackster.io

Oct 10, 2022

Pine64 Ox64 SBC to feature BL808 64-bit/32-bit RISC-V multi-protocol WiSoC with 64MB built-in RAM | Jean-Luc Aufranc, CNX Software

Oct 10, 2022

Make the Most of Rad-Hard RTG4 FPGAs with the Right Approach to Timing and Resets | Microchip Technology

Oct 9, 2022

Intel’s Horse Creek dev board features SiFive P550 RISC-V processor and 8GB RAM | Brad Linder, Liliputing

Oct 7, 2022

It’s Time to Consider RISC-V | Rob Enderle, SD Times

Oct 6, 2022

VisionFive 2 RISC-V Board Available For Pre-Order | Ian Evenden, Tom’s Hardware

Oct 6, 2022

RISC-V International Announces Agenda for RISC-V Summit 2022 | RISC-V International

Oct 5, 2022

China may prove Arm wrong about RISC-V’s role in the datacenter | Tobias Mann, The Register

Oct 5, 2022

VisionFive 2 RISC-V single-board computer is up for pre-order for $56 and up | Brad Linder, Liliputing

Oct 4, 2022

Alibaba T-Head TH1520 RISC-V processor to power the ROMA laptop | Jean-Luc Aufranc, CNX Software

Oct 3, 2022

Announcing RISC-V International’s Expanded Developer Boards Program | RISC-V International

Oct 3, 2022

DeepComputing and Xcalibyte announce the ROMA laptop will be powered by TH1520 – the first SoC from Wujian 600’s platform by Alibaba T-Head | Xcalibyte

Oct 3, 2022

Dev board for 32bit GigaDevice RISC-V | Steve Bush, Electronics Weekly

Oct 3, 2022

Linux 6.0 release – Main changes, Arm, RISC-V, and MIPS architectures | Jean-Luc Aufranc, CNX Software

Oct 2, 2022

XuanTie Security System Promotes Rapid Migration of Security Applications from Arm to RISC-V | Vincent Cui, Alibaba Cloud

Oct 1, 2022

SiFive has licenses C++ library for Risc-V | Steve Bush, Electronics Weekly

Oct 1, 2022

Researchers Build a RISC-V Chip That Calculates in Posits, Boosting Accuracy for ML Workloads | Gareth Halfacree, Hackster.io

Oct 1, 2022

Framework Based On An RISC-V Microprocessor Supporting LiM Operations | Coluccio, A.; Ieva, A.; Riente, F.; Roch, M.R.; Ottavi, M.; Vacca, M. RISC-Vlim, Semiconductor Engineering

Oct 1, 2022

Acceleration Robotics Partners with PlanV for a Robotics-Specific Open Source RISC-V Microcontroller | Gareth Halfacree, Hackster.io

Oct 1, 2022

Google experiments with RISC-V | Nick Farrell, Fudzilla

Oct 1, 2022

The Automotive Space Gears Up to Take on RISC-V | Murray Slovick, Electronic Design

Sep 27, 2022

Customising PolarFire® SoC FPGA for International Space Station Mission | Microchip Technology

Sep 23, 2022

ST to make European octacore RISC-V space chip with selectable cores | Nick Flaherty, EE News Europe

Sep 23, 2022

Arm vs RISC-V? Which One Is The Most Efficient? | Gary Explains

Sep 23, 2022

Native RISC-V ROS chip targets robotics | Nick Flaherty, EE News Europe

Sep 23, 2022

SiFive RISC-V cores picked for Google AI compute nodes | Dan Robinson, The Register

Sep 22, 2022

Google deploys SiFive’s Intelligence X280 processor for AI workloads | Sebastian Moss, Data Center Dynamics

Sep 22, 2022

Codasip joins OpenHW to push RISC-V verification | Nick Flaherty, EE News Europe

Sep 22, 2022

ARM IS THE NEW RISC/UNIX, RISC-V IS THE NEW ARM | Timothy Prickett Morgan, The Next Platform

Sep 20, 2022

Oracle brews Java 19. Mmmm, kinda tastes like RISC-V | Thomas Claburn, The Register

Sep 13, 2022

Renesas unveils motor control RISC-V ASSP | Gina Roos, Electronic Products

Sep 13, 2022

Renesas delivers RISC-V based motor control ASSP | Nitin Dahad, Embedded.com

Sep 13, 2022

SoC.one and Imagination to enable adoption of RISC-V for automotive design | Neil Tyler, New Electronics

Sep 13, 2022

SiFive Rolls Out Powerful New RISC-V Portfolio to Address Unmet Performance and Feature Needs of Rapidly Evolving Next-Gen Digital Automobiles | SiFive

Sep 12, 2022

Cortus Announces the Launch of its New Secure Low Power RISC-V Microcontrollers | Cortus S.A.S

Sep 9, 2022

The Open Source Ztachip Is a RISC-V Accelerator for Edge AI and Computer Vision Applications | Gareth Halfacree, Hackster.io

Sep 9, 2022

RISC-V Does Motor Control | William G. Wong, Electronic Design Magazine

Sep 9, 2022

NASA Taps SiFive’s RISC-V Core for its Spaceflight Processor | Jake Hertz, All About Circuits

Sep 9, 2022

Intel Shows Support for RISC-V Chip Design With Intel Pathfinder | Jake Hertz, All About Circuits

Sep 9, 2022

Dolpin Design teams for RISC-V Headphone 3.0 chips | Nick Flaherty, EE News Europe

Sep 8, 2022

RISC-V to Launch into Space | James Morra, Electronic Design Magazine

Sep 8, 2022

NASA’s new space computer to be powered by custom RISC-V processor | Joel Khalili, Tech Radar

Sep 8, 2022

Andes Technology Corp. Announces Its RISC-V CPU IP Serves as the Computing Engine in the New Renesas R9A02G020 MCU ASSP | Andes Technology

Sep 8, 2022

First RISC-V chip optimised for motor control | Nick Flaherty, EE News Europe

Sep 8, 2022

Renesas extends RISC-V Embedded Processing portfolio | Neil Tyler, New Electronics

Sep 8, 2022

RISC-V-Based ASSP EASY – The Start of a New Development Journey | Giancarlo Parodi, Renesas

Sep 8, 2022

Renesas Extends Leading RISC-V Embedded Processing Portfolio with New Motor Control ASSP Solution | Renesas

Sep 8, 2022

NASA, Microchip, SiFive Announces Partnership for RISC-V Spaceflight Computing Platform | Gareth Halfacree, Hackster.io

Sep 7, 2022

Renodepedia – From Zephyr’s structured data to traceable and testable open hardware with Renode | Antmicro

Sep 7, 2022

NASA has chosen these CPUs to power its next generation of spaceflight computers | Liam Tung, ZD Net

Sep 7, 2022

Alibaba Cloud Reveals New RISC-V Development Platform | Robin Mitchell, Electropages

Sep 6, 2022

NASA Selects SiFive and Makes RISC-V the Go-to Ecosystem for Future Space Missions | SiFive, Business Wire

Sep 6, 2022

SiFive RISC-V CPU cores to power NASA’s next spaceflight computer | Tobias Mann, The Register

Sep 5, 2022

SOC Verification Flows and Methodologies | Sivakumar P R, Maven Silicon

Sep 2, 2022

Four things to know about the Intel Pathfinder for RISC-V | Majeed Ahmad, EDN

Sep 1, 2022

Intel Pathfinder for risc-v delivers new capabilities silicon development | Scientific Computing World

Sep 1, 2022

Intel puts more weight behind RISC-V with Pathfinder platform | Nitin Dahad, Embedded.com

Sep 1, 2022

Intel leans harder on RISC-V | Chris Edwards, Engineering & Technology

Sep 1, 2022

SoC.one Cloud Accelerates Adoption within Intel Pathfinder for RISC-V Ecosystem | SoC.one Inc.,

Aug 31, 2022

How will you share your RISC-V knowledge and wisdom? | RISC-V International

Aug 31, 2022

TRACE32® on XuanTie CPUs | LiFeng, Alibaba and Frank Xing, Lauterbach China

Aug 30, 2022

RISC-V International and Intel team up to accelerate RISC-V adoption: Introducing Intel Pathfinder for RISC-V | Intel Corporation

Aug 30, 2022

Intel launches Pathfinder development kit for RISC-V | Judy Lin, DigiTimes

Aug 30, 2022

Andes and Green Hills Collab Yields RISC-V-based SoC for Automotive Safety | Abdulwaliy Oyekunle, All About Circuits

Aug 30, 2022

Andes Technology Corp Announces Its Joined Intel Pathfinder | Andes Technology

Aug 30, 2022

European tech in Intel’s RISC-V Pathfinder dev kit | Nick Flaherty, EE News Europe

Aug 30, 2022

PINE64 Shows Off the First Star64 RISC-V Single-Board Computer Prototypes, Targets a Launch in Weeks | Gareth Halfacree, Hackster.io

Aug 30, 2022

RISC-V International and Intel team up to accelerate RISC-V adoption: Introducing Intel Pathfinder for RISC-V | Intel

Aug 30, 2022

Imperas partners with Intel Pathfinder for RISC-V | Imperas Software

Aug 30, 2022

SoC.one Cloud Accelerates Adoption within Intel Pathfinder for RISC-V Ecosystem | SoC.one

Aug 30, 2022

LeapFive Eyes High-performance Realm with 1.8 GHz RISC-V SoC | Chantelle Dubois, All About Circuits

Aug 30, 2022

Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V | MIPS

Aug 30, 2022

Crypto Quantique’s quantum-driven silicon IP enables root-of-trust in the Intel Pathfinder for RISC-V environment | Crypto Quantique

Aug 30, 2022

Intel Chooses Check Point Software Technologies to Enable Security for New Intel Pathfinder for RISC-V Platform | Check Point Software Technologies INC

Aug 30, 2022

VisionFive 2 quad-core RISC-V dev board | Julian Horsey, Geeky Gadgets

Aug 29, 2022

NSITEXE, OTSL, Kyoto Microcomputer, AXELL, Collaborate to develop RISC-V based Reliable Edge AI platform | NSITEXE

Aug 29, 2022

Lilbits: PineBuds Pro, PlayStation Studios Mobile Division, and StarFive JH7110 RISC-V chip details | Brad Linder, Liliputing

Aug 29, 2022

Pine64 Star64 SBC to feature StarFive JH7110 quad-core RISC-V processor with Imagination GPU | Jean-Luc Aufranc, CNX Software

Aug 29, 2022

StarFive JH7110 RISC-V processor specifications released | Jean-Luc Aufranc, CNX Software

Aug 29, 2022

RISC-V pioneer raises funds for IoT, automotive | Peter Clarke, EE News Europe

Aug 28, 2022

StarFive Announced 2 High-Performance RISC-V Products: JH7110 SoC and VisionFive 2 SBC | StarFive

Aug 28, 2022

StarFive Announced 2 High-Performance RISC-V Products: JH7110 SoC and VisionFive 2 SBC | Design and Reuse

Aug 28, 2022

Pine64 reveals the Star64 RISC-V based Single Board Computer | Giorgio Mendoza, Linux Gizmos

Aug 27, 2022

RISC-V Universe Grows with New GPUs, CPUs, and Development Kits | Abdulwaliy Oyekunle, All About Circuits

Aug 26, 2022

As Alibaba declares new RISC-V milestone, is automotive MCU the next battleground? | Misha Lu, DigiTimes

Aug 26, 2022

Alibaba releases RISC-V development platform | Nick Farrell, Fudzilla

Aug 26, 2022

Dragon Li’s Bajiu Lite Is a Flexible FPGA Development Board with RISC-V SoC Capabilities | Gareth Halfacree, Hackster.io

Aug 26, 2022

Pinecil V2 Review: Smart Soldering Iron, Powered by RISC-V CPU | Les Pounder, Tom’s Hardware

Aug 25, 2022

Canonical enables Ubuntu on Allwinner’s Nezha RISC-V boards | Canonical

Aug 25, 2022

Alibaba Cloud unveils RISC-V chip development platform | Aaron Tan, Computer Weekly

Aug 25, 2022

Alibaba Cloud launches RISC-V chip-development platform | TechNode

Aug 25, 2022

Imagination teams for RISC-V development platform for edge AI chips | Nick Flaherty, EE Time Europe

Aug 25, 2022

Imagination’s GPU and AI Accelerator Licensed for the latest AIoT RISC-V-based applications | Imagination Technologies

Aug 25, 2022

Imagination’s GPU and neural processor on Alibaba Risc-V AI chip | Steve Bush, Electronics Weekly

Aug 25, 2022

Andes Technology USA Corp. to Host First Virtual Career Event Seeking RISC-V Talent to Grow Its North America Operation | Andes Technologies

Aug 25, 2022

Alibaba Cloud launches RISC-V developer platform for edge SoCs | Dan Robinson, The Register

Aug 25, 2022

Chip Pioneers to Battle it out in Modern RISC-V AI Chips | Agam Shah, HPC Wire

Aug 25, 2022

Costs Of Static HW Partitioning On RISC-V | Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Mauerer, Semiconductor Engineering

Aug 24, 2022

Pavilion Panel: Those Darn Bugs | Axiomise

Aug 24, 2022

Engineering Academy Tackles RISC-V in Next Educational Event Installment | William G. Wong, Machine Design

Aug 24, 2022

LeapFive launches NB2 RISC-V flagship SoC in China | Bogdan Solca, Notebook Check

Aug 24, 2022

Amid Chip Shortages, Companies Bet on RISC-V | Lianne Frith, All About Circuits

Aug 24, 2022

Versatile, Compact and High-Performance TySOM-M Embedded Development Board Based on PolarFire® SoC FPGA Device | Microchip Technologies

Aug 24, 2022

Alibaba Cloud Unveils Chip Development Platform to Support Developers with RISC-V based High-Performance SoCs | Alibaba Cloud

Aug 23, 2022

LeapFive NB2 is a New RISC-V Processor | Ian Evenden, Tom’s Hardware

Aug 23, 2022

StarFive Opens Crowdfunding for the VisionFive 2 RISC-V SBC, Starting at Just $46 | Gareth Halfacree, Hackster.io

Aug 23, 2022

1400 RISC-V cores for on-chip machine learning | Nick Flaherty, EE News Europe

Aug 22, 2022

StarFive VisionFive 2 quad-core RISC-V SBC launched for $46 and up (Crowdfunding) | Jean Luc Aufranc, CNX Software

Aug 22, 2022

Experimental Patches Allow Much Faster AArch64 & RISC-V Kexec Kernel Reboots | Michael Larabel, Phoronix

Aug 22, 2022

Ubuntu Announces Compatibility With Second RISC-V System | Ian Evenden, Tom’s Hardware

Aug 22, 2022

StarFive VisionFive 2 single-board PC with a quad-core RISC-V chip coming in November | Brad Linder, Liliputing

Aug 22, 2022

Canonical enables Ubuntu on StarFive’s VisionFive RISC-V boards | Ubuntu Blog, Canonical

Aug 21, 2022

T-Head DSA design in RISC-V | Chaojun Zhao, Alibaba Cloud

Aug 21, 2022

China’s RISC-V pioneer raises funds for IoT, automotive push | Peter Clarke, EE News

Aug 21, 2022

Ubuntu Now Supports The Allwinner D1 Powered Nezha RISC-V Board | Michael Larabel, Phoronix

Aug 20, 2022

LeapFive NB2 quad-core RISC-V processor comes with GPU, NPU, and DSP | Jean-Luc Aufranc, CNX Software

Aug 18, 2022

Implementing Cryptographic Algorithms For The RISC-V Instruction Set Architecture In Two Cases | Intel, North Arizona University and Google, Semiconductor Engineering

Aug 18, 2022

StarFive VisionFive V1 RISC-V SBC gets Ubuntu 22.04.1 Server image from Canonical | Jean-Luc Aufranc, CNX Software

Aug 18, 2022

RISC-V Processor IP Provider Nuclei Technology Secures New Funding | Pandaily

Aug 18, 2022

First RISC-V processor starts operation in orbit | Nick Flaherty, EE News Europe

Aug 18, 2022

Now you can run Ubuntu on a VisionFive single-board PC with a RISC-V processor | Brad Linder, Liliputing

Aug 18, 2022

StarFive VisionFive V1 RISC-V SBC gets Ubuntu 22.04.1 Server image from Canonical | Jean-Luc Aufranc, CNX Software

Aug 16, 2022

Crypto Quantique joins RISC-V International | Nick Flaherty, EE News Europe

Aug 16, 2022

Andes, Green Hills team for RISC-V automotive safety | Nick Flaherty, EE News Europe

Aug 16, 2022

Andes Technology and Green Hills Software Team Up to Deliver Advanced Automotive Safety Platform for RISC-V | Andes Technologies

Aug 16, 2022

Microchip to develop next generation 12 core RISC-V space processor for NASA | Nick Flaherty, EE News Europe

Aug 15, 2022

Latest Funding Drives Ventana’s First RISC-V Chiplets in Data Centers | Nitin Dahad, EE Times

Aug 15, 2022

2022 RISC-V Taipei Day to be held in September to explore RISC-V driven developments in EV, smart vehicles | DigiTimes Asia

Aug 15, 2022

Latest Funding Drives Ventana’s First RISC-V Chiplets in Data Centers | Nitin Dahad, EE Times

Aug 12, 2022

RISC-V Summit China 2022 Announces Agenda | Inside HPC

Aug 11, 2022

RISC-V Summit China 2022 Announces Agenda | RISC-V International

Aug 10, 2022

Case study: optimizing PPA with RISC-V custom extensions in TWS earbuds | John Minh, Andes Technologies

Aug 10, 2022

DAC – where RISC-V thrives and mixed signal design blends in | EW Staff, Electronics Weekly

Aug 9, 2022

Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library | Imperas Software

Aug 8, 2022

SiFive Is Leading The Way For Innovation On RISC-V | Karl Freund, Forbes

Aug 8, 2022

Chips and the Open-Source Secret | Isabella Borshoff, The Wire China

Aug 8, 2022

Defend Your Devices Against a Common and Insidious Hack With seL4 | Microchip Technologies

Aug 5, 2022

Nordic Semi sets up RISC-V design team | Nick Flaherty, EE News Europe

Aug 5, 2022

RISC-V verification ecosystem releases complete source file access | Imperas Software, Electropages

Aug 5, 2022

MangoPi MQ Pro with 64-bit RISC-V processor | Julian Horsey, Geeky Gadgets

Aug 4, 2022

HydraUSB3 RISC-V MCU board combines USB 3.0 with HSPI and SerDes high-speed interfaces | Jean-Luc Aufranc

Aug 4, 2022

Milandr MDR32F02FI is a RISC-V microcontroller for (Russian) electricity meters | Jean-Luc Aufranc, CNX Software

Aug 3, 2022

Low Power HW Accelerator For FP16 Matrix Multiplications For Tight Integration Within RISC-V Cores | Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti

Aug 2, 2022

First open-source SystemVerilog RISC-V processor functional coverage library | Nick Flaherty, EE News Europe

Aug 2, 2022

NSITEXE expands products lineup of RISC-V CPU supported functional safety | NSITEXE, Design and Reuse

Aug 1, 2022

PINE64 Formally Unveils the StarFive JH7110-Powered Star64 RISC-V Single-Board Computer | Gareth Halfacree, Hackster.io

Aug 1, 2022

Welcoming RISC-V International Board Members

Jul 29, 2022

RISC-V Global Summit Will Showcase Enormous Momentum for the Open Standard Hardware Architecture and Software Ecosystem | RISC-V International

Jul 28, 2022

Architectures for Matrix Extension in CPU | Jiang Zhao, Alibaba Cloud

Jul 26, 2022

Porting GNOME OS to Microchip’s PolarFire® SoC FPGA Icicle Kit for the First Time | Microchip

Jul 20, 2022

Andes Technology RISC-V Processors Reveal Outstanding Performance and Efficiency in MLPerf Tiny | Andes Technology

Jul 20, 2022

DAC 2022 – Is it too risky not to adopt RISC-V? | Brett Cline, Codasip

Jul 18, 2022

Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | Antmicro

Jul 18, 2022

Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies Inc

Jul 18, 2022

RISC-V Standardizes E-Trace and Binary Interface | William G. Wong, Electronic Design

Jul 15, 2022

Updated: Imagination’s first real-time embedded RISC-V CPU | Steve Bush, Electronics Weekly

Jul 14, 2022

Codasip opens RISC-V design centre in Greece | Nick Flaherty, EE News Europe

Jul 14, 2022

YD-CH32V307VCT6 RISC-V MCU board comes with Ethernet and plenty of I/Os | Jean-Luc Aufranc, CNX Software

Jul 13, 2022

RISC-V Guns for Raspberry Pi, Legacy Chips | Lucas Laursen, IEEE Spectrum

Jul 12, 2022

RISC-V Serves Up Open-Source Possibilities for the Future | Cabe Atwell, Electronic Design

Jul 12, 2022

Joint venture unveils world’s first RISC-V laptop | Robin Mitchell, Electropages

Jul 11, 2022

RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V International

Jul 11, 2022

Everything RISC-V at the Design Automation Conference! | RISC-V International

Jul 11, 2022

Imperas announces the latest updates to RVVI and welcomes the adoption by many leading RISC V processor developers | Imperas Software

Jul 11, 2022

Open Standard RISC-V Verification Interface (RVVI) for SOC testing | Nick Flaherty, EE News Europe

Jul 10, 2022

China pins hopes on local RISC-V start-ups to crack Western monopoly on CPU chips | Che Pan, South China Morning Post

Jul 9, 2022

Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba Cloud

Jul 8, 2022

ISA Extension For Low-Precision NN Training On RISC-V Cores | Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini, Semiconductor Engineering

Jul 8, 2022

Europe steps up as RISC-V ships 10bn cores | Nick Flaherty, EE News Europe

Jul 7, 2022

RISC-V Opens the Door on 48-bit Computing | Agam Shah, HPC Wire

Jul 7, 2022

Imperas and Breker partner for Risc-V system-level verification | Steve Bush, Electronics Weekly

Jul 7, 2022

First RISC-V-Based SoC FPGA Enters Mass Production | Microchip Technology, EE Time Asia

Jul 7, 2022

SiFive arrives in Cambridge to hire 100 for ascendant RISC-V computing | Mike Scialom, Cambridge Independent

Jul 7, 2022

Imperas Announces Partnership with Breker to Drive Rigorous Processor-to-System Level Verification for RISC-V | Imperas Software

Jul 7, 2022

seL4 userspace debugging with GDB extensions in Renode | Antmicro

Jul 7, 2022

PolarFire® SoC FPGA in Conclusive RCHD-PF System Module | Microchip

Jul 6, 2022

Imperas announce the latest RISC-V test suites are now available free with riscvOVPsimPlus | Imperas Software

Jul 5, 2022

Upcoming RISC-V laptop promises free silicon upgrades | Scharon Harding, Ars Technica

Jul 4, 2022

First RISC-V laptop arrives | Nick Farrell, Fudzilla

Jul 4, 2022

TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms | Semiconductor Engineering

Jul 3, 2022

Take note, Arm: The world’s first RISC-V laptop is now available for preorder | Joel Khalili, Tech Radar

Jul 1, 2022

First native RISC-V laptop readies for market | Nick Flaherty, EE News Europe

Jul 1, 2022

The first laptop with a RISC-V processor is coming | Brad Linder, Liliputing

Jul 1, 2022

One of the first RISC-V laptops may ship in September, has an NFT hook | Dylan Martin, The Register

Jul 1, 2022

DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep Computing

Jun 30, 2022

Espressif Unveils Its First Dual-Band Wi-Fi 6 and BLE RISC-V Part for the IoT: The ESP32-C5 | Gareth Halfacree, Hackster.io

Jun 30, 2022

Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies | Breker Verification Systems

Jun 30, 2022

RISC-V Takes Embedded World 2022 by Storm | Max Maxfield, Electronic Engineering Journal

Jun 30, 2022

German startup MachineWare announces a RISC-V simulator | Scientific Computing World

Jun 29, 2022

Esperanto is leading the RISC-V revolution for AI and enabling a new level of AI performance | Esperanto.ai

Jun 29, 2022

MachineWare RISC-V simulator for software developers | Brittany Hainzinger, App Developer Magazine

Jun 29, 2022

RISC-V International Adds Four ISA Chip Specification Approvals | Todd R Weiss, Futurum Research

Jun 29, 2022

Build Open Silicon with Google | Google Open Source Blog

Jun 29, 2022

Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP | Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. Carloni

Jun 29, 2022

SiFive opens Cambridge RISC-V design centre | Nick Flaherty, EE News Europe

Jun 29, 2022

Pine64 Teases RISC-V Based Raspberry Pi Alternative | Ian Evenden, Tom’s Hardware

Jun 29, 2022

New startup MachineWare enables ultra-fast RISC-V simulation | Electronic Engineering Journal

Jun 29, 2022

OpenHW Group announces RISC-V CORE-V MCU kit | Robin Mitchell, Electropages

Jun 29, 2022

Embedded World 2022 – the RISC-V genie is out of the bottle | Roddy Urquhart, Codasip

Jun 28, 2022

Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications | Tiera Oliver, Embedded Computing Design

Jun 28, 2022

SiFive chips into Cambridge to take on Arm in its own backyard | Tony Quested , Business Weekly

Jun 28, 2022

RISC-V: The Road Ahead | Stephano Cetola, RT-Thread IoT OS Global Tech Conference

Jun 28, 2022

Imagination launches IMG RTXM-2200 – its first real-time embedded RISC-V CPU | Imagination Technologies

Jun 28, 2022

Next Generation Data Center Architectures to be Driven by RISC-V and Open Standards | Balaji Baktha, Ventana Micro Systems

Jun 28, 2022

Open Source RISC-V: Serving a Side of Software with Chips | Agam Shah, The New Stack

Jun 27, 2022

SoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, Syntacore

Jun 27, 2022

Who Does Processor Validation? | Brian Bailey, Semiconductor Engineering

Jun 27, 2022

MNT Pocket Reform is 7 inch mini laptop with a modular, open hardware design | Brad Linder, Liliputing

Jun 27, 2022

The Future of RISC-V | Patrick Little, SiFive

Jun 27, 2022

Elektor Engineering Insights #3 – RISC-V | Stuart Cording, Elektor TV

Jun 27, 2022

Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | Antmicro

Jun 26, 2022

Ventana Micro CEO explains next gen data centers are driven by RISC-V and open standards | Ventana Micro Systems

Jun 26, 2022

Ferrous Systems and Espressif’s Rust Training on ESP32 | Espressif

Jun 26, 2022

Imagination unveils IMG RTXM-2200 32-bit RISC-V real-time “Catapult” CPU | Jean-Luc Aufranc, CNX Software

Jun 26, 2022

Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board | Michael Larabel, Phoronix

Jun 26, 2022

StarFive Survey Announced | StarFive

Jun 25, 2022

RISC-V Ratifies New Specifications, Including a “Cheap” Multiply-Only Operation for MCUs and FPGAs | Gareth Halfacree, Hackster.io

Jun 25, 2022

Lichee RV-86 RISC-V Linux 4-inch panel targets home automation, HMI applications | Jean-Luc Aufranc, CNX Software

Jun 24, 2022

CAP-VMs: Capability-Based Isolation and Sharing for Microservices | Vasily A. Sartakov, Lluís Vilanova, David Eyers, Takahiro Shinagawa, Peter Pietzuch

Jun 24, 2022

news Introducing ESP32-C5: Espressif’s first Dual-Band Wi-Fi 6 MCU | Espressif

Jun 24, 2022

FREE Trial of Beetle ESP32 – C3 | DFRobot

Jun 24, 2022

RISC-V Shines at Embedded World With New Specs and Processors | Jeff Child, All About Circuits

Jun 24, 2022

A RISC-V laptop or mini PC with Rockchip RK3588-class performance may be coming soon | Jean-Luc Aufranc, CNX Software

Jun 23, 2022

SiFive X280 RISC-V Processor Gets Scalability, Trust Updates | Todd R. Weiss, Futurum Research

Jun 23, 2022

Espressif Launches ESP Privilege Separation, Giving the ESP32-C3 a Secure Split Personality | Gareth Halfcree, Hackster.io

Jun 23, 2022

Digi-Key at Embedded World with OpenHardware Group | Digi-Key, Electronic Specifier

Jun 23, 2022

De-RISC: A complete RISC-V based space-grade platform | Wessman, Nils-Johan Malatesta, Fabio Ribes, Stefano Andersson, Jan García Vilanova, Antonio Masmano Tello, Miguel Nicolau Gallego, Vicente Gómez Molinero, Paco Le Rhun, Jimmy Alcaide Portet, Sergi Cabo Pitarch, Guillem Bas Jalón, Francisco Benedicte Illescas, PedroMés, Mazzocchetti, Fabio Abella Ferrer, Jaume

Jun 22, 2022

Codasip adds Veridify Secure Boot to RISC-V Processors | Veridify Security

Jun 22, 2022

Full RISC-V and CMake support added to NECTO Studio 2.0 IDE from MIKROE | Neil Tyler, New Electronics

Jun 22, 2022

Freier Befehlssatz als Basis für GPU | Johannes Hiltscher, Golem

Jun 22, 2022

Elektor Magazine at Embedded World 2022 | Elektor Magazine

Jun 22, 2022

XtremeEDA to enable IoT security deployment with Crypto Quantique’s solution using Codasip’s RISC-V processor | Design and Reuse

Jun 22, 2022

RISC-V International emits more open CPU specs | Liam Proven, The Register

Jun 22, 2022

ESP32-C5 RISC-V IoT MCU supports dual-band WiFi 6, Bluetooth 5.0 LE | Jean-Luc Aufranc, CNX Software

Jun 21, 2022

RISC-V’s CTO on the Art of Herding Cats | Junko Yoshida, The Ojo – Yoshida Report

Jun 21, 2022

Sipeed Lichee RV Dock Pro RISC-V SBC adds MIPI/RGB LCD connector, dual MIC, and BL702 JTAG+UART debugger | Jean-Luc Aufranc, CNX Software

Jun 21, 2022

SiFive Enhances Popular X280 Processor IP to Meet Accelerated Demand for Vector Processing | SiFive

Jun 21, 2022

Codasip Studio Mac extends potential to design for differentiation with RISC-V | Codasip

Jun 21, 2022

Think Silicon Shows Off First RISC-V 3D GPU | Michael Larabel, Phoronix

Jun 21, 2022

OpenHW Group Announces RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software | AIT News Desk, AIthority

Jun 21, 2022

Embedded World: RISC-V ratifies Efficient Trace and Supervisor Binary Interface | Steve Bush, Electronics Weekly

Jun 21, 2022

European RISC-V chip for IoT development kit | Nick Flaherty , EENews Europe

Jun 21, 2022

Ashling and Embecosm partnership continues to provide “best-in-class” embedded tools services and solutions to the RISC-V market | BusinessWire

Jun 21, 2022

CV32E40P Core From OpenHW Group Sets the RISC-V Quality Standard For Open-Source Hardware IP | Imperas Software Ltd.

Jun 20, 2022

Democratizing Chiplet-Based Processor Design | Ventana Micro Systems

Jun 20, 2022

RISC-V Vector Processing is Taking Off | SiFive

Jun 20, 2022

GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves Technologies

Jun 20, 2022

Overtake the Competition in Automotive Design with RISC-V Innovations | Codasip

Jun 20, 2022

RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V International

Jun 20, 2022

Build an IoT App with Zig and LoRaWAN | Lee Lup Yuen, Mr. Tech Blog

Jun 20, 2022

OpenHW Group announces RISC-V-based CORE-V MCU development kit | Nitin Dahad, Embedded.com

Jun 20, 2022

Hardware Dynamic IFT Mechanism That Scales to Complex Open-Source RISC-V Processors | Semiconductor Engineering

Jun 20, 2022

Think Silicon NEOX RISC-V GPU offers 3D graphics or AI acceleration | Jean-Luc Aufranc, CNX Software

Jun 20, 2022

Siemens streamlines, secures embedded RISC-V development with latest Nucleus ReadyStart solution | Siemens

Jun 19, 2022

QWERTY’s ICE-V Wireless Packs RISC-V, FPGA, Bluetooth, and Wi-Fi Into a Single Handy Board | Gareth Halfacree, Hackster.io

Jun 18, 2022

Linux on RISC-V | Drew Fustini, BayLibre

Jun 17, 2022

Renode 1.13 for improved machine learning and pre-silicon development | Antmicro

Jun 17, 2022

HiPEAC Info Issue 66 | HiPEAC

Jun 17, 2022

Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies

Jun 17, 2022

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on a 7nm Chip | Stanford Online

Jun 17, 2022

Experimental evaluation of neutron-induced errors on a multicore RISC-V platform | Fernando Fernandes dos Santos (TARAN), Angeliki Kritikakou (TARAN), Olivier Sentieys (TARAN)

Jun 16, 2022

Thermal (IR) Imaging Pipeline (ISP) Core on PolarFire® SoC FPGA SoM | Microchip

Jun 16, 2022

First RISC-V 3D GPUs Will Be Demoed Next Week | Mark Tyson, Tom’s Hardware

Jun 15, 2022

RISC-V: How Can I Get Involved ? | New York City RISC-V Group

Jun 15, 2022

Researchers Benchmark Experimental RISC-V Supercomputer | Tom’s Hardware

Jun 15, 2022

An Introduction to RISC-V—Understanding RISC’s Open ISA | Eduardo Corpeño, All About Circuits

Jun 15, 2022

Think Silicon to Unveil Industry’s First RISC-V 3D GPU at Embedded World 2022 | Think Silicon, Yahoo! Finance

Jun 14, 2022

Codasip appoints Mike Eftimakis as VP of Strategy and Ecosystem | Codasip

Jun 13, 2022

XuanTie C906 Tops MLPerf Tiny v0.7 Benchmark | MengChang, Alibaba Cloud

Jun 13, 2022

L’ESP32-C5 est la première puce-système RISC-V qui prend en charge le Wi-Fi 6 bibande et le Bluetooth LE | Pierrick Arlot, L’embarque.

Jun 11, 2022

An Introduction to Digi-Key’s RISC-V Reference Guide | Rich Miron, Digi-Key

Jun 11, 2022

Researchers Benchmark Experimental RISC-V Supercomputer | Anton Shilov, Tom’s Hardware

Jun 10, 2022

Microchip Pushes First RISC-V-based SoC FPGA to Mass Production | Jake Hertz, All About Circuits

Jun 10, 2022

Working with High-Level-Language Debuggers in RISC-V-Based Apps | Rafael Taubinger, Electronic Design

Jun 10, 2022

Lauterbach supports Fraunhofer RISC-V functional safety core | Nick Flaherty, EENews Europe

Jun 10, 2022

Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board | Michael Larabel, Phoronix

Jun 9, 2022

Strong Showing for First Experimental RISC-V Supercomputer | Nicole Hemsoth, The Next Platform

Jun 8, 2022

First RISC-V-Based System-on-Chip (SoC) FPGA Enters Mass Production | EE Journal

Jun 8, 2022

Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPS

Jun 6, 2022

$400m RISC-V design centre for Barcelona | Nick Flaherty, EE News Europe

Jun 6, 2022

RISC-V Researchers publish new RISC-V SoC | Robin Mitchell, Electropages

Jun 4, 2022

Linux 5.19 Adding Support For The PolarBerry RISC-V FPGA Board | Michael Larabel, Phoronix

Jun 3, 2022

SiFive RISC-V Sees Some Performance Improvements On Ubuntu 22.04 | Michael Larabel, Phoronix

Jun 2, 2022

RISC-V Summit China 2022 Call for Talks is Now Open

Jun 2, 2022

CAES and Ashling Announce Ashling’s RiscFree™ C/C++ Toolchain for CAES’ NOEL-V® Processors | Ashling, Business Wire

Jun 2, 2022

Intel investing in RISC-V Architecture for its Zettascale Supercomputers Chips | Nivedita Bangari, Technosports

Jun 2, 2022

First samples for RISC-V and ARM embedded modules | Nick Flaherty, EE News Europe

May 25, 2022

Yeah, RISC-V Is Actually a Good Design | Erik Engheim, ITNEXT

May 24, 2022

NSITEXE Selects ImperasDV for Automotive Quality RISC-V Processor Functional Design Verification | Imperas Software

May 24, 2022

Ashling to provide RiscFree™ RISC-V Toolchain support for Intel FPGAs | Ashling, Business Wire

May 23, 2022

Simplifying the Vehicle to Anything (V2X) Journey: Porting of Jamaica VM on PolarFire® SoC Icicle Kit | Leah Iris, Microchip

May 10, 2022

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability | MIPS

May 3, 2022

E4 Computer Engineering joins RISC-V International | E4 Computer Engineering

Apr 28, 2022

RISC-V Open Era of Computing – A Conversation with Calista Redmond and Mr. Sivakumar P R , Founder and CEO of Maven Silicon | Maven Silicon

Apr 25, 2022

Join us in the classroom! Put RISC-V into your Computer Architecture course using RVfpga! | Robert C.W. Owen, Imagination Technologies

Apr 20, 2022

Alibaba Cloud Tops MLPerf Tiny v0.7 Benchmark | Alibaba Cloud

Apr 19, 2022

Xuantie IOMMU from T-Head for RISC-V | Chong Ren, Alibaba Cloud

Apr 5, 2022

Mi-V Ecosystem Partner Solutions | Leah Iris, Microchip

Apr 4, 2022

XuanTie VirtualZone: RISC-V-based Security Extensions | Xuan Jian, Alibaba Cloud

Mar 29, 2022

HPCwire‘s People to Watch Program | HPCWire

Mar 28, 2022

MIPS Chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA Compatible IP Cores | Ashling and MIPS, BusinessWire

Mar 28, 2022

RISC-V is coming to the internet of things | Stacey Higginbotham, Stacey on IoT

Mar 28, 2022

SEGGER releases new Embedded Studio for RISC-V with hard real-time C++ support | SEGGER, Electronic Engineering Journal

Mar 27, 2022

RISC-V Gets Sv57-Based Virtual Memory, Other Improvements For Linux 5.18 | Michael Larabel, Phoronix

Mar 26, 2022

Now the V in RISC-V Stands for VROOM! | Matthew Carlson, Hackaday

Mar 25, 2022

Dongshan Nezha STU devkit features Allwinner D1 RISC-V SoM/SBC | Jean-Luc Aufranc, CNX Software

Mar 15, 2022

RISC-V RV32I JALR Instruction | Maven Silicon

Mar 14, 2022

Adafruit’s QT Py ESP32-C3, Its First RISC-V Dev Board, Begins Rolling Off the Production Line | Gareth Halfacree, Hackster.io

Mar 14, 2022

CEO Interview: Frankwell Lin, Chairman and CEO of Andes Technology | Daniel Nenni, SemiWiki

Mar 14, 2022

RISC-V AI Chips Are Joining GPU Race for AI Processing | Paul Mah, CDO Trends

Mar 14, 2022

Alphawave IP Announces Definitive Agreement to Acquire Entire OpenFive Business Unit from SiFive for US$210m in cash | Design and Reuse

Mar 14, 2022

IAR extends powerful RISC-V solutions with 64-bit support | IAR Systems

Mar 14, 2022

Intel Foundry Services Going Big On RISC-V ‘Brawny Cores’ With Ventana Micro Systems Compute Tiles | Patrick Moorhead, Forbes

Mar 14, 2022

Exploring emerging trends and topics in RISC-V architecture | Mouser Electronics, ElectroPages

Mar 13, 2022

Imperas unifies new RISC-V verification ecosystem with RVVI | Imperas

Mar 13, 2022

Mouser Electronics Launches 2022 Empowering Innovation Together Program with New Podcast on RISC-V | Raymond Yin, Business Wire

Mar 13, 2022

SEGGER collaboration makes Embedded Studio for RISC-V available at no cost | Neil Tyler, New Electronics

Mar 11, 2022

Codasip University Program spurs innovation and boosts curriculums | Codasip

Mar 11, 2022

SEGGER collaborates with HPMicro making Embedded Studio for RISC-V available at no cost | SEGGER

Mar 8, 2022

32bit RISC-V cores are customisable for TensorFlowLite AI | Nick Flaherty, EE News Europe

Mar 7, 2022

Renesas expands options with Andes-based RISC-V MPU | Nitin Dahad, Embedded.com

Mar 7, 2022

MPU leverages 64-bit RISC-V core | Susan Nordyk, EDN

Mar 4, 2022

$39 MangoPi-Nezha MQ RISC-V developer board runs OpenWrt, Debian, or RT-Smart RTOS (Crowdfunding) | Jean-Luc Aufranc, CNX Software

Mar 3, 2022

Open standard for RISC-V verification is announced at DVCon | Caroline Hayes, Electronics Weekly

Mar 1, 2022

Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | Imperas

Mar 1, 2022

M5Stamp C3U IoT module relies on ESP32-C3’s own USB interface for firmware programming | Jean-Luc Aufranc, CNX Software

Feb 28, 2022

Imperas announces RISC-V PMP Architectural Validation test suite | Neil Tyler, New Electronics

Feb 28, 2022

Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | Electronic Engineering Journal

Feb 26, 2022

Performance Evaluation of Various RISC Processor Systems: A Case Study on ARM, MIPS and RISC-V | Chinese Academy of Sciences

Feb 25, 2022

RISC-V design challenge – Get a free board, RISC-V chips, and cash prizes | Jean-Luc Aufranc, CNX Software

Feb 25, 2022

Linux 5.18 To Bring RISC-V sv57 Support For 5-Level Page Tables | Michael Larabel, Phoronix

Feb 17, 2022

FOSSi Explosion 2021 | Olof Kindgren, FOSSi Foundation and Qamcom

Feb 7, 2022

Esperanto Technologies Partners with Intel to Advance Massively Parallel RISC-V-based AI Acceleration Solutions | Esperanto Technologies

Feb 7, 2022

SiFive Partners with Intel to Spark Innovation in High-Performance RISC-V Platforms | SiFive

Feb 7, 2022

Andes Technology Corp. and Intel Foundry Services Bring RISC-V Solutions to Build an Open Ecosystem | Andes Technology Corporation

Feb 7, 2022

Ventana Micro Systems Inc. Announces Strategic Partnership With Intel For Broader Commercialization Of Its High-Performance RISC-V Cores And Chiplets | Ventana Micro Systems

Feb 7, 2022

Intel Creates $1B Innovation Fund To Grow RISC-V Market (And Attract New Foundry Customers) | Karl Freund, Forbes

Feb 7, 2022

Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing

Feb 6, 2022

Looking Back On 2021: Strong Growth Momentum Of RISC-V Market | Andes Technology

Feb 4, 2022

RISC-V RV32I J-Type | Maven Silicon

Feb 4, 2022

An Efficient Lightweight Cryptographic Instructions Set Extension for IoT Device Security | Wajih El Hadj Youssef, Ali Abdelli, Fethi Dridi, Rim Brahim, and Mohsen Machhout, Faculty of Sciences of Monastir, Electronics and Micro-Electronic Laboratory (LEME)

Feb 4, 2022

India goes RISC-V with VEGA processors | Jean-Luc Aufranc, CNX Software

Feb 3, 2022

Enhancing supply chain security for embedded systems: Renode Dashboard for Zephyr RTOS adds new SBOM capabilities by default | Michael Gielda (Antmicro) and Kate Stewart (Linux Foundation), Linux.com

Feb 3, 2022

Rust Cross-Compilation | Daniel Mangum, RISC-V BYTES

Feb 3, 2022

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises? | Joseph Hupcey III, Semiconductor Engineering

Feb 3, 2022

RISC-V CPU Design Courses | Redwood EDA, LLC

Feb 2, 2022

Intel May Enable Discrete GPU Driver Development for Arm, RISC-V | Anton Shilov, Tom’s Hardware

Feb 2, 2022

Gateway Implementations with RISC-V | Alex Pluemer, Mouser Electronics

Feb 2, 2022

Bringing chips back from the dead : MPW-1 Show-off | Sylvain Munaut

Feb 2, 2022

Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research Corporation

Feb 1, 2022

Helping to lead the RISC-V revolution | Solid Sands, Electropages

Feb 1, 2022

HIPEAC Info Magazine, January 2022 | HIPEAC

Jan 31, 2022

Introduction to FPGA Part 12 – RISC-V Custom Peripheral | Shawn Hymel, Digi-Key Electronics

Jan 31, 2022

Open source keystroke injector implementation on the Fomu FPGA board | Antmicro

Jan 31, 2022

Open source FPGA platform for Rowhammer security testing in the data center | Antmicro

Jan 31, 2022

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode | Gianmarco Ottavi∗ , Angelo Garofalo∗ , Giuseppe Tagliavini† , Francesco Conti∗ , Alfio Di Mauro‡ , Luca Benini∗‡, and Davide Rossi∗ ∗Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Italy †Department of Computer Science and Engineering (DISI), University of Bologna, Italy ‡ IIS Integrated Systems Laboratory, ETH Zurich, Switzerland

Jan 28, 2022

WCH CH32V307 RISC-V development board features 8 UART ports controlled over Ethernet | Jean-Luc Aufranc, CNX Software

Jan 28, 2022

SmartDV and NSITEXE Sign Agreement to Deploy NSITEXE’s RISC-V 32bit CPU Core throughout North America, China, India, Taiwan | SmartDV

Jan 27, 2022

Andes RISC-V SoC shipments top 3 billion units in 2021 | Julian Ho, DigiTimes

Jan 27, 2022

Imagination GPU cleared for RISC-V CPU compatibility, licensed to chip designers | Agam Shah, The Register

Jan 27, 2022

Alibaba Cloud Opens Up IoT Technology Development Platform | Wang Cindy, Alibaba Cloud

Jan 26, 2022

RISC-V security IP for chiplet die-to-die communication | Nick Flaherty, EE News Europe

Jan 26, 2022

RISC-V SoCs: Powering Embedded Computing | Efinix

Jan 25, 2022

Full-Stack Open-Source – T-Head Promotes the Maturity of RISC-V Technology | Alibaba Cloud, Apsara News

Jan 25, 2022

Introduction to FPGA Part 11 – RISC-V Softcore Processor | Digi-Key Electronics

Jan 25, 2022

Introducing an Open Source Microkernel OS for AIoT | Blues Lin, RT-Thread

Jan 25, 2022

Take Control of Your RISC-V Codebase | Rafael Taubinger, Electronic Design

Jan 25, 2022

Redpine Founder Launches AI Processor Startup | Sally Ward-Foxton, EE Times

Jan 24, 2022

Ceremorphic addresses AI, HPC, and the metaverse with QS 1 chip, lands $50M | Arne Verheyde, Venture Beat

Jan 23, 2022

RISC-V CH32V307 QuickStart E01 | WCH

Jan 22, 2022

$10 RISC-V Development Board is an Arduino Alternative | Ian Evenden, Tom’s Hardware

Jan 21, 2022

GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors | Nazareno Bruschi∗ , Germain Haugou†‡, Giuseppe Tagliavini∗ , Francesco Conti∗ , Luca Benini∗†, and Davide Rossi∗ (∗University of Bologna, †ETH, ‡GreenWaves-Technologies)

Jan 21, 2022

SiFive Preps Next-Gen HiFive Unmatched RISC-V Boards | Anton Shilov, Tom’s Hardware

Jan 21, 2022

Google Research Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning | Gareth Halfacree, AB Open

Jan 20, 2022

NSITEXE and Green Hills Software Partner on RISC-V Solutions | Design & Reuse

Jan 18, 2022

ASIC roundup of open source RISC-V CPU cores | Oguz Meteer, BitlogIT

Jan 18, 2022

RISC-V SoC + AI – Run a demo of the ncnn inference framework using Allwinner’s D1 “Nezha” Development Board | Verimake

Jan 18, 2022

The State of the RISC-V Union, part II | Paul McLellan, Cadence Design Systems

Jan 18, 2022

First impression on Nezha RISC-V SBC | 3mdeb

Jan 17, 2022

SEGGER J-Link – Performance analysis on RISC-V | SEGGER

Jan 17, 2022

At CES2022 Bouffalo Shows its Matter Turnkey Solution | Bouffalo Lab, EE Times

Jan 17, 2022

Deep Vision Adopts SiFive RISC-V to Add OpenCV-Enabled AI Support | SiFive

Jan 17, 2022

Picoclick C3T Is the World’s Smallest IoT Button and It Has a RISC-V Processor | James Lewis, Hackster.io

Jan 17, 2022

Baikal Electronics allies with IP-cores domestic developer | Design & Reuse

Jan 17, 2022

Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals | Jean-Luc Aufranc, CNX Software

Jan 16, 2022

RISC-V MCU CH32V307 Tutorial — Voice Control DEMO | Verimake

Jan 14, 2022

CFU Playground: Customize Your ML Processor for Your Specific TinyML Model | Tim Callahan, TinyML Talks

Jan 14, 2022

The Rapid Rise of RISC-V | Jack Kang, SiFive

Jan 14, 2022

ZAYA Secure μContainers for RISC-V Microcontrollers | Zaya

Jan 14, 2022

RISC-V SoCs: Powering Embedded Computing | Efinix, Inc.

Jan 13, 2022

“Revolutionizing Computer Architecture” – A fireside chat Dr. David Patterson, Vice Chair of RISC-V | Shaastra IITM

Jan 13, 2022

Is Programmable Overhead Worth The Cost? | Brian Bailey, Semiconductor Engineering

Jan 13, 2022

Alibaba Cloud opens up IoT technology development platform | Shannon Williams, ChannelLife Australia

Jan 13, 2022

A Minimal RISC-V | Brian Bailey, Semiconductor Engineering

Jan 13, 2022

Embedded Computing Design’s 2022 Tech Industry Predictions | Rich Nass, Embedded Computing Design

Jan 13, 2022

How to use the RISC-V development board to achieve automatic car patrol line driving? | RRoy, DFRobot

Jan 13, 2022

Picoclick C3T – the smallest ESP32-C3 based IOT button – assembly & tests | maker.moekoe

Jan 13, 2022

Rust on Apache Nuttx OS | Lup Yuen Lee, Mr. Tech Blog

Jan 13, 2022

MangoPi Shows Off a Raspberry Pi Zero-Inspired MQ Pro RISC-V Single-Board Computer — and Router | Gareth Halfacree, Hackster.io

Jan 13, 2022

Sub-mW Keyword Spotting on an MCU: Analog Binary Feature Extraction and Binary Neural Networks | Gianmarco Cerutti, Lukas Cavigelli, Renzo Andri, Michele Magno, Elisabetta Farella, Luca Benini

Jan 13, 2022

RISC-V不是你想得那樣 | RISC-V商業模式分析

Jan 12, 2022

2021 Year in Review | Roberto Frazzoli, EDA Cafe

Jan 12, 2022

My RISC-V development environment for programming and reverse engineering purposes | Rog3rSm1th

Jan 12, 2022

RISC-V RV32I S-Type | Maven Silicon

Jan 12, 2022

Finally an unmatched open frame case for the SiFive RISCV64 Linux board! | More Bits inside by René Rebe

Jan 12, 2022

Successful Conclusion of European Processor Initiative Phase One | European Processor Initiative

Jan 12, 2022

The Research of RISC-V for Embedded MCUs | RT-Thread

Jan 12, 2022

Linux 5.17 Adds Support For “The First Usable, Low-Cost RISC-V Platform” | Michael Larabel, Phoronix

Jan 11, 2022

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing | Andreas Kurth, Björn Forsberg and Luca Benini

Jan 8, 2022

Gentoo Linux Packages Up AMD ROCm, Makes Progress On RISC-V, LTO+PGO Python | Michael Larabel, Phoronix

Jan 8, 2022

The Chip Shortage, Giant Chips, and the Future of Moore’s Law | Samuel K. Moore, IEEE Spectrum

Jan 8, 2022

CH32V307 Chitu Development Board Tutorial: Use CMake to Develop | Yu Fan, VeriMake.io

Jan 8, 2022

MiG-V – Made in Germany RISC-V | HENSOLDT

Jan 7, 2022

Forces For Change And Competitive Intensity In Semiconductors | Michael Gurau, Forbes

Jan 7, 2022

21st Century Cryptography – Asynchronous ASIC | Jason Graalum, Galois

Jan 7, 2022

Board with 25 RGB LEDs is offered with ESP32-C3 or ESP32-Pico-D4 | Jean-Luc Aufranc, CNX Software

Jan 6, 2022

New Part Day: The RISC-V Lichee-RV Module and Dock | Dave Rowntree, Hackaday

Jan 6, 2022

CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs | Shvetank Prakash∗, Tim Callahan† Joseph Bushagour§, Colby Banbury∗, Alan V. Green†, Pete Warden†, Tim Ansell†, Vijay Janapa Reddi∗, †Google §Purdue University ∗Harvard University

Jan 6, 2022

SiFive announced new, high performance RISCV cores as AMD is looking for RISCV architect? | René Rebe, Bits inside by René Rebe

Jan 6, 2022

When You Reach The Summit, Keep Climbing | Andy Frame, SiFive

Jan 6, 2022

Using Imagination Around Arm & RISC-V | Embedded Computing Design Staff, Embedded Computing Design

Jan 6, 2022

RISC-V CTO: We won’t dictate chip design like Arm and x86 | Agam Shah, The Register

Jan 6, 2022

Mobileye Announces EyeQ6 And EyeQ Ultra Chips For Assisted And Automated Driving | Sam Abuelsamid, Forbes

Jan 6, 2022

Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions | Philippos Papaphilippou, Kelly Paul H. J., and Wayne Luk

Jan 5, 2022

Podcast EP54: Ventana Micro, RISC-V, HPC and Chiplets | Daniel Nenni, Semiwiki

Jan 5, 2022

Israeli Tech Industry to Get New Processor for Free, Courtesy of the State | Sagi Cohen, Haaretz

Jan 5, 2022

SATA Design Implementation on FPGAs with Open Source Tools | CHIPS Alliance

Jan 5, 2022

Inside RISC-V: Analysis and Exploitation | Don A. Bailey via Ringzer0

Jan 5, 2022

A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks | Angelo Garofalo∗, Gianmarco Ottavi∗, Francesco Conti∗, Geethan Karunaratne†‡, Irem Boybat†, Luca Benini‡∗, Davide Rossi∗, ∗University of Bologna, Bologna, Italy, †IBM Research Europe, Zurich, Switzerland, ‡ETH Zurich, Zurich, Switzerland

Jan 5, 2022

Intel Mobileye EyeQ Ultra RISC-V processor targets Level 4 autonomous driving | Jean-Luc Aufranc, CNX Software

Jan 4, 2022

This $5 dock turns the $17 Sipeed Lichee RV into a fully functional RISC-V computer | Brad Linder, Liliputing

Jan 4, 2022

CEO Interview: Igor Spinella, Eggtronic | Nick Flaherty, EE News Europe

Jan 4, 2022

64-bit RISC-V support added to new software release | SEGGER, Electropages

Jan 4, 2022

Sharing files between host and simulated platform in Renode with Virtio and other means | Antmicro

Jan 4, 2022

CH583 RISC-V microcontroller supports Bluetooth 5.3 LE | Jean-Luc Aufranc, CNX Software

Jan 4, 2022

Sipeed Lichee RV RISC-V module gets $5+ carrier board with HDMI and USB ports, optional WiFi | Jean-Luc Aufranc, CNX Software

Jan 4, 2022

Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMS

Jan 3, 2022

LoRaWAN on Apache NuttX OS | Lup Yuen Lee, Mr. Tech Blog

Jan 3, 2022

RISC-V Reaches Adolescence | Brian Santo, EE Times

Dec 27, 2021

P650 Pumps Up Performance by 50% | SiFive

Dec 17, 2021

RISC-V Summit 2021 | Codasip

Dec 15, 2021

Ventana reveals RISC-V CPU compute chiplet for data center | Nitin Dahad, Embedded.com

Dec 13, 2021

IAR Systems appoints Richard Lind as CEO | IAR Systems

Dec 13, 2021

RISC-V wants to be the third major chip architecture. CEO Calista Redmond has a lot of work to do | Max A. Cherney, Protocol

Dec 13, 2021

Finnish consortium tapes out multicore RISC-V edge AI IoT chip | Nick Flaherty, EE News Europe

Dec 11, 2021

HiSilicon Hi3731V110 32-bit RISC-V processor is made for Full HD televisions | Jean-Luc Aufranc, CNX Software

Dec 10, 2021

The 2021 RISC-V Summit Charts the Wildfire Expansion of Open-source Hardware | Tyler Charboneau, All About Circuits

Dec 10, 2021

StarFive Dubhe 64-bit RISC-V core to be found in 12nm, 2 GHz processors | Jean-Luc Aufranc, CNX Software

Dec 9, 2021

Chatter around GPUs for RISC-V is growing | Agam Shah, The Register

Dec 9, 2021

RISC-V vector instructions support in Renode | Antmicro

Dec 9, 2021

StarFive VisionFive single board computer officially for sale, accelerating RISC-V ecosystem development | Sponsored, CNX Software

Dec 9, 2021

Huawei HiSilicon Hi3731V110 is a new FHD TV chip based on RISC-V architecture | Sudarshan, GizmoChina

Dec 9, 2021

SiFive claims ‘fastest licensable RISC-V processor IP’ for its 11+SPECInt2006/GHz core | Steve Bush, Electronics Weekly

Dec 9, 2021

RISC-V Summit 2021 – High Performance Processors, Other Interesting Talks | Michael Larabel, Phoronix

Dec 9, 2021

E4 Announces the RISC-V-Based Monte Cimone Cluster | HPC Wire

Dec 8, 2021

SiFive Demonstrates RISC-V Rack Mount HPC Cluster | Anton Shilov, Tom’s Hardware

Dec 8, 2021

Two 64-bit RISC-V cores debut: StarFive Dubhe and CAS Nanhu | Eric Brown, LinuxGizmos

Dec 7, 2021

SEGGER adds 64-bit RISC-V support to Embedded Studio | SEGGER

Dec 6, 2021

IAR Systems and Codasip collaborate on low-power RISC-V-based applications | Neil Tyler, New Electronics

Dec 6, 2021

RISC-V Celebrates Incredible Year of Growth and Progress, Ratifying Multiple Technical Specifications, Launching New Education Programs, and Accelerating Broad Industry Adoption

Dec 6, 2021

Next generation music AI engine available for RISC-V

Dec 6, 2021

Ventana Micro Systems Inc. Joins RISC-V International’s Board of Directors

Dec 2, 2021

SiFive’s new chip could lead to revamped phone brains in 2023 | Stephen Shankland, CNET

Dec 2, 2021

HPMicro Semiconductor Announces the Release of the HPM6000 Series of Microcontrollers with AndesCore™ Dual D45 Cores | Andes Technology

Dec 2, 2021

SiFive Raises RISC-V performance bar with New Best-in-Class SiFive Performance P650 Processor | SiFive

Dec 2, 2021

RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs

Dec 1, 2021

Video: Linux made easy on RISC-V with Ubuntu | Ubuntu

Dec 1, 2021

Picocom samples its RISC-V OpenRAN chip | Nick Flaherty, EE News Europe

Dec 1, 2021

RISC-V’s open chip processors expected to double in 2022, and double again in 2023 | Hope Reese, TechRepublic

Dec 1, 2021

ルネサスに続きIntelもRISC-Vコア採用、Appleも追随か | 小島郁太郎日経クロステック／日経エレクトロニクス

Nov 30, 2021

The VisionFive V1 is a RISC-V alternative to Raspberry Pi and is coming soon | Sanjiv Sathiah, Notebook Check

Nov 30, 2021

Open-Source FPGA-Based RISC-V GPGPU That Supports OpenCL 1.2 | Michael Larabel, Phoronix

Nov 30, 2021

Learn the Latest on RISC-V and Vector Processing at All Five Andes Technology’s Presentations at the 2021 RISC-V Summit | Andes Technologies

Nov 30, 2021

IAR Systems and Codasip collaborate to enable low-power RISC-V-based applications | IAR Systems

Nov 30, 2021

Future Corporation Partners with AB Open for Unique RISC-V PC Project | Gareth Halfacree, AB Open

Nov 30, 2021

The Democratization of Chip Design | Mike Wishart and Lucio Lanza, EE Times

Nov 30, 2021

HLK-W801 board features Alibaba Xuantie XT804 based MCU with WiFi 4, Bluetooth LE 4.2 | Jean-Luc Aufranc, CNX Software

Nov 30, 2021

MIPS selects Imperas Reference Models for RISC-V Processor Verification | Imperas

Nov 29, 2021

Embedded vision kit employs SoC FPGA | Susan Nordyk, EDN

Nov 27, 2021

Implementing Bluetooth® BIS and CIS LE Audio | Telink Staff

Nov 27, 2021

RISC-V is Inevitable | Jack Kang, SiFive

Nov 26, 2021

Accelerating the Future of RISC-V | Rohit Kumar, SiFive

Nov 26, 2021

Meet ESP-C3-M1 and ESP-C3-M1-I ultra small ESP32-C3 mini modules | CNX Software, Sponsored

Nov 26, 2021

Video: RISC-V Duisburg Group – Making an authentication token IC based on the Opentitan Project

Nov 25, 2021

In Hardware We Trust? From TPM to Enclave Computing on RISC-V | Emmanuel Stapf, Patrick Jauernig, Ferdinand Brasser, and Ahmad-Reza Sadeghi

Nov 24, 2021

Samsung-Esperanto Concept AI-SSD Prototype | David Schor, WikiChip Fuse

Nov 24, 2021

Canonical at RISC-V Summit 2021 | Canonical

Nov 24, 2021

Embedded edge vision development kit for RISC-V FPGA | Nick Flaherty, EE News Europe

Nov 23, 2021

Imperas Announces Release of Simulator and Reference Models That Support Latest RISC-V Specifications | Imperas Software

Nov 22, 2021

Codasip Adopts Imperas for RISC-V Processor Verification Outlines vision for best-in-class RISC-V quality | Codasip

Nov 20, 2021

Branch Target Cache [BTC] (part 3) Managing a speculative subroutine call stack

Nov 18, 2021

See Western Digital’s SweRV Core family at the 2021 RISC-V Summit

Nov 15, 2021

Open Hardware: Skyrocketing Momentum & Global Adoption from Embedded to Enterprise | Calista Redmond, RISC-V International

Nov 15, 2021

FADU Technology Announces Speedy 14 GBps PCIe 5.0 SSD, up to 3.5 Million IOPS | Aaron Klotz, Tom’s Hardware

Nov 15, 2021

理研、創薬専用スパコン開発　「RISC-V」アーキテクチャ採用、10万原子の挙動再現 | [井上輝一，ITmedia

Nov 15, 2021

Compañía surcoreana anuncia una controladora PCIe 5.0 tipo RISC-V | Roberto Solé, Profesional Review

Nov 15, 2021

GCC Patches Pending For RISC-V’s Scalar Cryptography Extension | Michael Larabel, Phoronix

Nov 15, 2021

Video: ESP32-C3 Modular IoT board – OBJEX Link RISC-V | Salvatore Raccardi

Nov 15, 2021

OBJEX Link v1.6-C3 RISC-V | Salvatore Raccardi, Hackster.io

Nov 15, 2021

Video: Kneron 2021 semiconductor product launch | Kneron

Nov 15, 2021

Выпущена первая партия российского RISC-V микроконтроллера “МК32 АМУР” | Sergey Karasev, Server News

Nov 15, 2021

Plumerai develops embedded AI accelerator IP core for FPGAs | Nick Flaherty, EENews Europe

Nov 14, 2021

QEMU 6.2 On The Way With SGX For VMs, Apple Silicon, More RISC-V | Michael Larabel, Phoronix

Nov 12, 2021

Renesas RH850/U2B automotive SoC features RISC-V-based parallel co-processor | Jean-Luc Aufranc, CNX Software

Nov 9, 2021

SiFive Shepherds RISC-V ISA to Enterprise Applications, Broader Adoption | SiFive

Nov 9, 2021

Changing the Game With RISC-V ISA | Telink Staff

Nov 9, 2021

WinnerMicro W806 240 MHz MCU finds it way into a $2 development board | Jean-Luc Aufranc, CNX Software

Nov 9, 2021

A Novel Twist: Maxim Integrated Removes Risk of RISC-V with a Dual-Core Arm/RISC-V Microcontroller | Bill Giovino, Digi-Key

Nov 9, 2021

We Hope to See You at Intel® FPGA Technology Day 2021 | Alexa Labadie, Intel

Nov 9, 2021

SELENE Hardware Platform First Release | SELENE H2020 Project

Nov 9, 2021

建構基於RISC-V的MCU「芯」生態 | 作者 : 顧正書，EE Times China

Nov 9, 2021

How to run Ockam on RISC-V Linux | Ockam

Nov 9, 2021

NSITEXE DR1000C, a RISC-V based parallel processor IP with vector extension (DFP: Data Flow Processor) has been licensed for Renesas’ new RH850/U2B Automotive MCUs | NSITEXE

Nov 9, 2021

5 Talks on RISC-V Online Event | Veriest

Nov 9, 2021

Kneron’s RISC-V AI Chip Intends to Bring L1 and L2 Autonomy to “Any Vehicle” | Jake Hertz, All About Circuits

Nov 9, 2021

Video: Firefox 94 on Unmatched RISCV64 Linux Desktop! | Bits inside by René Rebe

Nov 9, 2021

A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures | Cristóbal Ramírez Lazo, César Alejandro Hernández, Oscar Palomar, Osman Sabri Unsal, Marco Antonio Ramírez, and Adrían Cristal

Nov 9, 2021

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM | Ataberk Olgun, Juan Gómez Luna, Konstantinos Kanellopoulos, Behzad Salami, Hasan Hassan, Oğuz Ergin, and Onur Mutlu

Nov 9, 2021

Andes Technology Issues GDR to Be Listed on Luxembourg | Andes Technologies

Nov 9, 2021

Open Source RT-Thread IoT OS Becomes a Member of RISC-V! | RT-Thread

Nov 9, 2021

Codasip Founder Karel Masařík Elected to RISC-V Technical Steering Committee | Codasip

Nov 9, 2021

Women Of The C-Suite: Calista Redmond Of RISC-V On The Five Things You Need To Succeed As A Senior Executive | Charlie Katz, Authority Magazine

Nov 9, 2021

VLSI Design Careers | Maven Silicon, Semiconductor Engineering

Nov 8, 2021

KVM Changes Land In Linux 5.16: RISC-V Hypervisor Support, AMD PSF Control Bit | Michael Larabel, Phoronix

Nov 8, 2021

Video: Implementing LOAD instructions: RISC-V ep.5 | Low Level JavaScript

Nov 8, 2021

How the RISC-V Atomic Extension Gives You Superior Bit Manipulation Capabilities | Bill Giovino, Digi-Key

Nov 7, 2021

Codasip Appoints Brett Cline to Drive Company Growth Worldwide | Codasip

Nov 7, 2021

What Computing Tech Will Drive Future Space Exploration? | Michelle Hampson, IEEE Spectrum

Nov 7, 2021

SME: Scalable Masking Extensions | Ben Marshall and Dan Page, University of Bristol and PQShield Ltd

Nov 5, 2021

How the Imagination RVfpga: Understanding Computer Architecture course is giving engineering under-grads real-world skills | Robert Owen, Imagination Technologies

Nov 4, 2021

Looking Towards the Future: FreeBSD on the RISC-V Architecture | Klara

Nov 4, 2021

Pixel 6: Setting a new standard for mobile security | Dave Kleidermacher, Jesse Seed, Brandon Barbello, and Stephan Somogyi, Android, Pixel & Tensor security teams, Google Security Blog

Nov 4, 2021

RISC-V-Based VEGA Brings Continual Learning to TinyML with an Order of Magnitude Efficiency Gain | Gareth Halfacree, Hackster.io

Nov 4, 2021

High-Level Synthesis For RISC-V | Brian Bailey, Semiconductor Engineering

Nov 4, 2021

Kneron Edge AI SoC Powered by Andes RISC-V Processor Core D25F | Andes Technology

Nov 3, 2021

Improving the OpenLane ASIC build flow with open source SystemVerilog support | Antmicro

Nov 2, 2021

How Alibaba is Porting RISC-V to the Android OS | Guoyin Chen, Alibaba

Nov 1, 2021

Truechip Introduces Silicon IP for Network on Chip (NOC) Focused for TileLink RISC-V Chips | Truechip

Oct 30, 2021

Build an open source-hardware Allwinner D1s RISC-V Linux SBC for under $10 | Jean-Luc Aufranc, CNX Software

Oct 29, 2021

Automatic SystemVerilog linting in GitHub Actions with Verible | Antmicro

Oct 28, 2021

RISC-V RV32I I-Type | Maven Silicon

Oct 27, 2021

Tiny SBC runs Linux on new RAM-equipped Allwinner RISC-V SoC |

Oct 26, 2021

SME: Scalable Masking Extensions | Ben Marshall (PQShield Ltd and University of Bristol) and Dan Page (University of Bristol)

Oct 26, 2021

Sneak peek into SiFive’s most powerful RISC-V yet | Steve Bush, Electronics Weekly

Oct 26, 2021

Video: 5 Stage Pipeline: RISC-V Processor In TS (part 3) | Low Level JavaScript

Oct 26, 2021

Codasip boosts Studio processor design tools | Neil Tyler, New Electronics

Oct 26, 2021

RISC-V-Based VEGA Brings Continual Learning to TinyML with an Order of Magnitude Efficiency Gain | Gareth Halfacree, Hackster.io

Oct 26, 2021

MangoPi-MQ1 Is an Ultra-Compact, Soon-to-be-Open Source Allwinner D1 RISC-V Dev Board | Gareth Halfacree, Hackster.io

Oct 26, 2021

New Allwinner RISC-V Chip Uncovered on Tiny Board | Ian Evenden, Tom’s Hardware

Oct 26, 2021

Recap of the Fall 2021 CHIPS Alliance Workshop | Rob Mains, CHIPS Alliance

Oct 25, 2021

Kit Close-Up: Lattice Semiconductor’s Crosslink-NX Development Kit | William G. Wong, Electronic Design

Oct 25, 2021

Socionext, Techsor and ZiFiSense Unveil IC for “ZETag,” a New Cloud Tag to Utilize ZETA Communication | AI Technology Insights

Oct 25, 2021

Intel CTO Greg Lavender interview — Why chip maker is spending on both manufacturing and software | Dean Takahashi, Venture Beat

Oct 25, 2021

Tutorial: Vortex tutorials at MICRO-54 (Oct 18 2021) | Hyesoon Kim, Blaise Tine, Ruobing Han, Liam Cooper, and Jeff Young, Georgia Institute of Technology

Oct 25, 2021

My experience installing Libero SoC in Ubuntu and Windows 10 | Jean-Luc Aufranc, CNX Software

Oct 25, 2021

GCC 12 Merges Initial Support For RISC-V’s Bitmanip Extensions | Michael Larabel, Phoronix

Oct 25, 2021

RISC-V starts to put pressure: 16-core CPU and performance superior to Cortex-A78 | Deepak Gupta, Tech Unwrapped

Oct 25, 2021

Alibaba Cloud pushes into South Korea, Thailand with faster, more efficient data centers | Peter Cohen, RCR Wireless News

Oct 25, 2021

IAR Systems Extends Functional Safety Offering for RISC-V with Build Tools for Linux | Tiera Oliver, Embedded Computing Design

Oct 25, 2021

Allwinner D1s/F133 RISC-V processor integrates 64MB DDR2 | Jean-Luc Aufranc, CNX Software

Oct 25, 2021

IAR Systems extends functional safety offering for RISC-V with leading build tools for Linux | IAR Systems

Oct 25, 2021

A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications | Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, and Saponara Sergio, IEEE Transactions on Emerging Topics in Computing

Oct 24, 2021

Video: Accelerating Neural Networks using RISC-V and Open Standard Software | Charles Macfarlane, Codeplay Software

Oct 24, 2021

SiFive Envisions 128-Core RISC-V SoCs as Gap With x86 and Arm Closes | Anton Shilov, Tom’s Hardware

Oct 24, 2021

ETH Zurich Team Unveils RISC-V-Based Snitch Processor, Boasts of Sixfold Performance Gains | Gareth Halfacree, Hackster.io

Oct 24, 2021

Research and Achievement of RISC-V for Embedded MCUs | WCH Micro Electronics

Oct 23, 2021

Showcasing the key features of the RT-Thread IoT OS and toolchain! | Lance Harvie, RT-Thread IoT OS Global Tech Conference 2021

Oct 23, 2021

PUFiot -The Secure Co-processor for RISC-V | PUFsecurity Corp.

Oct 23, 2021

AntChain Releases First Self-developed Blockchain Security Chip, the T1 | Pandaily

Oct 23, 2021

Vates joins RISC-V International | Vates

Oct 21, 2021

We’re closing the gap with Arm and x86, claims SiFive: New RISC-V CPU core for PCs, servers, mobile incoming | Agam Shah, The Register

Oct 21, 2021

Meet Snitch: the Small and Agile RISC-V Processor | Michelle Hampson, IEEE Spectrum

Oct 21, 2021

M5Stamp C3 RISC-V board supports WiFI 4, Bluetooth 5.0 Long Range and 2 Mbps bitrate | Jean-Luc Aufranc, CNX Software

Oct 20, 2021

Video: SMK68 – OpenSource RISCV Custom Mechanical Keyboard | Caesar Wu

Oct 20, 2021

Alibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910 | Jean-Luc Aufranc, CNX Software

Oct 20, 2021

De-RISC, the H2020 project which will create the first RISC-V fully European platform for aerospace, celebrates its second anniversary | Design and Reuse

Oct 19, 2021

Linley Fall Processor Conference 2021 | The Linley Group

Oct 19, 2021

The Basics of RISC-V: The Free Open Source Instruction Set | The New Stack

Oct 19, 2021

Power/Performance Bits: Oct. 19 | Jesse Allen, Semiconductor Engineering

Oct 19, 2021

Alibaba Announces Open Source RISC-V-Based Xuantie Series Processors | Pandaily

Oct 19, 2021

De-RISC – The H2020 Project Which Will Create The First RISC-V Fully European Platform For Aerospace, Celebrates Its Second Anniversary | Ana Rísquez Navarro, De-RISC

Oct 19, 2021

Andes Technology USA Corp. Announces Major Expansion of Its U.S. Operation | Andes Technology

Oct 18, 2021

Andes Presents “Datacenter Accelerators Using RISC-V” at Linley Fall Processor Conference 2021 | Chip Estimate

Oct 18, 2021

Segger licenses ARM and RISC-V compiler and linker to toolchain providers | Nick Flaherty , EE News Europe

Oct 18, 2021

Video: SERV Fistful of Gates Part 2 | Olof Kindgren, RISC-V Ambassador

Oct 18, 2021

Proposed RISC-V vector instructions crank up computing power on small devices | Agam Shah, The Register

Oct 18, 2021

Machine Learning: Esperanto coaxes 1092 RISC-V Processors to Dance on the Head of a Pin, er Chip | Amelia Dalton . Electronic Engineering Journal

Oct 18, 2021

OpenBSD 7.0 adds 64-bit RISC-V, improves Apple Arm silicon support | Jean-Luc Aufranc, CNX Software

Oct 18, 2021

HarmonyOS development board shows up for $11 | Jean-Luc Aufranc, CNX Software

Oct 17, 2021

LILYGO’s New TTGO T-32C3 Is a Compact, Sub-$3 Espressif ESP32-C3 RISC-V Microcontroller Module | Gareth Halfacree, Hackster.io

Oct 17, 2021

The 5th AI Edge Contest (Implementation Contest 3) Vehicle Driving Image Recognition using RISC-V | Signate

Oct 17, 2021

2nd National RISC-V Student Contest 2021-2022 Sponsored by Thales, the GDR SOC2 and the CNFM | Thales

Oct 17, 2021

Open Source Debayerization blocks in FPGA | Antmicro

Oct 16, 2021

Enthusiasts dash for RISC-V computer with GPU | Agam Shah, The Register

Oct 16, 2021

“Una versión de Windows para RISC-V es posible”: hablamos con Roger Espasa, CEO de Semidynamics | Javier Pastor, Xataka

Oct 16, 2021

Green Hills covers RISC-V with Integrity | Steve Bush, Electronics Weekly

Oct 15, 2021

Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics Research | Blaise Tine, Fares Elsabbagh, Krishna Yalamarthy, and Hyesoon Kim, Georgia Institute of Technology

Oct 15, 2021

Korean Language Video: The first SoC for security cameras designed with open source RISC-V – An Interview with Inix CEO Hwang Jung-hyun | Park Hye-jin PD, The Elec

Oct 15, 2021

RISC-V: The Next Revolution in the Open Hardware Movement | Olivier Lambert, The New Stack

Oct 14, 2021

Video: RISC-V Business – Testing Gaming and More on the HiFive Unmatched from SiFive | Level1Techs

Oct 13, 2021

Getting Started with the Yocto Linux BSP for Polarfire SoC FPGA Icicle Kit | Jean-Luc Aufranc, CNX Software

Oct 13, 2021

Dev kit debuts RISC-V XuanTie C910 SoC with a 3D GPU and Android and Linux support | Eric Brown, Linux Gizmos

Oct 13, 2021

ZAYA Now Offers Trusted Execution Environment For RISC-V | ZAYA

Oct 12, 2021

Bluespec, Inc. releases ultra-low footprint RISC-V processor family for Xilinx® FPGAs, offers free quick-start evaluation | Bluespec

Oct 12, 2021

Codasip Announces UK Hiring for RISC-V Development | Robin Mitchell, ElectroPages

Oct 12, 2021

Intel Infuses Nios Soft Processors with RISC-V Instruction Set | Aleksandar Kostovic, Tom’s Hardware

Oct 10, 2021

Java port eyed for RISC-V hardware | Paul Krill, InfoWorld

Oct 9, 2021

European supercomputer project receives RISC-V test chips | Nick Flaherty, EE News Europe

Oct 7, 2021

SiFive HiFive Unmatched Hands-On, Initial RISC-V Performance Benchmarks | Michael Larabel, Phoronix

Oct 7, 2021

Chiplet Strategy is Key to Addressing Compute Density Challenges | Balaji Baktha, EE Times

Oct 7, 2021

RISC-V Mentorship: Formal Verification of SweRV EL2 Processor | Shashank V.M.

Oct 6, 2021

Intel backs RISC-V for Nios FPGA processor | Nick Flaherty, EE News Europe

Oct 6, 2021

Security Enclave IP based on RISC-V | Silex Insight

Oct 5, 2021

Startup Funding for September 2021 | Jesse Allen, Semiconductor Engineering

Oct 5, 2021

Sipeed Teases Linux-Capable 64-Bit RISC-V System-on-Module — for Under $20 | Gareth Halfacree, Hackster.io

Oct 5, 2021

Initializing RISC-V: A Guided Tour for ARM Developers | Ahmad Fatoum and Rouven Czerwinski, Pengutronix

Oct 5, 2021

How RISC-V and CHIPS Alliance are Driving a New Unified Memory Architecture Standard | CHIPS Alliance

Oct 4, 2021

CHERI Software Release for Summer 2021 | George Neville-Neil, Light Blue Touchpaper

Oct 4, 2021

SiPearl opens design centre in Grenoble, looks for 50 engineers | Nick Flaherty, EE News Europe

Oct 4, 2021

Calculating the big picture: Future HPC efforts will soon see off its von Neumann past | Rupert Goodwins, The Register

Oct 3, 2021

A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System | Haifeng Zhang, Xiaoti Wu, Yuyu Du, Hongqing Guo, Chuxi Li, Yidong Yuan, Meng Zhang and Shengbing Zhang

Oct 2, 2021

RISC-V: The New Architecture on the Block | Klara Systems

Oct 2, 2021

SiPearl opens design centre in Grenoble, looks for 50 engineers | Nick Flaherty, EE News Europe

Oct 2, 2021

IoT Use Cases Based on Telink TLSR9 Series RISC-V Connectivity SoC | Telink Semiconductor, RISC-V Con China

Oct 1, 2021

The RISC-V BL602 Book | Lee Lup Yuen

Oct 1, 2021

MicroZed Chronicles: Bluespec RISC-V | Adam Taylor, Adiuvo Engineering and Training, LTD.

Oct 1, 2021

Esperanto Technologies on Accelerating Machine Learning | Dave Ditzel, Hot Chips 33

Oct 1, 2021

Agenda for the RISC-V Summit 2021: Together We Are Shaping the Open Era of Computing

Oct 1, 2021

Security Enclave IP Based on RISC-V | Silex Insight

Oct 1, 2021

RVSoC Project: A Portable and Linux Capable RISC-V Computer System on an FPGA | Arch Lab, Tokyo Tech

Sep 28, 2021

RISC-V Upstart Targets ML Inference Performance, Power Efficiency | Jeffrey Burt, The Next Platform

Sep 28, 2021

6,000 RISC-V Cores on a Xilinx FPGA Break the CoreScore World Record | Francisco Pires, Tom’s Hardware

Sep 28, 2021

Chiplet Strategy is Key to Addressing Compute Density Challenges | Balaji Baktha of Ventana Micro Systems, EE Times

Sep 28, 2021

Bluespec, Inc. Releases Ultra-Low Footprint RISC-V Processor Family for Xilinx FPGAs, Offers Free Quick-Start Evaluation | Design & Reuse

Sep 28, 2021

VS Code Venus RISC-V extension 1.0.0 released | Stefan Wallentowitz, RISC-V @ HM

Sep 28, 2021

Maven Silicon organized a Panel Discussion on the topic “Hard-to-Hire VLSI Engineers”

Sep 27, 2021

Codasip Opens UK Design Center Led by Simon Bewick | Codasip

Sep 27, 2021

Privileged Specification Version 1.12 Now Open to Public Review

Sep 27, 2021

RISC-V – running GNOME OS on SiFive hardware for the first time | Valentin David and Sam Thursfield, Codethink

Sep 27, 2021

SHREC Students Clinch Best Paper Award for Research in Space Computing | Leah Russell,

Sep 27, 2021

New CoreScore World Record Crams 6,000 SERV RISC-V Cores Into a Single FPGA | Gareth Halfacree, Hackster.io

Sep 27, 2021

Studying RISC-V architecture to create customized systems for space computing | Leah Russell, University of Pittsburgh

Sep 26, 2021

EdgeQ Samples 5G Basestation-on-a-Chip | Sally Ward-Foxton, EE Times

Sep 26, 2021

EPI EPAC1.0 RISC-V Test Chip Samples Delivered | European Processor Initiative

Sep 25, 2021

Global alliance formed to promote open hardware support for women and underrepresented individuals | Aimee Kalnoskas, EE World Online

Sep 25, 2021

Video: RISC-V RV32I B-Type | Maven Silicon

Sep 24, 2021

Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software

Sep 23, 2021

PUFiot: An Essential Secure Coprocessor for RISC-V | Sam Chung, Sean H. Wu, and Evans Yang, PUF Security

Sep 23, 2021

Video: It’s Not Just About Embedded! | The Yocto Project

Sep 23, 2021

Zephyr RTOS + RISC-V – see the live demo at Open Source Summit/Embedded Linux Conference! | Jonathan Beri, Golioth

Sep 23, 2021

New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The Register

Sep 23, 2021

Optimization Driving Changes In Microarchitectures | Ann Steffora Mutschler, Semiconductor Engineering

Sep 22, 2021

RISC-V Chiplets, Disaggregated Die, and Tiles | Chris Jones, SiFive

Sep 22, 2021

ZAYA now supports RISC-V | Zaya

Sep 22, 2021

…and out come SweRVolf | Olof Kindgren, Qamcom

Sep 21, 2021

Open source SystemVerilog tools in ASIC design | Antmicro, Google Open Source Blog

Sep 20, 2021

Unlock the RISC-V Naming Code | Richard A. Quinnell, Digi-Key

Sep 20, 2021

The Accuracy and Efficiency of Posit Arithmetic | Stefan Dan Ciocirlan, Dumitrel Loghin, Lavanya Ramapantulu, Nicolae Tapus, and Yong Meng Teo

Sep 19, 2021

HiFive Unmatched – some benchmarking results | Gábor Samu, Technical Computing Goulash

Sep 18, 2021

Whitepaper: Ensuring the Success of Your RISC-V Product with a Commercial-Grade Software Development Ecosystem | Engineering.com

Sep 18, 2021

Data Center Hot Chips, Plus Aart de Geus on AI in Chip Design | Sally Ward-Foxton , EE Times

Sep 17, 2021

RISC-V Pioneer SiFive Opens its First UK Office, Announces Hiring Push | Gareth Halfacree , AB Open

Sep 16, 2021

Study about the impact of open source software and hardware on technological independence, competitiveness and innovation in the EU economy | European Commission

Sep 16, 2021

RISC-V Launches the Open Hardware Diversity Alliance

Sep 15, 2021

Announcing the latest Open Source Peer Bonus winners | Google Open Source Blog

Sep 15, 2021

Russian Company Develops 32-Bit RISC-V Microcontroller | Anton Shilov , Tom’s Hardware

Sep 15, 2021

Epileptic Seizure Detection on an Ultra-Low-Power Embedded RISC-V Processor Using a Convolutional Neural Network | Andreas Bahr, Matthias Schneider, Maria Avitha Francis, Hendrik M. Lehmann, Igor Barg, Anna-Sophia Buschhoff, Peer Wulff, Thomas Strunskus, and Franz Faupel

Sep 15, 2021

Antmicro Doubles Down on Commitment to Zephyr RTOS as Community Grows to More Than 1,000 Contributors | The Zephyr Project

Sep 15, 2021

Getting Started with the ESP32-C3 RISC-V MCU | Mathias Claussen, Elektor Magazine

Sep 15, 2021

New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The Register

Sep 15, 2021

LoRaWAN on PineDio Stack BL604 RISC-V Board | Lup Yuen Lee

Sep 14, 2021

El Correo Libre Issue 42 | Gareth Halfacree, LibreCores

Sep 14, 2021

Synopsys Accelerates Most Stringent Functional Safety Certification of NSITEXE RISC-V Parallel Processor IP | Design and Reuse

Sep 14, 2021

Open Source HW and RISC-V – Linked but not the same | Luca Benini , PULP Platform

Sep 14, 2021

Chinese companies are interested in RISC-V to localize semiconductors | Kim Won-jung, The Korea Industry Daily

Sep 14, 2021

Forget Microservices: A NIC-CPU Co-Design For The Nanoservices Era | Timothy Prickett Morgan, The Next Platform

Sep 13, 2021

Andes Technology Corp. Brings Its Broad Family of RISC-V CPU IP to the Silicon Catalyst Semiconductor Incubator | Chip Estimate

Sep 13, 2021

Getting started with Bluetrum AB32VG1 RISC-V Bluetooth audio board using RT-Thread | Jean-Luc Aufranc, CNX Software

Sep 13, 2021

Video: CFU Playground | Alan Green, PyConline AU 2021

Sep 13, 2021

Why It’s the Perfect Time to Join Codasip and be Part of the RISC-V Revolution | Rupert Baines, CMO Codasip

Sep 13, 2021

RISC-V to Shake up $8.6-Billion Semiconductor IP Market | William Li, Counterpoint Research

Sep 9, 2021

LILYGO T-32C3 – A small ESP32-C3 WiFi & BLE IoT module with 4MB flash | Jean-Luc Aufranc , CNX Software

Sep 9, 2021

PUFiot – An Essential Security Coprocessor for RISC-V Designs | Sam Chung, Embedded Computing Design

Sep 9, 2021

Mikron MIK32 – Made in Russia 32-bit RISC-V MCU offers features similar to STM32L0 MCU | Jean-Luc Aufranc, CNX Software

Sep 9, 2021

Intro to the Microchip FPGA and SoC-Based RISC-V Ecosystem | Alex Pluemer, Mouser Electronics

Sep 9, 2021

Supporting CUDA for an extended RISC-V GPU architecture | Ruobing Han, Blaise Tine, Jaewon Lee, Jaewoong Sim, Hyesoon Kim

Sep 9, 2021

Fun with Open Source Semis | Jonathan Goldberg, Digits to Dollars

Sep 9, 2021

LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!

Sep 8, 2021

Coffee disease classification with ML | João Vitor Yukio Bordin Yamashita, Hackster.io

Sep 8, 2021

Video: Low-Power License Plate Detection and Recognition on a RISC-V Multi-Core MCU-based Vision System | Lorenzo Lamberti, EMEA 2021 Student Forum

Sep 8, 2021

Andes Technology Corp. Brings Its Broad Family of RISC-V CPU IP to the Silicon Catalyst Semiconductor Incubator | Design and Reuse

Sep 7, 2021

Tech giants are rushing to develop their own chips — here’s why | Sam Shead, CNBC

Sep 7, 2021

Nvidia CUDA Software Gets Ported to Open-Source RISC-V GPGPU Project | Aleksandar Kostovic , Tom’s Hardware

Sep 7, 2021

RISC-V Gains Traction in the Data Center | Jake Hertz, All About Circuits

Sep 7, 2021

All the Polynomial Multiplication You Need on RISC-V | Hwajeong Seo, Hyeokdong Kwon, Siwoo Eum, Kyungbae Jang, Hyunjun Kim, Hyunji Kim, Minjoo Sim, Gyeongju Song, and Wai-Kong Lee

Sep 7, 2021

Public Review Period Opens for Proposed RISC-V Scalar Cryptography Extensions | Gareth Halfacree , AB Open

Sep 7, 2021

RT-Thread Partnered with WCH Mircoelectronics, to Promote More Applications for RISC-V Ecosystem! | RT-Thread

Sep 7, 2021

Yadro’s RISC-V Designers Show Students How to Design Processors | Yuri Panchul, Habr

Sep 6, 2021

Video: NixOS/Nix – Cross Compilation via pkgsCross | Matthew Croughan

Sep 6, 2021

A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method | Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, and Zhiyi Yu, IEEE XPlore

Sep 6, 2021

RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute | Nitin Dahad, EE Times

Sep 5, 2021

RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures | Gianna Paulin, Renzo Andri, Francesco Conti, and Luca Benini, IEEE Xplore

Sep 5, 2021

Semiconductor veterans gather to design customizable, chiplet-based RISC-V server processors | Chris Williams, The Register

Sep 5, 2021

End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? | Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti, Irem Boybat, Luca Benini, and Davide Rossi

Sep 4, 2021

Andes Technology and Cyberon Collaborate to Provide Edge-Computing Voice Recognition Solution on DSP-capable RISC-V Processors | Intrado

Sep 3, 2021

Simpira Gets Simpler: Optimized Simpira on Microcontrollers | Minjoo Sim and Siwoo Eum and Hyeokdong Kwon and Kyungbae Jang and Hyunjun Kim and Hyunji Kim and Gyeongju Song and Wai-Kong Lee and Hwajeong Seo, Cryptology ePrint

Sep 3, 2021

RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography Extensions

Sep 3, 2021

Video: Apple’s GPU Maker is Designing RISC-V CPUs for Mobiles and Desktops | Gary Explains

Sep 2, 2021

A Novel Compaction Approach for SBST Test Programs | Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, and Matteo Sonza Reorda

Sep 2, 2021

Haawking licenses SEGGER’s emRun for RISC-V | SEGGER

Sep 2, 2021

Hot Chips Concludes An Amazing Lineup of AI Chip Companies | Karl Freund, Forbes

Sep 2, 2021

Apple Exploring RISC-V, Hiring RISC-V ‘High Performance’ Programmers | Anton Shilov, Tom’s Hardware

Sep 1, 2021

Rivos Inc: A Chip Off The Old Block? New RISC-V Startup Garners Many Senior CPU Architects From Apple, Google, Marvell, Qualcomm, Intel, and AMD | Dylan Patel, Semi Analysis

Sep 1, 2021

Ventana Micro Systems raises $38M to design datacenter RISC-V processors | Dean Takahashi, Venture Beat

Aug 31, 2021

efabless, Google and SkyWater Are Enabling Us Mere Mortal Makers to Design Our Own Open Source ASICs | Tom Fleet, Hackster.io

Aug 30, 2021

AB32VG1 – An Arduino Uno-like RISC-V based development Board Designed for Audio Applications | Electronics-Lab

Aug 30, 2021

Linux 5.14 Release – Main changes, Arm, MIPS, and RISC-V architectures | Jean-Luc Aufranc, CNX Software

Aug 30, 2021

Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin Mishra

Aug 30, 2021

Accelerating exhaustive and complete verification of RISC-V processors | Ashish Darbari, Axiomise

Aug 28, 2021

Podcast: David Patterson – “RISC-V, Tesla’s D1 Chip, The Future of Hardware For Machine Learning” | Marwa ElDiwiny, Soft Robotics Podcast

Aug 28, 2021

Andes Technology and Cyberon Collaborate to Provide Edge-Computing Voice Recognition Solution on DSP-capable RISC-V Processors | Chip Estimate

Aug 27, 2021

Imagination Technologies to design RISC-V cores | Jean-Luc Aufranc, CNX Software

Aug 26, 2021

A Hardware Platform for Ensuring OS Kernel Integrity on RISC-V

Aug 26, 2021

Open source custom GitHub Actions runners with Google Cloud and Terraform | Antmicro

Aug 25, 2021

Esperanto Emerges From Stealth With 1,000-Core RISC-V AI Accelerator | Sally Ward-Foxton, EE Times

Aug 25, 2021

French: Espressif dévoile une puce-système radio ESP32 à cœur RISC-V… compatible Bluetooth, Zigbee et Thread | Pierrick Arlot, L’Embarqué

Aug 25, 2021

Open source DDR controller framework for mitigating Rowhammer | Antmicro

Aug 25, 2021

Imagination Technologies Enters the CPU Space With RISC-V Architecture | Francisco Pires, Tom’s Hardware

Aug 25, 2021

When You Come to a Fork in the Road, TAKE IT! | Jose Betancourt, SUSE

Aug 24, 2021

Video: Morpheus II – A RISC-V Security Extension for Protecting Vulnerable Software and Hardware | Todd Austin, HotChips 2021

Aug 24, 2021

Esperanto Launches AI Accelerator With Over 1000 RISC-V Cores | Karl Freund, Forbes

Aug 24, 2021

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | Esperanto

Aug 24, 2021

RISC-V Embraces AI and ML with a Dual-Core 64-bit Machine Vision/Hearing Development Board | Bill Giovino, Digi-Key Electronics

Aug 24, 2021

Video: RT Thread Board Quick Demo | Lance Harvie, Runtime

Aug 24, 2021

Esperanto Technologies Unveils Energy-Efficient RISC-V-Based Machine Learning Accelerator Chip At Hot Chips 33 Conference | Esperanto Technologies

Aug 23, 2021

Bluetrum’s AB32VG1 is Arduino Uno-like RISC-V Based Development Board | Open Cloudware

Aug 23, 2021

RISC-V Benchmarking for Onboard Sensor Processing | Michael J. Cannizzaro, Evan W. Gretok, and Alan D. George

Aug 23, 2021

Thales, IIIT-Delhi Sign MoU On Open Source Hardware R&D | Editorial Team, Open Source for You

Aug 23, 2021

Zephyr FPGA controller | Antmicro

Aug 23, 2021

Picocom Accelerates 5G Communications SoC Development with Cadence Palladium Emulation | 01net, Business Wire

Aug 23, 2021

Google Summer of Code’21 at FOSSI Foundation: M-extension Support for SERV | Zeeshan Rafique, RISC-V Ambassador

Aug 22, 2021

Espressif Expands their RISC-V Portfolio with new ESP32-H2 Thread+Zigbee+BLE SoC | Vishnu Mohanan, Circuit State

Aug 22, 2021

Ultra-Low-Power RISC-V System-on-Chip features Adaptive Body Biasing Technology | Abhishek Jadhav, CNX Software

Aug 22, 2021

EdgeQ Samples 5G Basestation-on-a-Chip | Sally Ward-Foxton, EE Times

Aug 22, 2021

A lightweight ISE for ChaCha on RISC-V | Ben Marshall, Daniel Page, and Thinh Hung Pham, Cryptology

Aug 22, 2021

DIY LED Cube For The Masses | Inderpreet Singh, Hackaday

Aug 20, 2021

RISC-V – A Baremetal Introduction using C++ | Phil Mulholland

Aug 18, 2021

EdgeQ samples SoC for 5G and AI inference engines | Michael Vizard, Venture Beat

Aug 18, 2021

A First Look at RISC-V Virtualization from an Embedded Systems Perspective | Bruno Sá, José Martins, and Sandro Pinto

Aug 17, 2021

RISC-V Chip Delivers Quantum-Resistant Encryption | Charles Q. Choi, IEEE Spectrum

Aug 17, 2021

Working With RISC-V | Ed Sperling, Semiconductor Engineering

Aug 17, 2021

RISC-V Wireless Chip With Adaptive Body Bias Reaches pW power | Nick Flaherty, EE News Europe

Aug 17, 2021

RISC-V RV32I R-Type | Maven Silicon

Aug 16, 2021

XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage | Thinh H. Pham, Ben Marshall, Alexander Fell, Siew-Kei Lam, and Daniel Page, Cryptology

Aug 16, 2021

RISC-V CEO: The biggest opportunity to change computing since the 1980s | Tiernan Ray, ZDNet

Aug 15, 2021

Rolf Segger on the chip shortage | Nick Flaherty , EE News Europe

Aug 13, 2021

Secure FPGA RISC-V SoC Forgoes Heatsink | William G. Wong, Electronic Design

Aug 12, 2021

SEGGER Releases Floating Point Library to Support RISC-V | Raspberry Pi Projects

Aug 10, 2021

Mythic Licenses Codasip’s L30 RISC-V Core for Next-Generation AI Processor |

Aug 10, 2021

Announcing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and Zhinxmin

Aug 10, 2021

Researchers Develop RISC-V Chip for Quantum-Resistant Encryption | Francisco Pires, Tom’s Hardware

Aug 9, 2021

TUM Researchers Design Chip for ‘Post Quantum’ Cryptography | John Russell, HPC Wire

Aug 9, 2021

Video: Booting the HiFive Unmatched board | Gábor Samu

Aug 9, 2021

Video: Glitching RISC-V chips: MTVEC corruption for hardening ISA | Adam Zabrocki and Alex Matrosov, DEF CON 29

Aug 9, 2021

Open source SystemVerilog tools in ASIC designOpen source SystemVerilog tools in ASIC design

Aug 6, 2021

Video: OSDI 21 – The nanoPU: A Nanosecond Network Stack for Datacenters

Aug 6, 2021

Hands-On: Whiskey Pirates DC29 Hardware Badge Blings With RISC-V | Mike Szczys, Hackaday

Aug 6, 2021

Huawei Release Their First RISC-V Development System – Hi3861 | Robin Mitchell, electropages

Aug 6, 2021

The RISC-V Platform Specification aims to ensure RISC-V hardware and software compatibility | Jean-Luc Aufranc, CNX Software

Aug 5, 2021

Video: VSD – Pipelining RISC-V with Transaction-Level Verilog | Lea Pegeen

Aug 5, 2021

Video: Next-Generation Vector Processor Design II | Dr. Thang Tran, Andes Technology

Aug 5, 2021

StarFive open source single board hardware platform will be officially released by the end of Q3 2021

Aug 5, 2021

BL-63B – A smaller BL602 IoT module that sells for $1.5 | Jean-Luc Aufranc, CNX Software

Aug 5, 2021

Radxa and StarFive Partner to Deliver RISC-V Single Board PC to Consumers | Aleksandar Kostovic, Tom’s Hardware

Aug 4, 2021

Video: QEMU RV32I Installation & Setup | John’s Basement

Aug 4, 2021

NSI-TEXE achieves world’s first RISC-V processor with vector extension certified for ISO 26262 ASIL D ready product

Aug 4, 2021

Post-quantum chip has built-in hardware Trojan | Christoph Hammerschmidt, EE News Europe

Aug 3, 2021

Video: RISC-V RV32I R-Type | Maven Silicon

Aug 3, 2021

Custom RISC-V Processor Built in VHDL | Bryan Cockfield, Hackaday

Aug 3, 2021

seL4 Integrity Enforcement Proved for RISC-V

Aug 3, 2021

“中国信芯” 再迈一步，万向区块链携生态伙伴举办RISC-V区块链行业工作组首次公开活动

Aug 2, 2021

Ingenic T40, focusing on the new SVIoT track | Muzi, Leiphone.com

Aug 1, 2021

Video: EKF for a 9-DOF IMU on a RISC-V MCU | Hien Vu

Jul 29, 2021

Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer | Hannah McLaughlin

Jul 29, 2021

SERV : RISC-V for a fistful of gates | Diode Zone

Jul 29, 2021

RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV | By Lee Moore and Simon Davidmann, Semiconductor Engineering

Jul 28, 2021

ESP32-H2 Bluetooth LE & 802.15.4 RISC-V SoC shows up in ESP-IDF source code | Jean-Luc Aufranc

Jul 28, 2021

The 2021 RISC-V Summit to Co-Locate with the 58th Design Automation Conference (DAC) in San Francisco | Yahoo! Finance

Jul 28, 2021

The 2021 RISC-V Summit Will Demonstrate Adoptions and Technical Advances This December in San Francisco

Jul 27, 2021

Espressif’s Unannounced RISC-V ESP32-H2 LR-WPAN SoC Leaks in an SDK Update | Gareth Halfacree, Hackster.io

Jul 27, 2021

Is RISC-V the Future? | Codasip

Jul 27, 2021

Delivering on the Promise of Industry-Leading RISC-V Processors | Drew Barbier, SiFive

Jul 26, 2021

Design flow of the DRAC project |

Jul 25, 2021

Russia to Build 8-Core RISC-V CPUs for Laptops, Government Systems | Joel Hruska, Extreme Tech

Jul 25, 2021

Whitepaper: RISC-V processor core for functional safety | Fraunhofer Institute for Photonic

Jul 24, 2021

Computer scientist showcases world’s first RISC-V-based Linux PC coupled with an AMD RX 6700 XT GPU | Bogdan Solca, Notebook Check

Jul 23, 2021

GNOME, Wireshark update in Tumbleweed | Douglas DeMaio, OpenSuse

Jul 23, 2021

World’s First Desktop PC RISC-V Board Meets AMD Radeon RX 6700 XT | Anton Shilov, Tom’s Hardware

Jul 23, 2021

Interview With Dirk Koch and Nguyen Dao | Matt Venn, Zero To ASIC

Jul 22, 2021

Introduction & Developer Tips for Zephyr RTOS | Zephyr Project

Jul 21, 2021

Video: Pineapple One: An Open-Source Discrete 32-Bit RISC-V CPU

Jul 21, 2021

CAES Receives Contract from Vinnova to Advance High Performance RISC-V Space Computing

Jul 20, 2021

Life in a Formal Verification Lane | Shivani Shah

Jul 20, 2021

Agile Analog brings analog IP to RISC-V International | Jean-Pierre Joosting, Design & Reuse

Jul 20, 2021

René Rebe Patches the Linux Kernel for “World’s First” Look at a Radeon RX 6700XT on a RISC-V PC | Gareth Halfacree, Hackster.io

Jul 19, 2021

WARP-V: A RISC-V CPU Core Generator Supporting MIPS ISA | Abhishek Jadhav, CNX Software

Jul 19, 2021

Previewing the Beagle V | Mender.io

Jul 19, 2021

What You Need to Know About Verilator Open Source Tooling | Rob Mains, CHIPS Alliance

Jul 19, 2021

Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites

Jul 16, 2021

Case Study: SiFive Launches Unmatched Board Remotely | Blue Clover Devices

Jul 15, 2021

RISC-V processor core for functional safety supported by development tools | electropages

Jul 15, 2021

Russia’s Elbrus has a RISC-V competitor as Yadro prepares native chips for launch | Gareth Halfacree, The Register

Jul 14, 2021

Compsci eggheads bring OpenCL framework to RISC-V to push parallel performance | Gareth Halfacree, The Register

Jul 14, 2021

What is RISC-V? | Abhishek Jadhav

Jul 14, 2021

Video: Decade of RISC-V Desktop?! HiFive Unmatched First Look

Jul 14, 2021

A Free RISC-V CPU Core Builder – Democratizing CPUs | Steve Hoover, Redwood EDA

Jul 13, 2021

NSITEXE achieves world’s first RISC-V processor with vector extension certified for ISO 26262 ASIL D ready product |

Jul 12, 2021

RISC-V RV32I Assembly – Multiplication | Maven Silicon

Jul 12, 2021

Chinese Wearable Technology Firm Huami to Launch New OS with Better Understanding of Users | Pandaily

Jul 12, 2021

Andes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extension

Jul 12, 2021

NodeMCU Launches Sub-$5 Espressif ESP32-C3 RISC-V Development Boards | Gareth Halfacree, Hackster.io

Jul 12, 2021

RISC-V Bytes: Introduction to Instruction Formats | Daniel Mangum

Jul 11, 2021

Bringing OpenCL to Commodity RISC-V CPUs | Tine Blaise, Seyong Lee, Jeff Vetter, and Hyesoon Kim, Georgia Institute of Technology

Jul 11, 2021

A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI | David Schor, WikiChip Fuse

Jul 11, 2021

Huami Will Unveil Self-developed OS, Chip, GPU at Next Beat 2021 Conference | Kamlesh Bhati, Sparrows News

Jul 10, 2021

Building occupancy management solution using the TensorFlow Object Detection API | GreenWaves Technologies

Jul 9, 2021

A Survey on RISC-V Security: Hardware and Architecture | Tao Lu, Marvell Semiconductor Ltd

Jul 9, 2021

Fraunhofer IPMS RISC-V processor core for functional safety supported by development tools from IAR Systems | Franka Balvin, IDW

Jul 9, 2021

Canaan Announces Kendryte K510 Edge AI Chip as a Triple-Core RISC-V Part with 3 TOPS NPU | Gareth Halfacree, Hackster.io

Jul 9, 2021

Kendryte K510 tri-core RISC-V AI processor deliver up to 3 TOPS | Jean-Luc Aufranc, CNX Software

Jul 9, 2021

Fraunhofer IPMS RISC-V processor core for functional safety supported by development tools from IAR Systems | Design & Reuse

Jul 9, 2021

Embedded development board features Microchip PolarFire RISC-V FPGA SoC | Jean-Luc Aufranc, CNX Software

Jul 9, 2021

Fraunhofer IPMS RISC-V processor core for functional safety supported by development tools from IAR Systems

Jul 9, 2021

Suse Tumbleweed Gets RubyGems Updates, New systemd

Jul 8, 2021

SBC builds on PolarFire SoC with dual GbE and CAN | Eric Brown, Linux Gizmos

Jul 8, 2021

The Importance of Increasing Diversity in the Open Source Community

Jul 6, 2021

NeuralScale: Industry Leading General Purpose Programmable NPU Architecture based on RISC-V

Jul 6, 2021

Video: tinyML Talks France – State of the TinyML today

Jul 6, 2021

Open Source Mindset with Michael Gielda | The Amp Hour

Jul 6, 2021

Zephyr RTOS Virtualization and Memory Isolation | Zephyr Project

Jul 6, 2021

Video: How to make a 32-bit RISC-V CPU

Jul 6, 2021

Video: Homemade 32-bit RISC-V CPU | JLCPCB

Jul 6, 2021

Chinese chip designers hope to topple Arm’s Cortex-A76 with XiangShan RISC-V design | Gareth Halfacree, The Register

Jul 5, 2021

GreenWaves releases Profiler – A visualization tool for profiling and debugging GAP applications

Jul 5, 2021

XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 | Jean-Luc Aufranc, CNX Software

Jul 5, 2021

DC-SCM compatible open source BMC hardware platform | Antmicro

Jul 4, 2021

Video: Exception handling in a RISC-V core – Exercise #7 | Learn RISC-V

Jul 2, 2021

Announcing the Research Triangle RISC-V Community Group | Daniel Mangum

Jul 2, 2021

Week In Review: Design, Low Power | Jesse Allen, Semiconductor Engineering

Jul 2, 2021

Andes Technology Announces Over 2 Billion Shipments Of Andes-Embedded SoCs In 2020

Jul 2, 2021

Video: Spike & Proxy Kernel from Source to Hello World | Danny Pratama

Jul 2, 2021

Video: Spike Debugging, OpenOCD, and GDB | Danny Pratama

Jul 2, 2021

Video: GCC Toolchain & SiFive Prebuilt Toolchain | Derry Pratama

Jul 2, 2021

SiFive Collaborates with Imperas on Models of SiFive’s RISC-V Core IP Portfolio

Jul 1, 2021

Deep neural networks… IN SPAAACE: Vector-enhanced RISC-V chips could give satellites onboard AI | Gareth Halfacree, The Register

Jul 1, 2021

SiFive Performance P550 Core Sets New Standard as Highest Performance RISC-V Processor IP

Jun 30, 2021

Advanced co-simulation with Renode and Verilator: PolarFire SoC and FastVDMA | Antmicro

Jun 30, 2021

A Process Independent Power Optimised Register File Architecture

Jun 30, 2021

RISC-V Bytes: Passing on the stack | Daniel Mangum

Jun 30, 2021

Imperas Expands Partnership with Valtrix to Address Growing RISC-V Verification Market

Jun 30, 2021

Video: SSRC Collaborates with Global Universities on RISC-V-Based Secure Flight Computer System | ATRC

Jun 30, 2021

SiFive Deepens RISC-V Core Lineup | William G. Wong, Electronic Design

Jun 30, 2021

BSC, Codeplay and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVM

Jun 30, 2021

RiVer Core: A RISC-V Core Verification Framework

Jun 30, 2021

On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors

Jun 29, 2021

Wanxiang Blockchain Organized the First Public Activity of RISC-V Blockchain SIG with Partners

Jun 29, 2021

Canonical Launches Its First Official Ubuntu RISC-V Builds, for SiFive’s Unleashed and Unmatched | Gareth Halfacree, hackster.io

Jun 28, 2021

Canonical Announces Ubuntu Support For RISC-V | Steven Dickens, Futurum

Jun 28, 2021

TII’s Secure Systems Research Centre Collaborates with Global Universities on RISC-V-Based Secure Flight Computer System

Jun 28, 2021

Video: RISC-V Ubuntu, Benchmarks and Gaming on the HiFive Unmatched | Tired Technician

Jun 28, 2021

SiFive Collaborates with Imperas on Models of SiFive’s RISC-V Core IP Portfolio

Jun 28, 2021

Automotive Hardware Functional Safety (FuSa) Features: ISO 26262

Jun 28, 2021

Ubuntu 20.04/21.04 64-bit RISC-V released for QEMU, HiFive boards | Jean-Luc Aufranc, CNXsoft

Jun 28, 2021

Linux 5.13 Release – Notable changes, Arm, MIPS and RISC-V architectures | Jean-Luc Aufranc, CNXsoft

Jun 27, 2021

Video: Pineapple – the 32-bit RISC-V CPU that you can make at home | Filip Szkandera

Jun 27, 2021

A Free RISC-V CPU Core Builder – Democratizing CPUs | Steve Hoover

Jun 25, 2021

An Introduction to Digi-Key’s RISC-V Reference Guide | Rich Miron, DigiKey

Jun 25, 2021

RISC-V BYTES: CALLER AND CALLEE SAVED REGISTERS | Daniel Mangum

Jun 25, 2021

RiVer Core: A RISC-V Core Verification Framework

Jun 25, 2021

Video: FreeBSD Developer Summit June 2021 – RISC-V | Mitchell Horne, FreeBSD

Jun 25, 2021

A RISC-V Future? SiFive and Andes Aim to Shake Up the Processor Industry | Adrian Gibbons, All About Circuits

Jun 25, 2021

Will We Soon Be Running Linux on SiFive Cores Made by Intel? | Jenny List, Hackaday

Jun 25, 2021

專訪RISC-V International技術長與晶心科技執行長：RISC-V是必然趨勢

Jun 25, 2021

RISC: Open Hardware

Jun 24, 2021

Mathias Claussen’s Guide Puts Quake on Your RISC-V Microcontroller — on the Game’s 25th Birthday | Gareth Halfacree, hackster.io

Jun 24, 2021

Deploying deep learning models on the edge with Kenning

Jun 24, 2021

Intel Will Offer SiFive RISC-V CPUs on 7nm, Plans Own Dev Platform | Joel Hruska, ExtremeTech

Jun 24, 2021

Bluetrum Launches RT-Thread-Based Arduino Uno-Like RISC-V Development Board, the AB32VG1 | Gareth Halfacree, hackster.io

Jun 24, 2021

Video: Arm vs RISC-V-What You Need to Know | Gary Explains

Jun 24, 2021

EPI Chair Jean-Marc Denis Shares Vision for Future Supercomputers | Tiffany Trader

Jun 24, 2021

Intel to Adopt SiFive’s New High-Performance P550 RISC-V Cores With 7nm Platform | Paul Alcorn, Tom’s Hardware

Jun 23, 2021

NEORV32: a customizable RISC-V SoC #RISCV #FPGA

Jun 23, 2021

SiFive Boasts of the “Highest-Performance RISC-V Processor” in Its New P550 Design | Gareth Halfacree, hackster.io

Jun 23, 2021

Canonical enables Ubuntu on SiFive’s HiFive RISC-V boards

Jun 23, 2021

Extended development tools performance capabilities for Andes RISC-V cores

Jun 23, 2021

IAR Systems extends development tools performance capabilities for Andes RISC-V cores

Jun 22, 2021

Intel to Adopt SiFive’s New High-Performance P550 RISC-V Cores With 7nm Platform | Paul Alcorn, Tom’s Hardware

Jun 22, 2021

Codasip Announces A71X RISC-V Application Core with Dual-Issue Capability

Jun 22, 2021

Segger and Codasip Announce Cooperation on RISC-V

Jun 22, 2021

SiFive aims to challenge Arm with new tech, pairs with Intel on effort | Stephen Nellis, Reuters

Jun 22, 2021

Life in a Formal Verification Lane | Shinavi Shah, SemiWiki.com

Jun 22, 2021

Video: RISC-V vs x86 – History and Key Differences Explained

Jun 22, 2021

SiFive’s brand-new P550 is one of the world’s fastest RISC-V CPUs | Jim Salter, arsTechnica

Jun 21, 2021

Argonne, ORNL Award Codeplay Contract to Strengthen SYCL Support for AMD GPUs | HPCwire

Jun 21, 2021

SEGGER and Codasip Announce Cooperation on RISC-V

Jun 21, 2021

Video: RISC-V RV32I Assembly – Multiplication | Maven Silicon

Jun 21, 2021

Video: RISC-V Custom PC Build

Jun 21, 2021

Video: The Future of Linux on RISC-V

Jun 21, 2021

Video: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

Jun 21, 2021

Alibaba’s chip unit realizes key breakthroughs with Xuantie CPU | Global Times

Jun 21, 2021

RISC-V could be coming to supercomputers (eventually) | Brad Linder, liliputing

Jun 21, 2021

Video: RISC V & consumer technology with Ted Marena

Jun 21, 2021

Video: WCAE ’21 – Paper 8: Digital Design and RISC-V Computer Architecture Textbook:Harris & Harris

Jun 21, 2021

European Processor Initiative Tapes Out Their First RISC-V Test Chip | Robin Mitchell, ElectroPages

Jun 21, 2021

RISC-V boffins lay out a plan for bringing the architecture to high-performance computing | Gareth Halfacree, The Register

Jun 21, 2021

Embedded Programming and IoT – Memory Management Criticality!

Jun 21, 2021

Cortus Develops Next Generation High-End RISC-V CPU Core for HPC

Jun 21, 2021

RISC-V Evolving to Address Supercomputers and AI | Anton Shilov, Tom’s Hardware

Jun 20, 2021

Video: Let’s build a custom RISCV64 Unmatched Linux kernel! | More Bits Inside, Rene Rebe

Jun 20, 2021

Rebooting Imagination: A Heterogeneous Compute Strategy | Nitin Dahad, EE Times

Jun 18, 2021

Advanced Computing Systems Research Project Seeks Collaboration | Tactical Computing Labs

Jun 17, 2021

Video:

Jun 16, 2021

The 10 Hottest Semiconductor Startups Of 2021 (So Far) | Dylan Martin, CRN

Jun 16, 2021

Video: The Future of Linux on RISC-V

Jun 14, 2021

Andrew “bunnie” Huang’s Reconfigurable RISC-V Precursor Gets a True Random Number Generation Upgrade | Gareth Halfacree, hackster.io

Jun 14, 2021

Cortus Hopes to Stake Early RISC-V HPC Claim | Nicole Hemsoth, The Next Platform

Jun 10, 2021

RISC-V Functional Safety Processor IP Core introduced by Fraunhofer IPMS and CAST | EE Journal

Jun 9, 2021

Embedded Executive: James Prior, Head of Global Communications, SiFive | Embedded Computing Design

Jun 9, 2021

AndesBoardFarm Enables SoC Designers to Explore RISC-V Processors in Online FPGA Board Collection | Andes Technology

Jun 9, 2021

RISC-V SIG-HPC Enabling RISC-V in HPC, Supercomputers to the Edge, and Emerging AI/ML/DL HPC Workloads

Jun 8, 2021

RISC-V FPGA SoM module starts production | eeNews Europe, Nick Flaherty

Jun 8, 2021

RISC-V Functional Safety Processor IP Core introduced by Fraunhofer IPMS and CAST | Fraunhofer

Jun 8, 2021

AI is RISC-V’S Trojan Horse into the Datacenter | The Next Platform

Jun 8, 2021

China’s ISCAS to build 2,000 RISC-V laptops by the end of 2022 as nation seeks to cut reliance on Arm, Intel chips | The Register

Jun 8, 2021

M100PFS SoM with Microchip’s PolarFire SoC FPGA Goes into Series Production

Jun 7, 2021

As Linux Foundation’s Zephyr Project Turns Five, Addressing Constrained Device Challenges is More Important Than Ever | IoT Evolution, Arti Loftus

Jun 7, 2021

RISC-V RV32I RTL Architecture | Maven Silicon

Jun 4, 2021

Alibaba Future-Proofing Cloud OS, Will Support Multiple Architectures | WebProNews, Matt Milano

Jun 4, 2021

The Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10

Jun 3, 2021

Huawei Release Their First RISC-V Development System – Hi3861 | electropages

Jun 3, 2021

Antmicro Open Source Portal launched

Jun 2, 2021

TII’s Secure Systems Research Centre Joins RISC-V International

Jun 2, 2021

PUFsecurity and Andes Technology Cooperate to Integrate Crypto Coprocessor PUFiot into RISC-V AIoT Security Platform

Jun 2, 2021

European supercomputer test chip tapes out | eeNews, Peter Clarke

Jun 2, 2021

VIDEO: TII’s Secure Systems Research Centre Joins RISC-V International | ATRC

Jun 1, 2021

Technology Innovation Institute’s Centre Joins RISC-V International | Faizan Hashmi

Jun 1, 2021

HiFive ISS | UKRocketry

Jun 1, 2021

Continuing Challenges For Open-Source Verification | BRIAN BAILEY, Semiconductor Engineering

Jun 1, 2021

EPI EPAC1.0 RISC-V Test Chip Taped-out | Design & Reuse

Jun 1, 2021

European Processor Initiative Announces EPAC1.0 RISC-V Test Chip Taped-out | HPCWire

Jun 1, 2021

VIDEO: RISC-V MYTH Workshop Promo video – 2 | VLSI System Design

Jun 1, 2021

VIDEO: Keynote Session: Hypervisor Extensions in RISC-V – Robert Eshleman, Vates SAS | The Xen Project

May 31, 2021

SEGGER’s emRun Runtime Library Licensed by SiFive for Superior Code Size and Performance Improvements | Design & Reuse

May 30, 2021

RISC-V 2021 中国峰会同地举办(co-located)活动预告

May 28, 2021

Are we seeing the takeover from RISC-V? | Electropages, Robin Mitchell

May 28, 2021

Alibaba is making its cloud OS compatible with multiple chip architectures | TechCrunch, Rita Liao

May 28, 2021

New Open Source Contributor Model: RISC-V Development Partners

May 28, 2021

首届RISC-V中国峰会即将举行汇集最新技术和学术成果

May 27, 2021

VIDEO: DVCon 2021 case study on RISC-V Verification with NVIDIA Networking and Imperas Software

May 25, 2021

Build a RISC-V CPU From Scratch | Filip Szkandera

May 21, 2021

Domain-Specific Accelerators | Codasip

May 21, 2021

Nezha RISC-V Linux SBC launched for $99 and up | JEAN-LUC AUFRANC, CNX Software

May 21, 2021

HiFive Unmatched RISC-V computer board is now shipping | Brad Linder, liliputing

May 21, 2021

Low Cost Raspberry Pi Alternative RISC-V Board Starts Crowdfunding | Ian Evenden, Tom’s Hardware

May 21, 2021

VIDEO: Meet the Latest Wireless Member of the DARWIN Family — Maxim Integrated and Mouser Electronics | EE Journal

May 21, 2021

VIDEO: OSSG – Introduction to the Open Source in Space evening | British Computer Society Open Source Specialists

May 19, 2021

VIDEO: RISC-V RV32I RTL Architecture | Maven Silicon

May 17, 2021

Run Linux on BeagleV Starlight in Renode | Antmicro

May 16, 2021

VIDEO: BeagleV RISC-V Computer (Beta) | Leon Anavi

May 15, 2021

VIDEO: GigaDevice RISC-V / GD32VF103 Nuclei Studio – getting started | Tam Hanna

May 14, 2021

PicoCom tapes out multicore RISC-V OpenRAN chip for ORANIC board | eeNews Europe, Nick Flaherty

May 14, 2021

VIDEO: RISC-V: The Lowest Layer of the Cloud-Native Landscape – Daniel Mangum & Carlos Eduardo de Paula

May 14, 2021

RISC-V中国峰会议程公开（非最终版本）

May 14, 2021

Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!

May 13, 2021

RISC-V RV32I Instructions Format | Maven Silicon

May 12, 2021

Antmicro Develops RISC-V SoM | electropages, Robin Mitchell

May 12, 2021

What is RISC-V and Why is it Important? | ICS, Jeff Tranter

May 12, 2021

How does RISC-V fit into automotive systems? | EE World, Jeff Shepard

May 12, 2021

Five tips for writing RISC-V assembly code #RISCV | Stephen Marz

May 11, 2021

KubeCon EU: The Case for Bare Metal | B. Cameron Gain, The New StackKubern

May 11, 2021

Dialog Semiconductor Selected as SiFive Preferred Power Management Partner for RISC-V Development Platforms | Dialog Semiconductor

May 10, 2021

RISC-V国际基金会现已登陆B站（哔哩哔哩）

May 10, 2021

Standards, Open Source, And Tools | Semiconductor Engineering, Brian Bailey

May 7, 2021

Run Linux on BeagleV Starlight in Renode | Antmicro

May 5, 2021

Video: (EN) Accelerating RISC V AI and IoT Development with Andes Software Solutions | Andes Technology

May 5, 2021

RISC-V International and seL4 Foundation Announce New Security Milestone

May 5, 2021

seL4 on RISC-V Verified to Binary Code

May 5, 2021

全球首款RISC-V DSP即将量产[1]

May 4, 2021

Video: aicas and SiFive Demo on RISC-V Board

May 4, 2021

Video: The RISC-V Online Tutor | British Computer Society Open Source Specialists

May 3, 2021

The world’s first DSP based on RISC-V ISA is about to be mass-produced

May 2, 2021

Video: MPU6050 Gyro + Accelerometer Sensor Demo using VEGA Processor [ RISC-V ISA]

May 2, 2021

Allwinner D1 RISC-V processor SDK & Documentation | JEAN-LUC AUFRANC, CNX Software

Apr 30, 2021

Linux-driven RISC-V module can plug into Raspberry Pi CM4 cluster carrier | Eric Brown, LinuxGizmos.com

Apr 29, 2021

SiFive and Samsung Foundry Extend Partnership to Accelerate AI SoC Development

Apr 29, 2021

RISC-V International Offers Academics, Individuals Free Development Boards with Up to 16GB of RAM | Gareth Halfacree, hackster.io

Apr 29, 2021

Video: Enabling OpenCL and SYCL for RISC-V Processors

Apr 29, 2021

New MPW-TWO Program Will Provide Fabrication For Fully Open Source Projects | Rob Mains, CHIPS Alliance

Apr 29, 2021

Antmicro’s ARV RISC-V SoM announced | Ant Micro

Apr 29, 2021

Video: Getting Started with IAR Embedded Workbench for RISC-V

Apr 29, 2021

RISC-V International Welcomes Chengwei Capital as a Premier Member

Apr 28, 2021

Filip Szkandera’s Pineapple ONE Is a RISC-V Computer Built Entirely From Discrete Logic Components | Gareth Halfacree, hackster.io

Apr 28, 2021

Embedded Executive: Mark Himelstein, CTO, RISC-V | Rich Nass, Embedded Computing DesignMark

Apr 28, 2021

Adding Value To Open-Source RISC-V Cores With Verification | Lee Moore, Semiconductor Engineering

Apr 28, 2021

Goings-on in the FuseSoC project and other Open Source Silicon related news | Olof Kindgren

Apr 28, 2021

Video: neXt Curve Webcast: RISC V – Ready or Not?

Apr 28, 2021

RISC-V Developer Boards to drive innovation

Apr 27, 2021

New Methodologies Create New Opportunities | Brian Bailey, Semiconductor Engineering

Apr 27, 2021

Video: PULSE Sensor Demo using VEGA Processor [ RISC-V ISA] | VEGA Processors

Apr 27, 2021

Video: New Online Courses For RISC-V | Linux Foundation

Apr 27, 2021

Pineapple ONE 32 bit RISC-V homemade CPU | filip.szkandera

Apr 27, 2021

Renode 1.12 release – new platforms, sensors and debugging features | Antmicro

Apr 25, 2021

Memory Availability Comparison between ESP32 and ESP32-C3 | Amey Inamdar: The ESP Journal

Apr 25, 2021

Video: 16X4 LCD Display Demo using VEGA Processor [ RISC-V ISA] | VEGA Processors

Apr 24, 2021

AI-Thinker introduces 5 ESP32-C3 modules pin compatible with ESP8266 & ESP32 modules | Jean-Luc Aufranc, CNX Soft

Apr 24, 2021

Video: RISC V Chip Testing Demo | Nanoelectronics and Computing Research Laboratory

Apr 23, 2021

New Online Courses For RISC-V | The Linux Foundation

Apr 23, 2021

Andes Announces the New Upgrade of AndeSight™ IDE v5.0: a comprehensive software solution to accelerate RISC-V AI and IoT developments | Globe Newswire

Apr 23, 2021

Video: GNOME OS on RISC-V |

Apr 23, 2021

Tenstorrent Selects SiFive Intelligence X280 for Next-Generation AI Processors

Apr 23, 2021

RISC-V Forum Security

Apr 23, 2021

Video: De-RISC project

Apr 22, 2021

How a National Effort Could Help End the Chip Shortage | Sascha Brodsky, Lifewire

Apr 22, 2021

RISC-V Targets Data Centers | Ann Steffora Mutschler, Semiconductor Engineering

Apr 22, 2021

RISC-V Targets Data Centers | ANN STEFFORA MUTSCHLER, Semiconductor Engineering

Apr 22, 2021

Jim Keller-Led Tenstorrent Licenses RISC-V for AI | Anton Shilov, Tom’s Hardware

Apr 22, 2021

What is the RISC-V ecosystem? | Jeff Shepard, EE World

Apr 22, 2021

Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications

Apr 22, 2021

Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications

Apr 21, 2021

RISC-V User space access Oops | Ben Dooks, Codethink

Apr 21, 2021

Getting Started with BeagleV™ – StarLight | Seeed

Apr 21, 2021

RISC-V User space access Oops | Ben Dooks, Codethink

Apr 21, 2021

Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform | Journal of Systems Architecture

Apr 21, 2021

RISC-V RV32I Instructions Format | Maven Silicon

Apr 21, 2021

Loongson promises self-reliance with new architecture | Stewart Randall, technode

Apr 20, 2021

Video: An easy-to-use Linux-compatible RISC-V personal computer on an FPGA starter board

Apr 20, 2021

RISC-V ZCE Extension | British Computer Society Open Source Specialists

Apr 20, 2021

Using eFPGA core for CPU ISA extension, reconfigurability | IMEN BAILI, EDN

Apr 20, 2021

CAES Gaisler Signs Contract with the European Space Agency for New Advanced Space Processor | Design & Reuse

Apr 19, 2021

Bugs: A verification engineer’s dream, a designer’s nightmare

Apr 19, 2021

BSC Working Towards First Completely Open Source European Full-Stack Ecosystem Based on New RISC-V CPU | HPCWire

Apr 17, 2021

Loongson unveils LoongArch CPU instruction set architecture for processors made in China | JEAN-LUC AUFRANC, CNX Software

Apr 16, 2021

Week In Review: Auto, Security, Pervasive Computing | SUSAN RAMBO, Semiconductor Engineering

Apr 16, 2021

Inclusivity in Open Source: Inclusivity for LGBTQ | Rob Knight, CTO, Enterprise Cloud Products at SUSE

Apr 16, 2021

Stepping into the lime light and the heat lamp – ten thoughts on putting yourself into the spotlight | Calista Redmond

Apr 16, 2021

国产芯片四大件之：全球首款RISC-V DSP即将量产

Apr 16, 2021

Silex Insight and Andes Technology Extend Strategic Partnership to Deliver Flexible and Scalable Root-of-Trust Security IP Solution | Electronics Engineering

Apr 15, 2021

China finalizes work on proprietary “Loong Arch” CPU instruction set that does not conflict with foreign CPU patents | Notebook Check, Bogdan Solca

Apr 15, 2021

InspireSemi Secures Two Customer Agreements, Including Pre-Orders, for its Second-Generation Compute Accelerator for Blockchain, HPC and AI Applications | Inspire Semiconductor, Cision PR Newswire

Apr 15, 2021

Morpheus Turns a CPU Into a Rubik’s Cube to Defeat Hackers | Samuel K. Moore, IEEE Spectrum

Apr 15, 2021

Allwinner’s RISC-V D1 Chip, Single-Board Computer Leak Ahead of Next Week’s Launch Announcement | Gareth Halfacree, hackster.io

Apr 15, 2021

What Is RISC-V? | elektor mag.

Apr 15, 2021

Silex Insight and Andes Technology Extend Strategic Partnership to Deliver Flexible and Scalable Root-of-Trust Security IP Solution

Apr 15, 2021

SiFive FU740 PCIe Support Queued Ahead Of Linux 5.13 | Michael Larabel, phoronix

Apr 13, 2021

RISC-V Raspberry Pi Alternative Edges Closer to Release | Ian Evenden, Toms Hardware

Apr 13, 2021

Espressif’s ESP32-C6 brings the next generation wireless connectivity | Open Cloudware

Apr 13, 2021

SiFive Tapes Out Their First 5nm RISC-V Processor Core | Michael Larabel

Apr 13, 2021

A first look at Allwinner D1 Linux RISC-V SBC and Processor | Jean-Luc Aufranc, CNX Soft

Apr 13, 2021

Homebrew RISC-V Computer Has Beauty and Brains | Tom Nardi, Hackaday

Apr 13, 2021

Low-Cost Single-Board Computers with RISC-V Chips are Coming Soon | Brad Linder, liliputing

Apr 13, 2021

Video: The Future of RISC-V in HPC – Vadim Malenboim, Sr Field Application Engineer, SiFive Core IP

Apr 13, 2021

SiFive Tapes Out First 5nm TSMC RISC-V Chip With 7.2 Gbps HBM3 | Anton Shilov, Tom’s Hardware

Apr 12, 2021

From NIST to RISC-V: PQShield continues its leading role in international cryptography standardisation efforts for software and hardware | Dr Ali El Kaafarani

Apr 12, 2021

Building security into an AI SoC using CPU features with extensions | Marco Ciaffi, John Min, Embedded

Apr 11, 2021

ESP32-C6 WiFI 6 and Bluetooth 5 LE RISC-V SoC for IoT devices coming soon | JEAN-LUC AUFRANC (CNXSOFT)

Apr 11, 2021

New Part Day: Espressif Esp32-C6 Includes Wifi 6 and a RISC-V Core | Kerry Scharfglass, Hackaday

Apr 9, 2021

Video: Pipelining of RISC-V processor

Apr 9, 2021

Video: Stall vs. Flush in RISC-V processor

Apr 8, 2021

Xen releases a new version 4.15 after a slightly delayed development process | Simon Sharwood, APAC Editor, The Register

Apr 8, 2021

RISC-V Application to Machine Language | Maven Silicon

Apr 7, 2021

Open Source Leader Shares the Importance of Knowing and Embracing Your Strengths with Executive Kim McMahon | The Digital Executive

Apr 7, 2021

RISC-V Star Rises Among Chip Developers Worldwide | Jeremy Hsu, IEEE Spectrum

Apr 7, 2021

Efinix® Announces Expansion of High-Performance Titanium FPGA Product Line | Press Release

Apr 7, 2021

Get Ready for the Most Interesting CPU Market We’ve Seen in Decades | Joel Hruska , Extreme Tech

Apr 6, 2021

Week In Review: Design, Low Power | Jessee Allen, Semiconductor Engineering

Apr 6, 2021

DARPA adds RISC-V to its Toolbox: Defense researchers can get special access to SiFive chip designs | Katyanna Quach

Apr 6, 2021

An Ultra-Low Power RISC-V Chip and a Clever Neural Network Give This Crazyflie “Top-Notch” Autonomy | Gareth Halfacree

Apr 6, 2021

RISC-V Extension Boasts Dramatic Improvements in Ultra-Low Power IoT Wireless Signal Processing | Gareth Halfacree

Apr 6, 2021

Axiomise Unveils Formal Verification 101 Training Program | GlobeNewsWire

Apr 6, 2021

Axiomise Unveils Formal Verification 101 Training Program | Press Release

Apr 6, 2021

Video: #CSWSpring21 / RISC-V for acceleration of data-parallel workloads: from IoT to HPC

Apr 6, 2021

First Google-Sponsored MPW Shuttle Launched at SkyWater with 40 Open Source Community Submitted Designs | Press Release

Apr 5, 2021

Video: Multithreaded Application Synchronization pt. II (Mutual Exclusion Locks a’la RISC-V) | John’s Basement

Apr 5, 2021

Video: ECC3118-1: Lab on RISC-V Emulator

Apr 4, 2021

ARM vs RISC-V Vector Extensions | Erik Engheim

Apr 2, 2021

Codasip to Offer Secure Boot Solutions with Veridify Tools

Apr 1, 2021

Video: Verification and Virtual Prototyping for RISC-V Systems

Apr 1, 2021

Video: (EN) AndeSysC™ – A Flexible RISC-V Processor Model for SoC Virtual Prototyping

Apr 1, 2021

Video: Fun Hardware With RISC-V Processors

Apr 1, 2021

Geniatech DB1126 Development Board Features RV1126 SoC for AI Applications | ABHISHEK JADHAV, CNX Software

Apr 1, 2021

Open-Source Verification not as Easy as Design | John Blyler, Design News

Apr 1, 2021

SiFive and DARPA Collaborate to Bring the Power of RISC-V to Technology Innovation | Press Release

Mar 31, 2021

SiFive and DARPA Collaborate to Bring the Power of RISC-V to Technology Innovation | BusinessWire

Mar 31, 2021

Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT project

Mar 29, 2021

Opening Up New Design Possibilities with OmniXtend

Mar 29, 2021

NASA Joins Forces with Small Business Team | Tactical Computing Labs

Mar 29, 2021

Imperas releases free ISS for RISCV-V CORE-V developers in the OpenHW ecosystem | Imperas

Mar 29, 2021

Geniatech DB1126 development board features RV1126 SoC for AI applications | ABHISHEK JADHAV, CNX-Software

Mar 29, 2021

Open-Source Verification not as Easy as Design | John Blyler, Design News

Mar 29, 2021

What Does RISC-V Stand For? | Semiconductor Engineering, Roddy Urquhart

Mar 27, 2021

Fun Hardware With RISC-V Processors | TWiT Tech Podcast Network

Mar 26, 2021

Video: Intel to Make ARM & RISC-V Chips!!! | Gary Explains

Mar 26, 2021

Video: MAX30102 Pulse Oximeter and Heart Rate Sensor Demo using VEGA Processor [ RISC-V ISA]

Mar 26, 2021

RISC-V XIP Support Queued Ahead Of Linux 5.13 To “eXecute In Place” | Michael Larabel

Mar 26, 2021

Valtrix and Codasip Cooperate on Verification of RISC-V Systems

Mar 26, 2021

In $20bn push, Intel hopes to make US chip-making great again | Aljazeera

Mar 26, 2021

Verification In The Open Source Era | Brian Bailey, Semiconductor Engineering

Mar 26, 2021

Instructor-led course now includes hands-on labs with a RISC-V based emulated development target | Behan Webster

Mar 26, 2021

ESP32-C3-DevKitM-1 RISC-V WiFI & BLE board to launch for $8, modules for $1.8+ | JEAN-LUC AUFRANC (CNXSOFT)

Mar 26, 2021

SiFive collaborates with new Intel Foundry Services to enable innovative new RISC-V computing platforms | Sifive Blog – Patrick Little, President & CEO, SiFive

Mar 26, 2021

IAM949- CEO Expands and Engages Company’s Stakeholders | Podcast Interview with Calista Redmond

Mar 25, 2021

AndeSysC™ – A Flexible RISC-V Processor Model for SoC Virtual Prototyping | Andes Technology

Mar 25, 2021

The Cybersecurity Pincushion and a Myriad of Tiny Threat Points

Mar 24, 2021

Mitacs and OpenHW Group partner on $22.5M first-of-its-kind open-source research program

Mar 24, 2021

SiFive collaborates with new Intel Foundry Services to enable innovative new RISC-V computing platforms | Patrick Little, SiFive

Mar 24, 2021

WISeKey $WKEY Partners with Cortus to Secure Automated Vehicles Capable of Controlling All Aspects of Driving Without Human Intervention

Mar 24, 2021

Valtrix and Codasip Cooperate on Verification of RISC-V Systems | Valtrix Technologies

Mar 24, 2021

CHIPS Alliance and RISC-V International Invite the RISC-V Community to Participate in Updating a New Unified Memory Architecture Standard

Mar 24, 2021

A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing | Semiconductor Engineering

Mar 23, 2021

Intel’s tilt to foundry opens a door to upstart RISC-V technology | Tiernan Ray, ZDNet

Mar 23, 2021

Efinix FPGAs with Sammy Cheung | The Amp Hour Electronics Podcast

Mar 23, 2021

Made in Thailand CorgiDude RISC-V AI board aims to teach machine learning | Jean-Luc Aufranc (CNXSOFT)

Mar 22, 2021

Check out the new RISC-V Careers page and RISC-V Mentorship program!

Mar 22, 2021

Formal Verification Keystore | Dr. Jaap Boender, Formal Verification Engineer at HENSOLDT Cyber

Mar 22, 2021

SiFive, ArchiTek Announce High-Efficiency Sub-1W Edge AI Processor, the AiOnIc | Gareth Halfacree, hackster.io

Mar 19, 2021

Video: LeaRnV: a RISC-V based Embedded System Design Framework for Education and Research Development | TIMA Laboratory

Mar 19, 2021

Formal Verification | Dr. Jacob Boender, Formal Verification Engineer at HENSOLDT Cyber GmbH

Mar 19, 2021

FOSSi Fever 2020

Mar 18, 2021

Video: RISC-V Application to Machine Language | Maven Silicon

Mar 18, 2021

Video: Automatic end-to-end formal verification of RISC-V processors | Axiomise Formal Verification Channel

Mar 18, 2021

Why, and how, we’ll all be making our own computer chips in the future… | Rob Taylor

Mar 18, 2021

Is RISC-V China’s Semiconductor Salvation? | Tobias Mann

Mar 18, 2021

Enabling RISC-V Based System Development | Sandeep Nasa and Sagar Thakran, Logic Fruit Technologies

Mar 18, 2021

SiFive and ArchiTek Enable Secure, Private, Flexible Edge AI Computing With AiOnIc® Processor | SiFive

Mar 17, 2021

K210 AI Accelerator a Compact Raspberry Pi HAT for Computer Vision Applications | Saumitra Jagdale

Mar 17, 2021

RISC-V Security Forum 2021 – Schedule Announced!

Mar 17, 2021

Using TL-Verilog for FPGAs | Shivani Shah

Mar 17, 2021

3 RISC-V Forums Scheduled | insideHPC

Mar 16, 2021

Imperas’ RV32/64K Crypto Architectural Validation Test Suites Now Included in RISC-V Verification Ecosystem | Chad Cox Embedded Computing Design

Mar 16, 2021

DARPA pitted 500+ hackers against this computer chip. The chip won. | Gabe Cherry Michigan Engineering

Mar 16, 2021

Ron Black Joins Codasip as Executive Chairman

Mar 15, 2021

An Insider’s View Of Verifying Custom RISC-V Processor Cores | Shubhodeep Roy Chodhury, Semiconductor Engineering

Mar 15, 2021

Enabling Edge AI Vision with RISC-V and a Silicon Platform | Tom Simon

Mar 15, 2021

MIPS, China’s Loongson CPU Are Both Going All-in on RISC-V | Joel Hruska

Mar 12, 2021

Video: PineTalk episode 4: GPU-o-Rama | Pine64

Mar 12, 2021

Home News Hackers hack at unhackable new chip for three months. Chip remains unhacked | Dave James, PC Gamer

Mar 12, 2021

Xen and the RISC-V Hypervisor Extension

Mar 12, 2021

7 Things You Probably Do Not Know about De-RISC PROJECT

Mar 9, 2021

Growing an Open and Inclusive Community

Mar 9, 2021

如何利用RISC-V SoC同时处理5G与AI工作负载？| How to use RISC-V SoC to handle 5G and AI workloads at the same time? | Sally Ward-Foxton (Chinese)

Mar 9, 2021

OpenHW Group and Mitacs announce OpenHW Accelerate | OpenHW Group

Mar 9, 2021

Bluetrum AB32VG1 board features AB5301A Bluetooth RISC-V MCU, runs RT-Thread RTOS | Jean-Luc Aufran, CNX Software

Mar 9, 2021

CODASIP ANNOUNCES COMMERCIAL ADD-ONS TO SWERV CORE® EH1 | Codasip

Mar 9, 2021

EU Seeks to Double Share of World Chip Market by 2030 in ‘Digital Sovereignty’ Drive | Daniel Michaels and Stu Woo, WSJ

Mar 9, 2021

Codasip Announces Commercial Add-Ons to SweRV Core EH1

Mar 8, 2021

Wait, What? MIPS Becomes RISC-V Classic CPU Company Exits Bankruptcy, Throws in the Towel |Jim Turley, Electronics Engineering Journal

Mar 5, 2021

Open Source Processors for Next-Generation Storage Controllers | Eye on Tech

Mar 5, 2021

Enter at Your Own RISC! – Intermezzo mit RISC-V und dem ESP32-C3 | Intermezzo with RISC-V and the ESP32-C3 | Michael Stal, heise (German)

Mar 5, 2021

RISC-V Execution Stages | Maven Silicon

Mar 4, 2021

Matthew Venn talks with Olof Kindgren about his involvement in FOSSi, Open Source EDA and his many award winning achievements. | YosysHQ

Mar 4, 2021

IAR Systems announces availability of RISC-V development tools with certification for IEC 61508 and ISO 26262 | PR Newswire

Mar 4, 2021

GitHub Actions self-hosted runners, Build Event Server and Google Cloud | Antmicro

Mar 3, 2021

Free Courses Now Available to Learn ‘RISC-V’ by The Linux Foundation & RISC-V International | Sourav Rudra, It’s Foss News

Mar 2, 2021

RISC-V Fast Tracks Simpler Extensions | eeJournal, Jim Turley

Mar 2, 2021

Linux Foundation and RISC-V International launch free RISC-V training classes | Steven J. Vaughan-Nichols, ZDNet

Mar 2, 2021

Learn About the RISC-V ISA with Two Free Training Courses from The Linux Foundation and RISC-V International

Mar 1, 2021

Lattice Expands mVision Solutions Stack Capabilities | businesswire

Mar 1, 2021

Imperas Donates Latest RV32/64K Crypto (scalar) Architectural Validation Test Suites to the RISC-V Verification Ecosystem | imperas

Mar 1, 2021

RISC-V Is On a Roll. Is It Ready to Take a Seat Alongside Intel, AMD, and Arm? | Data Center Knowledge, Christine Hall

Mar 1, 2021

RISC-V Star Rising from the East – Introducing StarFive

Mar 1, 2021

RISC-V growth and successes in technology and industry : embedded world 2021

Feb 27, 2021

EXPLORING THE OPEN SOURCE THAT REALLY GOES INTO A RISC-V CHIP | Hackaday, Jenny List

Feb 26, 2021

WHAT IS CODAL? | Codasip

Feb 26, 2021

Using Renode for education, research and demonstration | Antmicro

Feb 26, 2021

RISC-V With Linux 5.12 Begins Mainlining SiFive’s FU740 Support, NUMA | phoronix, Michael Larabel

Feb 26, 2021

RISC-V International Announces Inception of Fast Track Architecture Extension Process | Embedded Computing Design, Perry Cohen

Feb 26, 2021

Wanxiang Blockchain Forms RISC-V International Blockchain SIG with Ecosystem Partners | DarkReading

Feb 25, 2021

Wanxiang Blockchain Forms RISC-V International Blockchain SIG with Ecosystem Partners | Wanxiang Blockchain

Feb 25, 2021

Imperas reunites with SystemVerilog Co-Founders at DVCon 2021 | Imperas

Feb 25, 2021

RISC-V: è la miglior risorsa per diventare indipendenti dalle CPU americane | RISC-V: is the best resource for becoming independent of American CPUs | tecnoandroid, Alexander Pope (Italian)

Feb 25, 2021

The Single Greatest Opportunity For Open Source | Semiconductor Engineering, Brian Bailey

Feb 25, 2021

Customizing An Existing RISC-V Processor | Semiconductor Engineering, Roddy Urquhart

Feb 25, 2021

Startup Plots Base-Station-on-a-Chip That Combines 5G and AI | Electronic Design, James Morra

Feb 25, 2021

aitos.io builds important cornerstones by joining RISC-V International and forms new Blockchain SIG with ecosystem partners | aitos.io

Feb 24, 2021

万向区块链携手生态合作伙伴，联合发起成立RISC-V基金会“区块链行业工作组” | Wanxiang Blockchain and ecological partners jointly initiated the establishment of the RISC-V Foundation “Blockchain Industry Working Group” | Wanxiang Blockchain (Chinese)

Feb 24, 2021

Andes Technology and Rambus Collaborate to offer Secure Solution for MCU and IoT Applications | Global News Wire

Feb 24, 2021

Tianyihexin Licenses Codasip L30 for Powering Intelligent Wearable Device Solutions | Codasip

Feb 24, 2021

Imagination’s GPU selected for Beagle V RISC-V AI single board computer | Neil Tyler, New Electronics

Feb 24, 2021

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension | Design & Resuse

Feb 24, 2021

Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning | British Computer Society Open Source

Feb 23, 2021

OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP

Feb 23, 2021

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension

Feb 21, 2021

Smart public transportation system using VEGA Processor [ RISC-V ISA] | VEGA Processors

Feb 19, 2021

LeaRnV: a RISC-V based Embedded System Design Framework for Education and Research Development | TIMA Laboratory

Feb 18, 2021

PINECIL – Soldering Iron w/a RISC-V Processor! | Level1Techs

Feb 16, 2021

Using gem5 and RISC-V simulation to enable the optimization of heterogeneous architectures | HiPEAC

Feb 16, 2021

Webinar: RISC-V Custom Instructions – Design, Development and Deployment, Feb 24 2021 | Imperas

Feb 15, 2021

RISC-V Summit 2020

Feb 15, 2021

Pine64 introduces Quartz64 single-board PC with RK3566 processor, teases upcoming RISC-V board | Brad Linder, Liliputing

Feb 14, 2021

RISC-V: How much is open source? Featuring the new ESP32-C3 | Andreas Spiess

Feb 12, 2021

RISC-V Becoming Less Risky with the Right Verification

Feb 12, 2021

Calista Redmond on EDACafe Bunker Broadcast

Feb 12, 2021

Developing Diosix: An open-source RISC-V bare-metal hypervisor from scratch in Rust | British Computer Society Open Source Specialists

Feb 12, 2021

Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning | British Computer Society Open Source Specialists

Feb 12, 2021

Micro Magic, Inc. Delivers Ultra Low Power 64-Bit RISC-v Core | Cision PR Newswire

Feb 11, 2021

RISC-V Awareness Webinar From Dr. Ali Ahmed and Zeeshan Rafique from UIT | Micro Electronics Research Lab -UIT

Feb 11, 2021

High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platform

Feb 11, 2021

CUSTOMIZING AN EXISTING RISC-V PROCESSOR | Codasip

Feb 10, 2021

Shakti Open Source Processor Development Ecosystem

Feb 10, 2021

RISC-V台湾联盟 – RISC-V Taiwan Alliance

Feb 9, 2021

A Look Back At 2020: Another Strong Year Of Growth For Andes Despite The Pandemic | Andes Technology

Feb 8, 2021

HANDS-ON: THE RISC-V ESP32-C3 WILL BE YOUR NEW ESP8266 | Elliot Williams, Hackaday

Feb 5, 2021

RISC-V: Q&A with SiFive head of global communications James Prior | Judy Lin, DIGITIMES

Feb 5, 2021

Hardware Description Language Chisel & Diplomacy Deeper dive

Feb 4, 2021

“Open ISAs (RISC-V, OpenPOWER, etc)” – Alistair Francis, Hugh Blemings (LCA 2021 Online) | linux.conf.au

Feb 4, 2021

Securing RISC-V-Based Systems | Max Maxfield, Electronic Engineering Journal

Feb 4, 2021

Electronic industry trends for 2021 | Dunstan Power, newelectronics

Feb 3, 2021

Precursor: Mobile, Open Hardware, RISC-V System-on-Chip (SoC) Development Kit | Tech5

Feb 3, 2021

RISC-V Processor Designs Emerge | Majeed Ahmad, EETimes

Feb 3, 2021

Can Open Source Hardware Emulate Linux? | Nitin Dahad, eeTimes

Feb 2, 2021

Formal bytes Episode 40: A fireside chat with Dr. Zvonimir Bandic | Axiomise Formal Verification Channel

Feb 2, 2021

Open Source: It’s Not Just for Software Anymore | Kevin Krewell, EETimes

Feb 2, 2021

Custom graphics extensions boost RISC-V | Nick Flaherty, eeNews Europe

Feb 1, 2021

Mouser Electronics Presents New RISC-V Resource Page | Mouser Electronics

Feb 1, 2021

Dr. Who HiFive Inventor Coding Kit

Feb 1, 2021

BeagleBoard.org BeagleV

Feb 1, 2021

SiFive HiFive Unmatched

Jan 31, 2021

“HiFive Unmatched Software and Hardware” – Keith Packard (LCA 2021 Online) | linux.conf.au

Jan 29, 2021

HOW TO CHOOSE AN ARCHITECTURE FOR A DOMAIN-SPECIFIC PROCESSOR |

Jan 29, 2021

Where to start with RISC-V

Jan 28, 2021

Entering 5G, Andes Technology’s performance this year has risen again (Chinese) | Su Jiawei, Commercial Times

Jan 27, 2021

RISC-V based SoC is 5G basestaton on a chip | Eric Brown, LinuxGizmos.com

Jan 27, 2021

RISC-V: what is it all about? | Nigel Charig, Power & Beyond

Jan 26, 2021

EdgeQ touts RISC-V chips for open RAN 5G

Jan 26, 2021

Learn Risc-V Assembly Programming – Lesson1 : For absolute beginners! | ChibiAkumas

Jan 26, 2021

Andes Technology Corp. Announces EdgeQ to Deliver Converged 5G and AI Silicon Platform with AndesCore™ RISC-V License for the 5G Open Radio Access Network | GlobeNewswire

Jan 26, 2021

New RISC-V hardware designs from 5G startup EdgeQ | Jim Salter, Ars Technica

Jan 26, 2021

64-bit CPU with RISC-V Vector Extension | Design & Reuse

Jan 25, 2021

What is RISC-V? (2021) | Learn Technology in 5 Minutes | Makerdemy

Jan 25, 2021

Imperas Leads The RISC-V Processor Verification Ecosystem | Imperas

Jan 25, 2021

RISC-V Becoming Less Risky With The Right Verification | Rob Van Blommestein, Semiconductor Engineering

Jan 25, 2021

Embedded Trends and Tech to Watch in 2021 | Shawn Prestridge, Electronic Design

Jan 22, 2021

Android 10 ported to RISC-V board powered by Alibaba T-Head XuanTie C910 Processor | Jean-Luc Aufranc, CNX Software

Jan 21, 2021

Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)

Jan 21, 2021

The Android system on RISC-V has come！| Open Chip Community

Jan 21, 2021

Android 10 ported to homegrown multi-core RISC-V system-on-chip by Alibaba biz, source code released | Matthew Hughes, The Register

Jan 20, 2021

Antmicro Joins the EC’s VEDLIoT Project to Bring Ultra-Efficient RISC-V Deep Learning to the IoT | Gareth Halfacree, hackster.io

Jan 20, 2021

RISC-V CPU Performance | Maven Silicon

Jan 19, 2021

The Future Is Now: Mark Himelstein of RISC-V On How Their Technological Innovation Will Shake Up The Tech Scene | Fotis Georgiadis, Authority Magazine

Jan 19, 2021

Formal Bytes, Episode 39: Abstraction in 7 minutes! | Axiomise Formal Verification Channel

Jan 18, 2021

SiFive Helping To Teach Kids Programming With RISC-V HiFive Inventor Coding Kit | Michael Larabel, Phoronix

Jan 18, 2021

Open Hardware: Open Source conquering processors (French) | David Feugey, Silicon.fr

Jan 15, 2021

国内RISC-V厂商赛昉科技与紫光展锐完成战略合作签约 | Domestic RISC-V manufacturer Saifang Technology and Ziguang Zhanrui have signed a strategic cooperation agreement | 163.com (Chinese)

Jan 14, 2021

Very Efficient Deep Learning in IoT project with RISC-V and Renode | Antmicro

Jan 14, 2021

What Is RISC V: Should You Even Care | Brodie Robertson

Jan 14, 2021

Andes Technology And Rafael Microelectronics Announce A Strategic Partnership To Provide High Power Efficiency Wireless IP Solutions For IoT Devices | Andes Technology

Jan 13, 2021

Move over, ARM: BeagleV is a $150 RISC-V computer designed to run Linux | Jim Salter, Ars Technica

Jan 13, 2021

CES 2021: RISC-V’s journey from experimentation to commercial processors | Majeed Ahmad, EDN

Jan 13, 2021

RISC-V Scalar Crypto| Markku-Juhani Saarinen & Ben Marshall, Real World Crypto 2021 Symposium, TheIACR

Jan 13, 2021

BeagleBoard.org® and Seeed introduces the first affordable RISC-V board designed to run Linux

Jan 13, 2021

David Patterson at GYSS 2021 – Reduced Instruction Set Computers | National Research Foundation Singapore

Jan 13, 2021

Here’s a new well-stocked RISC-V Raspberry Pi challenger | Mayank Sharma, TechRadar

Jan 12, 2021

Renode 1.11 – improved testing, RISC-V support and user experience | Zephyr Project

Jan 12, 2021

Zepp To Debut and Wow Consumers Worldwide at CES 2021 | PRNewswire, Zepp

Jan 11, 2021

Sunplus Technology Uses SiFive RISC-V Processor | 凌陽科技採用SiFive RISC-V處理器 | Digitimes (Chinese)

Jan 11, 2021

RISC-V and the future of open-source computing at CES 2021 | Engadget

Jan 9, 2021

RISC-V, a Technology That Can Change the Future of Hardware | Milagros Martinez, TekCrispy (Spanish)

Jan 8, 2021

Aiming at Smart, Efficient, and Low-Energy IoT Scenarios, “Risechip” Develops AI Chips Based on the RISC-V Architecture | Zi Yu Qing, Sohu (Chinese)

Jan 8, 2021

Why Processor? | Maven Silicon – A RISC-V Training Partner | Maven Silicon

Jan 8, 2021

Rediscovering RISC-V: Apple M1 sparks renewed interest in non-x86 architectures | Robin Harris, Storage Bits, ZDNet

Jan 8, 2021

SEGGER introduces new Open Flashloader for direct programming of any RISC-V system | SEGGER

Jan 6, 2021

Andes Technology Provides RISC-V CPU Core to SK Telecom | Andes Technology

Jan 6, 2021

28 Entrepreneurs Share Their Goals for 2021 | CB Nation

Jan 6, 2021

Let’s Make RISC-V Connected Systems Synonymous with Security

Jan 5, 2021

RISC-V Electronic Design Industry Predictions 2021 | EDACafe’

Jan 5, 2021

Chinese Startups and Venture Capitalists Bet Big on Open Source RISC-V | China Money Network

Jan 4, 2021

Axiomise joins RISC-V International | iCrowdNewswire

Jan 4, 2021

The Lost Art Of Processor Verification | Kevin McDermott, Semiconductor Engineering

Jan 1, 2021

Swedish Cobham and Spanish fentISS deepen their relationship | ArchiTecnologia

Dec 31, 2020

Welcome 2021 from Axiomise | Axiomise Formal Verification Channel

Dec 31, 2020

Enabling open source Ibex synthesis and simulation in Verilator/Yosys via UHDM/Surelog | Antmicro

Dec 31, 2020

A look back at RISC-V Development Timeline in 2020 | SEEED Studio

Dec 31, 2020

Ibex support in Verilator/Yosys via UHDM/Surelog | Antmicro

Dec 31, 2020

Year 2020 in review – Top ten posts and stats | Jean-Luc Aufranc, CNX Software

Dec 31, 2020

RISC-V Vector Instructions vs. ARM and x86 SIMD | Erik Engheim, Medium

Dec 29, 2020

4 of the Best IoT Boards for Children | Sayak Boral, IoT Tech Trends

Dec 29, 2020

2020: As The Hardware World Turns | Tom Nardy, Hackaday

Dec 29, 2020

The IoT Radar – RISC-V (Italian) | Elettronica Tech

Dec 28, 2020

2020 Put Us on the Edge of a CPU Revolution, Upscaled | Chris Schodt, Engadget

Dec 28, 2020

Esperanto AI Chip Exploits Thousands of Minions | Jim Turley, Electric Engineering Journal

Dec 26, 2020

RISC-V at OSFP LIVE event with Dr. Naveed Sherwani, Dr. Ali Ahmed and Dr. Bilal Zafar | Micro Electronics Research Lab -UIT

Dec 26, 2020

RISC-V Assembly for Beginners | Erik Engheim, Medium

Dec 23, 2020

What Brought Joy to Electronics Executives in 2020? | Maurizio Di Paolo Emilio & Anne-Françoise Pelé, EETimes Europe

Dec 23, 2020

SEGGER's J-Link OB plays crucial role in new BBC ‘HiFive Inventor’ educational kit | Segger

Dec 22, 2020

The Open Source RISC-V is Prompting Chip Technology Breakthroughs | ZDNet

Dec 22, 2020

Does ISA Ownership Matter? A Tale of Three ISAs | Roddy Urquhart

Dec 22, 2020

Baremetal RISC-V Renode – Part 1: Blinky | Zak Kohler

Dec 22, 2020

Multicore Debug Evolves To The System-Level | Ann Steffora Mutschler, Semiconductor Engineering

Dec 22, 2020

Open Source vs. Commercial RISC-V Licensing Models | Roddy Urquhart, Semiconductor Engineering

Dec 22, 2020

RISC-V Verification Challenges Spread | Ann Steffora Mutschler, Semiconductor Engineering

Dec 22, 2020

The year edge AI took off | Nick Flaherty, EE News Europe

Dec 21, 2020

HW News – NVIDIA & Reviewers, RISC-V Core Designs, 8GHz Intel CPU OC, & CPU Shortages | Gamers Nexus

Dec 21, 2020

Swiss Spin-Off to Develop RISC-V Edge AI chip | Peter Clarke, EE News Europe

Dec 20, 2020

DESK OF LADYADA – Brainwave Sunday + HiFive RISC-V Inventor Kit | Adafruit Industries

Dec 19, 2020

RISC-V-Enabled SOM Aids Embedded Development | Susan Nordyk, EDN

Dec 18, 2020

OpenRISC + RISC-V Improvements Come for Linux 5.11 | Michael Larabel, Phoronix

Dec 18, 2020

Digital Storage Projections for 2021, Part 1 | Thomas Coughlin, Forbes

Dec 17, 2020

IAR Systems enables Linux-based Continuous Integration and automated workflows for RISC-V | IAR Systems

Dec 17, 2020

Cmsemicon ANT32RV56xx is a RISC-V microcontroller for wireless charging | Jean-Luc Aufranc, CNX Software

Dec 16, 2020

Spatial : Cobham Gaisler et l’éditeur espagnol fentISS collaborent autour de l’architecture de processeur RISC-V (French) | Pierrick Arlot, L’embarqué

Dec 16, 2020

Russian microcontroller K1986BK025 based on the RISC-V processor core for smart electricity meters (Russian) | Habr

Dec 16, 2020

Micro Magic details its 1GHz RISC-V processor | Peter Clarke, ee News Europe

Dec 15, 2020

Linux 5.10 LTS release – Main changes, Arm, MIPS and RISC-V architectures | Jean-Luc Aufranc, CNX Software

Dec 15, 2020

RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDA

Dec 14, 2020

RISC-V International Annual Awards

Dec 14, 2020

ET-SoC-1 Chip with More Than 1,000 RISC-V Cores Aimed at Accelerating Machine Learning | Abhishek Jadhav, hackster.io

Dec 14, 2020

Compiling a Benchmark for RISC-V | TechTechPotato

Dec 14, 2020

RISC-V Summit 2020 showcases a growing ecosystem and a wider application spectrum | Roberto Frazzoli, EDACafe'

Dec 14, 2020

RISC-V And Marvell Technologies Advances Enable Storage Solutions | Tom Coughlin, Forbes

Dec 14, 2020

Embedded Studio for RISC-V now comes with SEGGER Linker | Neil Tyler, New Electronics

Dec 14, 2020

The Genius of RISC-V Microprocessors | Erik Engheim, Medium

Dec 13, 2020

Calista Redmond of RISC-V International Tells Us About Its Open-Source Development Model and COVID-19 | Kossi Adzo, startup.info

Dec 12, 2020

Linker Shrinks RISC-V Application Size | Nick Flaherty, eeNews Europe

Dec 11, 2020

Seagate Announces Its Own RISC-V Cores for Future Storage Controllers | Joel Hruska, Extreme Tech

Dec 11, 2020

European R&D marks milestones in steps to deliver fully European platform for space applications | Cordis

Dec 11, 2020

Cobham Gaisler and fentISS Deepen Collaboration around RISC-V | Doug Black, Inside HPC

Dec 11, 2020

Week In Review: Design, Low Power | Jesse Allen, Semiconductor Engineering

Dec 11, 2020

Green Hills adds RTOS support to portfolio of RISC-V-based SoCs | newelectronics

Dec 10, 2020

The 2020 RISC-V Summit | Paul McLellan, Cadence

Dec 10, 2020

重磅|赛昉科技发布全球性能最强的RISC-V 天枢系列处理器内核 | Heavy | Saifang Technology releases the world's most powerful RISC-V Tianshu series processor core | StarFive (Chinese)

Dec 10, 2020

Seagate, Western Digital outline progress on RISC-V designs | Carol Sliwa, SearchStorage.TechTarget.com

Dec 10, 2020

Saifang Technology releases leading performance RISC-V Tianshu processor core (Chinese) | China News Network

Dec 10, 2020

Lattice Propel Accelerates Time-to-Market for Embedded Processor-based Designs on Latest Nexus Platform FPGAs | businesswire

Dec 10, 2020

Swiss AI Chip Startup Raises Seed Funding | Sally Ward-Foxton, EE Times

Dec 10, 2020

Cobham Advanced Electronic Solutions Introduces Support for Wind River VxWorks RTOS for NOEL-V Processor | Cobham

Dec 10, 2020

Après Western Digital, Seagate conçoit à son tour ses propres cœurs de processeur RISC-V (French) | Pierrick Arlot , L'embarqué

Dec 10, 2020

RISC-V hardware & software ecosystem highlights in 2020 | CNX Software

Dec 9, 2020

Cobham Gaisler and fentISS Deepen Collaboration around RISC-V | Cobham Gaisler

Dec 9, 2020

Esperanto Technologies Appoints Jin Kim as Chief Data Scientist and VP of Software | Esperanto Technologies

Dec 9, 2020

Trap-less Virtual Interrupt for KVM on RISC-V by Siqi Zhao | KVM Forum

Dec 9, 2020

Un fabricant de disques dur est-il en train de concevoir les futures puces RISC-V de nos smartphones ? (French) | Ecran Mobile

Dec 9, 2020

Nvidia has one surprising new rival: the world's largest storage vendor | Barclay Ballard, TechRadar

Dec 9, 2020

Seagate Develops Own RISC-V Cores for Storage Controllers | Anton Shilov, Tom's Hardware

Dec 9, 2020

Imperas releases new RISC-V Processor Verification IP to drive RISC-V adoption forward with a flexible methodology for all SoC adopters | Imperas

Dec 9, 2020

Seagate develops RISC-V based processor for faster & secure HDDs | Raunak Saha, TechnoSports

Dec 9, 2020

Tech Snippet #11: So, What Exactly is RISV V? | TechReportArticles

Dec 8, 2020

CHIPS Alliance to Collaborate with RISC-V to Standardize an Open Unified Memory Leveraging OmniXtend | CHIPS Alliance

Dec 8, 2020

Esperanto Unveils ML Chip with Nearly 1,100 RISC-V Cores | Oliver Peckham, HPC Wire

Dec 8, 2020

Codasip announces RISC-V processor cores providing multi-core and SIMD capabilities | new electronics

Dec 8, 2020

Nucleus RTOS enabling RISC V for Edge and Smart Devices | Mentor Embedded

Dec 8, 2020

SiFive HiFive Unmatched RISC-V PC: Up for pre-order now, ships in early 2021 following a spec bump | Brad Linder, Liliputing

Dec 8, 2020

Seagate Designs RISC-V Cores to Power Data Mobility and Trustworthiness | businesswire

Dec 8, 2020

RISC-V: 1000-Kern-Beschleuniger, Server-Karte und Effizienz-Champion (German) | Heise

Dec 8, 2020

Seagate says it's designed two of its own RISC-V CPU cores – and they'll do more than just control storage drives | Chris Mellor, The Register

Dec 8, 2020

Silicon Labs selects Imperas RISC-V Reference Model for verification | Imperas

Dec 8, 2020

Spatial : Sysgo va porter son OS temps réel PikeOS sur les cœurs de processeur Leon et RISC-V de Cobham (French) | Pierrick Arlot , L'Embarqué

Dec 8, 2020

SiFive's RISC-V HiFive Unmatched Upgraded To Ship With 16GB Of RAM | Michael Larabel, Phoronix

Dec 8, 2020

Andes va coupler la technologie eFPGA du français Menta à ses cœurs de processeur RISC-V (French) | Andes Technology

Dec 8, 2020

C-DAC Selects Valtrix STING For Design Verification Of RISC-V Based Microprocessors | Valtrix Systems

Dec 8, 2020

Stream Computing Joins RISC-V International as a Premier Member

Dec 8, 2020

RISC-V International Reports Another Strong Year of Growth with New Technical Milestones, Educational Programs, RISC-V Adoption and More

Dec 7, 2020

C-DAC Selects Valtrix STING For Design Verification Of RISC-V Based Microprocessors | Cision

Dec 7, 2020

OneSpin Contributes to the OpenHW Ecosystem to Achieve Processor Integrity for the CORE-V CVE4 Open-Source RISC-V Cores | businesswire

Dec 7, 2020

Porting PikeOS to NOEL-V and LEON: SYSGO and Cobham Gaisler Extend Cooperation around RISC-V | Design & Reuse

Dec 7, 2020

Menta eFPG and Codasip Announce Technology Partnership | Codasip

Dec 7, 2020

Porting PikeOS to NOEL-V and LEON: SYSGO and Cobham Gaisler Extend Cooperation around RISC-V | Cobham

Dec 7, 2020

Menta and Andes Announce Partnership Enabling Hardware Reconfiguring for ISA Extension | Andes Technology

Dec 4, 2020

Embedded Linux "from scratch" in 45 minutes…on RISC-V | Bootlin

Dec 4, 2020

Betrusted’s Precursor and Renode – a user story | Antmicro

Dec 4, 2020

SiFive与赛昉科技携手加强以数据为中心的人工智能运算在存储领域上的应用

Dec 4, 2020

Codasip Announces Three New RISC-V Application Processor Cores Providing Multi-Core and SIMD Capability | Codasip

Dec 4, 2020

#519 – Simulating Embedded Hardware with Michael Gielda | The AMP Hour

Dec 4, 2020

New RISC-V CPU claims record breaking performance per watt | Micro Magic Inc

Dec 4, 2020

Imperas Extends free riscvOVPsimPlus Simulator for RISC-V | Imperas

Dec 4, 2020

RISC-V Summit 2020 – virtual booth, keynote session and talks | Antmicro

Dec 3, 2020

RISC-V for ultra-low power processing and AI on the edge | Jeff Shepard, Microcontroller Tips

Dec 3, 2020

Extending Torture with RISC-V 'Vector' extension | Lampro Mellon DC

Dec 3, 2020

Imperas Simulator Supports Andes Custom Extension™ to Accelerate Software Development in Domain Specific Applications | Andes Technology

Dec 3, 2020

The design of scalar AES Instruction Set Extensions for RISC-V |

Dec 2, 2020

Faster, Smaller and More Accurate Edge AI Using Deeplite and Andes Technology Software + Hardware | Andes Technology

Dec 2, 2020

Micro Magic, Inc. Delivers World’s Highest Performance/Power RISC-V Core

Dec 2, 2020

Andes RISC-V Vector Processor NX27V is Upgraded to RVV 1.0 | Andes Technology

Dec 2, 2020

64-bit RISC-V core claims 10x better CoreMarks/Watt compared to other 3-5GHz CPUs | Eric Brown, Technologic Systems

Dec 2, 2020

Esperanto Technologies to Reveal Chip with 1000+ Cores at RISC-V Summit | Esperanto Techologies

Dec 1, 2020

Espressif dévoile sa première puce-système sans fil ESP32 bâtie sur un cœur RISC-V | L'embarqué

Dec 1, 2020

Andes announces new RISC-V processors | New Electronics

Dec 1, 2020

BSC researchers develop and validate hardware components of the De-RISC platform | Barcelona Supercomputing Center

Dec 1, 2020

Semiconductor Events | Semiconductor Engineering

Dec 1, 2020

Arduino Donation Program: Making a difference in the open-source community! | Arduino

Nov 30, 2020

RISC-V, the Linux of the chip world, is starting to produce technological breakthroughs | Tiernan Ray , ZDNet

Nov 30, 2020

Andes Announces New RISC-V Processors: Superscalar 45-Series with Multi-core Support and 27-Series with Level-2 Cache Controller | Andes Technology

Nov 30, 2020

Pushing the FPGA Video Player Further | Matthew Carlson, Hackaday

Nov 30, 2020

RISC-V is growing and offers stability, scalability and security | Jeff Shepard, Microcontroller Tips

Nov 30, 2020

Espressif's ESP32-C3 Leaks as a Drop-In Pin-Compatible RISC-V Replacement for the Popular ESP8266 | Gareth Halfacree

Nov 29, 2020

Ask the Expert Session with Calista Redmond, CEO of RISC V International

Nov 29, 2020

Linux on RISC-V with Open Hardware | Drew Fustini, BeagleBoard.org Foundation

Nov 29, 2020

What is Processor Core Complexity?

Nov 28, 2020

RISC-V Project: Driving GPIO Pins

Nov 27, 2020

DeRISC Project: exclusive interview for AT | ArchiTecnologia

Nov 27, 2020

RISC-V Gets an Early, Minimal Android 10 Port Courtesy of PLCT Lab | Gareth Halfacree, AB Open

Nov 27, 2020

RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One) | Paul Dempsey, Tech Design Forum

Nov 26, 2020

IAR Embedded Workbench for RISC-V extends optimisation and trace capabilities | New Electronics

Nov 26, 2020

What is RISC-V? Origins and Forecast | Tech Design

Nov 26, 2020

Linux on RISC-V with Open Source Hardware (OSSummit Japan 2020) | Drew Fustini

Nov 25, 2020

Security Gaps In Open Source Hardware And AI | Ed Sperling, Semiconductor Engineering

Nov 25, 2020

What is Needed to Support an Operating System?

Nov 24, 2020

AdaCore Introduces GNAT Pro for the Wind River® Helix™ Virtualization Platform

Nov 24, 2020

Using AI And Bugs To Find Other Bugs | Ann Steffora Mutschler, Semiconductor Engineering

Nov 24, 2020

M1108 AI accelerator chip delivers up to 35 TOPS for high-end edge AI applications | Abhishek Jadhav, CNX Software

Nov 24, 2020

RISC-V Summit: agenda highlights | Nitin Dahad, Embedded

Nov 24, 2020

Pine64’s PINECIL RISC-V soldering iron launched for $25 | Jean-Luc Aufranc, CNX Software

Nov 24, 2020

Using AI And Bugs To Find Other Bugs | Ann Steffora Mutschler, Semiconductor Engineering

Nov 24, 2020

What Interested You In 2020 | Brian Bailey, Semiconductor Engineering

Nov 24, 2020

Renode 1.11 – improved testing, RISC-V support and user experience | Antmicro

Nov 24, 2020

Are RISC-V chips ready to compete with Arm? | Matthew Gooding, TechMonitor

Nov 23, 2020

Renode 1.11 – improved testing, RISC-V support and user experience | Antmicro

Nov 23, 2020

'Bunnie' Huang Dives Deep Into the Security of the RISC-V-Powered Precursor | Gareth Halfacree, hackster.io

Nov 23, 2020

Imperas RISCV Custom Instruction Flow Application Note (Whitepaper) | Imperas

Nov 23, 2020

Battle of the BBC boards | Nick Flaherty, eeNews Europe

Nov 23, 2020

Espressif's ESP32-C3 Leaks as a Drop-In Pin-Compatible RISC-V Replacement for the Popular ESP8266 | Gareth Halfacree, hackster.io

Nov 23, 2020

Understanding the Performance of Processor IP Cores

Nov 23, 2020

Webinar Download: Static Verification for RISC-V Cores and SoCs | Aldec

Nov 23, 2020

Webinar Download: RISC-V Design and Verification with FPGA Hardware In The Loop | Aldec

Nov 22, 2020

An Automated Scalable RISC-V Cache Coherency Verification Project | Breker Verification Systems

Nov 22, 2020

ESPRESSIF LEAKS ESP32-C3: A WIFI SOC THAT’S RISC-V AND IS ESP8266 PIN-COMPATIBLE | Jenny List, Hackaday

Nov 22, 2020

ESP32-C3 WiFi & BLE RISC-V processor is pin-to-pin compatible with ESP8266 | JEAN-LUC AUFRANC (CNXSOFT)

Nov 22, 2020

Building coreboot for RISC-V and running it in Qemu | Wojciech Niewiadomski, 3MDEB

Nov 20, 2020

SiFive Strengthens Foothold in Storage Applications for Data-Centric AI Computing | James Prior, SiFive

Nov 20, 2020

Open Source in Teaching RISC-V | British Computer Society Open Source Specialists

Nov 20, 2020

BBC Picks SiFive’s RISC-V-Powered HiFive Inventor for Doctor Who Coding Push | Gareth Halfacree, AB Open

Nov 20, 2020

OpenHW TV S01E06 – A deep dive into Formal Verification for the CORE-V CVE4 | OpenHW Group

Nov 19, 2020

Doctor Who-Themed RISC-V Board to Introduce IoT to Kids | Les Pounder, Tom's Hardware

Nov 19, 2020

BBC picks SiFive RISC-V chip for Doctor Who programming-for-kids kit – with Jodie Whittaker narrating | Chris Williams, The Register

Nov 19, 2020

博流智能IoT产品采用SiFive RISC-V嵌入式CPU Core IP | Boliu smart IoT products use SiFive RISC-V embedded CPU Core IP | StarFiveTech (Chinese)

Nov 19, 2020

SiFive Pushes Open Source RISC-V Chip Architecture Closer to Prime Time | Christine Hall, Data Center Knowledge

Nov 19, 2020

RISC-V Summit 2020 Preview | Paul McLellan, Breakfast Bytes Blog

Nov 18, 2020

IC Integrity Of Edge-Computing Processors: Meeting The Demands Of AI | Rob Van Blommestein, Semiconductor Engineering

Nov 18, 2020

Introducing Telink’s New RISC-V-Based TLSR9 Series | Telink

Nov 18, 2020

RPC DRAM support in open source DRAM controller

Nov 18, 2020

Introducing Telink’s New RISC-V-Based TLSR9 Series | Telink

Nov 18, 2020

Bouffalo Lab Standardizes on SiFive RISC-V Embedded CPU Core IP for New IoT Products | SiFive

Nov 17, 2020

Olof Kindgren: exclusive interview for AT | ArchiTechnologia

Nov 17, 2020

SiFive VIU7-256 Takes Vector Lead | Aakash Jani, The Linley Group

Nov 16, 2020

Hot Chips: Alibaba’s Ultra High-Performance Superscalar Processor – XuanTie910 | Embedded Computing Design

Nov 16, 2020

Alibaba’s Ultra High-Performance Superscalar Processor – XuanTie910 | Abhishek Jadhav, Embedded Computing Design

Nov 16, 2020

Program a Shakti RISC-V processor using Rust

Nov 16, 2020

IPFS on RISC-V | David Burela

Nov 16, 2020

First steps to European multicore RISC-V chip for space | Nick Flaherty, eeNews Europe

Nov 15, 2020

Emulating RISC-V Debian on WSL2 | David Burela

Nov 15, 2020

My New Research Project | Kian Nejadfard

Nov 13, 2020

Taking the mystery out of custom extensions in RISC-V SoC design | Embedded Staff

Nov 13, 2020

13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core

Nov 12, 2020

Apple Silicon DIY: RISC-V is Serious About It. | ExpovistaTV

Nov 12, 2020

De-RISC First Anniversary, a H2020 Project Which Will Create the First RISC-V, Fully European Platform for Space

Nov 12, 2020

De-RISC first anniversary, a H2020 project which will create the first RISC-V, fully European platform for space | Design & Reuse

Nov 12, 2020

PicoRio: the Raspberry Pi-like Small-Board Computer for RISC-V

Nov 11, 2020

RISC-V Linux Dev Board, ESP32 WT32-ETH01, Raspberry Pi DDJ-400, and More! | Electromaker

Nov 11, 2020

Efinix® Announces Trion® Titanium Tapeout at TSMC 16 nm Process Node | Efinix

Nov 10, 2020

CVA6: A Linux-Capable RISC-V CPU | Whitney Knitter, hacksterio

Nov 10, 2020

RISC-V Development board | David Burela

Nov 10, 2020

Open Source Digital Library in HPC

Nov 9, 2020

RISC-V based Allwinner chip to debut on $13 Linux hacker board | Eric Brown, LinuxGizmos.com

Nov 9, 2020

XuanTie C906 based Allwinner RISC-V processor to power $12+ Linux SBC’s

Nov 9, 2020

European Processor Initiative: Second year of activities

Nov 9, 2020

European exascale supercomputer chip project updates its roadmap | Nick Flaherty, ee News

Nov 9, 2020

Here comes the most formidable rival to the Raspberry Pi yet | Mayank Sharma, TechRadar

Nov 9, 2020

PolarBerry offers a secure PolarFire SoC | Julian Horsey, Geeky Gadgets

Nov 9, 2020

The Logic Chip RISC-V Project Reboots | Jenny List, Hackaday

Nov 9, 2020

PolarFire SoC and RISC-V

Nov 8, 2020

OPEN SOURCE PROCESSOR – RISC V could be revolutionary (video), Eli the Computer Guy

Nov 7, 2020

Smart Cameras for Non-Intrusive Vital Signals Detection, Electorinca Embedded 2020 (video)

Nov 6, 2020

Open-Source RISC-V ISA Offers More | John Blyler, Design News

Nov 6, 2020

Rebooting the LMARV-1 RISC-V project! (video) | Robert Baruch

Nov 5, 2020

Emulate RISC-V on a Raspberry Pi (video) | Gary Explains

Nov 5, 2020

Now Available from Crowd Supply: PolarBerry’s Application-Flexible System-on-Module SBC | Crowd Supply, Electronic Engineering Journal (Press Release)

Nov 4, 2020

Open Source Summit Europe: Proceedings

Nov 4, 2020

Speeding Up AI With Vector Instructions | Ann Steffora Mutschler Semiconductor Engineering

Nov 4, 2020

Valtix joins RISC-V International

Nov 3, 2020

Neulinker Licenses Codasip Bk5 And Studio For Powering Innovative AI And Blockchain Solutions

Nov 2, 2020

Telink and Andes Announce the TLSR9 SoC with RISC-V Processor | Andes Technology

Nov 2, 2020

The SiFive RISC-V software ecosystem featuring IAR Systems, Lauterbach, and more (video) | SiFive

Nov 2, 2020

Telink and Andes Announce the TLSR9 SoC with RISC-V Processor

Nov 2, 2020

SiFive shows there is life in RISC-V | Nick Farrell, Fudzilla

Nov 2, 2020

Third Workshop on RISC-V Activities – It’s the ecosystem!

Nov 1, 2020

May RISC-V Processors compete with Intel, Arm, and AMD?

Oct 31, 2020

SiFive Releases HiFive Unmatched Mini-ITX Board To Bring RISC-V Development To The Masses | Marco Chiappetta, Forbes

Oct 30, 2020

The Heart of RISC-V Software Development is Unmatched (video) | SiFive

Oct 30, 2020

Bubble Sort in Risc-V assembly (video) | Learn RISC-V

Oct 30, 2020

Engage in Unmatched RISC-V Business with SiFive | Jeremy Hellstrom, PC Perspective

Oct 30, 2020

RISC-V is trying to launch an open-hardware revolution | Christopher Schodt, Engadget

Oct 30, 2020

SiFive Unveils "the World's Fastest" RISC-V Development Board, and the Heart of Its RISC-V PC | Gareth Halfacree, hackster.io

Oct 29, 2020

SiFive’s RISC-V PC coming soon for $665 | Brad Linder, Liliputing

Oct 29, 2020

HiFive Unmatched ushers in a new era of RISC-V Linux development with a platform in a PC form factor (video) | Bits inside by René Rebe

Oct 29, 2020

The Heart of RISC-V Development is Unmatched | James Prior, SiFive

Oct 29, 2020

SiFive unveils plan for Linux PCs with RISC-V processors | Dean Takahashi, Venture Beat

Oct 29, 2020

RISC-V Global Forum 2020 Transparency Report

Oct 29, 2020

NSITEXE, Kyoto Microcomputer and Codeplay Software are bringing open standards programming to RISC-V Vector processor for HPC and AI systems

Oct 29, 2020

SiFive Is Launching The Most Compelling RISC-V Development Board Yet | Michael Larabel, Motherboards

Oct 29, 2020

Adding an Instruction to the GNU Assembler | British Computer Society

Oct 28, 2020

SiFive VIU75 Accelerates Vector Math | Abhishek Jadhav, AB Open

Oct 27, 2020

Why Universities Want RISC-V | Jim Turley, Electronic Engineering Journal

Oct 26, 2020

Understanding Non-Local Jumps (setjp/longjmp) in RISC-V Assembly

Oct 26, 2020

Member Webinar: Title: UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV

Oct 26, 2020

Member Webinar: UVM-based Verification of Custom Instructions with RISC-V Cores

Oct 26, 2020

Video: Ariel IoT SoC Development Platform Featuring Andes N25F RISC-V Core

Oct 26, 2020

Parsing RISC-V assembly | Austin Z. Henley, University of Tennessee

Oct 26, 2020

RISC-V International Announces Agenda for the Third Annual RISC-V Summit

Oct 23, 2020

Micro Magic, Inc. Unleashes World’s Fastest RISC-V Core

Oct 23, 2020

349: OPEN DOWN TO THE TRANSISTOR | Drew Fustini (@pdp7) spoke with us about building Linux, RISC-V cores, and many other things.

Oct 23, 2020

Nvidia-Arm Deal a Boon for RISC-V?

Oct 23, 2020

Video: Introduction RISC-V | Drew Fustini

Oct 22, 2020

RISC-V: What it is, and what benefits it can provide to your organization | Scott Matteson, Tech Republic

Oct 22, 2020

Video: How to run Linux on RISC-V with open hardware and open source FPGA tools | Drew Fustini

Oct 21, 2020

OneSpin Contributes Processor Integrity Solution for ZuSE-Scale4Edge Government-Funded Project to Assure Integrity of Edge Computing Processors | Business Wire, OneSpin Solutions (Press Release)

Oct 21, 2020

SiFive reminds everyone you don't always need to offload vector math | Chris Williams, The Register

Oct 21, 2020

Security Enclave IP based on RISC-V | Design and Reuse

Oct 21, 2020

IAR Systems brings functional safety tools to RISC-V with certification for IEC 61508 and ISO 26262

Oct 21, 2020

Codasip announces a New Design Center in France

Oct 20, 2020

Welcome to the RISC-V Revolution | British Computer Society Open Source Specialists (YouTube)

Oct 20, 2020

A Plan 9 C Compiler for RV32GC and RV64GC

Oct 20, 2020

CloudBEAR BM-310 RISC-V MCU core for IoT applications | ABHISHEK JADHAV

Oct 20, 2020

Deterministic Processing for Mission-Critical Applications | Linley Gwennap, Principal Analyst, The Linley Group

Oct 19, 2020

Bluespec Updates its Free RISC-V Explorer with OpenHW Group CV32E40P Cores and Ubuntu Support | Bluespec (Press Release)

Oct 17, 2020

Qinheng RISC-V Chip Three-Wire Release: Bluetooth, USB3.0, General-Purpose Single-Chip | Microcomputer EEPW News (Chinese)

Oct 16, 2020

Mergers, Acquisitions, and Free Money | Brandon Lewis and Rich Nass, Embedded Computing Design (Embedded Insiders Podcast)

Oct 15, 2020

Understanding the Basics of the RISC-V CPU – Part 1 | Abdallah Salem (YouTube)

Oct 15, 2020

RISC-V boom from edge AI says Facebook's chief AI scientist | Nick Flaherty

Oct 15, 2020

The SiFive 20G1 Update for 7-Series Core IP | Drew Barbier, Director of Product Marketing

Oct 15, 2020

SiFive/RISC-V Questions w/James Prior

Oct 15, 2020

Imperas RISC-V reference simulator and model extended for coverage analysis

Oct 14, 2020

RISC-V: Will There Be Other Open-Source Cores? | Ed Sperling, Semiconductor Engineering

Oct 12, 2020

Move fast and break things? Not so fast in embedded.

Oct 12, 2020

ERASER: Early-Stage Reliability and Security Estimation for RISC-V an Open Source Framework for Resilience/Security Evaluation and Validation in RISC-V Processors | FOSDEM, (YouTube)

Oct 10, 2020

Saifang Technology Released the World's First RISC-V Artificial Intelligence Visual Processing Platform-Jinghong 7100 | Race Fang Technology, EEPW (Chinese)

Oct 9, 2020

Linux 5.10: Reveals Big Step Forward for RISC-V | Linux Addicts (Spanish)

Oct 9, 2020

RISC-V Day Vietnam

Oct 9, 2020

Linux 5.10: Reveals Big Step Forward for RISC-V | Isaac, Linux Addicts (Spanish)

Oct 9, 2020

Introduction to the RISC-V Evening | British Computer Society Open Source Specialists (YouTube)

Oct 9, 2020

Arm and RISC-V Software Development Solution from Ashling: RiscFree™ for Arm & RISC-V | Ashling (Press Release)

Oct 8, 2020

LLVM: Quickly Finding RISC-V Code Quality Issues with Differential Analysis | lowRISC (YouTube)

Oct 8, 2020

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference | Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini and Davide Rossi, Cornell University (White Paper)

Oct 7, 2020

Think Silicon to Introduce a New Inference Micro GPU Architecture Based on RISC-V at Linley Fall Virtual Processor Conference | Think Silicon (Press Release)

Oct 6, 2020

Women In Engineering: Calista Redmond Unlocks Key For Open Source, Collaborative Engineering | Aimee Kalnoskas, EE World News Online

Oct 6, 2020

CSCE 611 Fall 2020 Lecture 10: RISC-V Microarchitecture | Jason Bakos (YouTube)

Oct 6, 2020

Product of the Week: Microchip PolarFire SoC FPGA Icicle Kit | Staff, Embedded Computing Design

Oct 6, 2020

PLS Expands Architecture Support: UDE Now Also Supports Debugging of RISC-V-based Devices and Cyclone V FPGAs | Staff, EE Journal

Oct 5, 2020

AI for Entrepreneurs #4: | Loic Lietar (GreenWaves Technologies) OpenCV AI (YouTube)

Oct 4, 2020

RISC-V, the open source chip to rival Intel and ARM | Ramalho Lima, Tecmundo (Portuguese)

Oct 4, 2020

RISC-V Deep Dive, CTO Interview | Dan Olds, Radio Free HPC

Oct 2, 2020

An Open Alternative to Intel and ARM: What Is RISC-V? | Matthew Hughes, How To Geek

Oct 2, 2020

Session Recordings from the RISC-V Virtual Global Forum _ SparkFun

Oct 2, 2020

Maven Silicon – a RISC-V Training Partner

Oct 1, 2020

Watch Bluespec CTO Demo BSV & BH for RISC-V Open Source Hardware Accelerator at International Conference on Functional Programming

Oct 1, 2020

Renesas signs deal with open source ARM competitor | By Nick Flaherty

Oct 1, 2020

RISC-V: Standing on the Shoulders of Giants

Sep 30, 2020

RISC-V Global Forum: Proceedings

Sep 30, 2020

Introduction to RISC-V and the RV32I Instructions | John’s Basement (YouTube)

Sep 30, 2020

Is RISC-V Processor Hardware or Software? | Design News

Sep 30, 2020

RISC-V: A Playground for Game-changing Design Methodologies

Sep 29, 2020

Tackling Functional Correctness, Safety, Trust and Security | Rob van Blommestein, Semiconductor Engineering

Sep 29, 2020

For Whom RISC-V Is An Alternative | Dr. Claus Kühnel, Elektronik (German)

Sep 28, 2020

PicoRio for RISC-V like Raspberry Pi for ARM!

Sep 28, 2020

RISC-V: This Is The Chip That Everyone Talks About | Rodolfo de Juana, Muy Computer Pro (Spanish)

Sep 27, 2020

Will RISC-V Be a Contender Now That Nvidia Is Buying Arm?| Dean Takahashi, VentureBeat

Sep 26, 2020

SiFive Begins Adding RISC-V "Bullet" Microarchitecture Code to LLVM | Michael Larabel, Phoronix

Sep 25, 2020

The Nvidia-Arm Deal Hasn't Boosted RISC-V. But It Soon Could. | Shakeel Hashim, Protocol

Sep 25, 2020

India Creates RISC-V-based Chip | Nick Farrell, Fudzilla

Sep 25, 2020

Great discussion on the bright future of RISC-V and work we're doing at RISC-V International | Calista Redmond with Shakeel Hashim, Protocol

Sep 24, 2020

NSITEXE selects Imperas RISC-V and Vectors Reference Model

Sep 23, 2020

RISC-V: How an Open ISA Benefits Hardware Security | Drew Fustini | Hardwear.io Webinar (YouTube)

Sep 23, 2020

Open ESP the Heterogeneous Open-Source Platform for Developing RISC-V Systems | Luca Carloni and Davide Giri, Fosdem (YouTube)

Sep 23, 2020

Libre Space Foundation Joins RISC-V International as a Community Member | Nikoletta Triantafyllopoulou, Libre Space Foundation

Sep 23, 2020

Codasip Whitepaper – Creating Domain-Specific Processors Using Custom RISC-V ISA Instructions | Codasip (White Paper)

Sep 22, 2020

The First Decade of RISC-V: A Worldwide Phenomenon | Paul McLellan, Cadence

Sep 22, 2020

Tech Insight: RISC-V | Leonard Lee, next Curve Podcast

Sep 21, 2020

SiFive's mission, journey, and the origins of RISC-V, as told by co-inventor Dr. Krste Asanovic

Sep 18, 2020

Imagination Technologies Talks About Its RISC-V Undergraduate Course | Ramish Zafar, WCCF Tech

Sep 17, 2020

RISC-V embedded variant RV32E now fully supported by SEGGER's Floating-Point library

Sep 17, 2020

RISC-V Catalyst for Change

Sep 17, 2020

SiFive Appoints Patrick Little as President and Chief Executive Officer

Sep 17, 2020

The Incredible Opportunity For SiFive | A note from SiFive President & CEO, Patrick Little

Sep 17, 2020

SiFive Readies RISC-V Desktop PC for Devs, New CPUs with Vector Extensions | Anton Shilov, Tom’s Hardware

Sep 17, 2020

Microchip Looks to Leverage RISC-V ISA | Neil Tyler, New Electronics

Sep 17, 2020

Arm Rival SiFive Says Nvidia Deal Spurs Interest in Its Technology | Stephen Nellis, Reuters

Sep 16, 2020

The Industry’s First SoC FPGA Development Kit Based on the RISC-V Instruction Set Architecture is Now Available

Sep 16, 2020

RISC-V State of the Universe| Paul McLellan, Cadence

Sep 15, 2020

Jensen Huang's defence of the Nvidia-ARM deal

Sep 15, 2020

SiFive Announces New RISC-V Processor Architecture plus Its First-Ever Desktop PC Processor in Response to Nvidia's Plans to Dominate the Server Market | Bogdan Solca, Notebook Check

Sep 15, 2020

GigaDevice Offers MCUs Based on Both RISC-V, Arm | Rich Nass, Embedded Computing Design

Sep 14, 2020

USENIX Security '20 – Donky: Domain Keys – Efficient In-Process Isolation for RISC-V and x86 | David Schrammel, USENIX (YouTube)

Sep 12, 2020

MuniHac 2020 Workshop: Christiaan Baaij – Building a RISC-V SoC | Haskell and Python TNG Technology Consulting GmbH (YouTube)

Sep 10, 2020

Building RISC-V systems on the secure seL4 microkernel in Renode – Antmicro

Sep 10, 2020

RISC-V Hypervisors Where Are We? What Next? | Anup Patel, FOSDEM (YouTube)

Sep 10, 2020

RISC-V Global Forum Report 3 – RISC-V in China; is RISC-V investable? Closing remarks | Primeur Magazine (YouTube)

Sep 9, 2020

An Interview With Tom Verbeure: Phantom Packets, RISC-V, Under The Hood Of FV | Matt Venn, Symbiotic EDA (YouTube)

Sep 9, 2020

RISC-V Global Forum Report 2 – RISC-V in Space & PicoRico, a "Raspberry Pi" based on RISC-V | Primeur Magazine (YouTube)

Sep 9, 2020

When 32 bits isn't enough — Porting Zephyr to RISCV64

Sep 8, 2020

RISC-V Global Forum – It's a wrap!

Sep 8, 2020

RISC-V Global Forum Report 1 – HPC highlights | Primeur Magazine (YouTube)

Sep 8, 2020

What Enables AI at the Edge? | Sally Ward-Foxton, EE Times

Sep 7, 2020

Avec PicoRio, l’écosystème RISC V aura bientôt son Raspberry Pi | Adrian BRANCO

Sep 6, 2020

New PicoRio SBC To Feature RISC-V Open-Source Processor | Ash Puckett, Tom’s Hardware

Sep 4, 2020

First Soc FPGA Development Kit With Hardened Risc-V Micro-Processor Subsystem | Microchip Technology (YouTube)

Sep 4, 2020

Imagination Releases RISC-V Course for Universities | Nitin Dahad

Sep 3, 2020

SiFive and Barcelona Supercomputing Center Advance Industry Adoption of RISC-V Vector Extension

Sep 3, 2020

RIOS Laboratory and Imagination Look to Grow RISC-V Ecosystem | Neil Tyler, New Electronics

Sep 3, 2020

RISC-V’s CPU Verification Challenge | EEWeb

Sep 2, 2020

Imagination Announces the First RISC-V Computer Architecture Course

Sep 2, 2020

GPU Company Imagination Technologies to Teach Students How to Design a CPU | Anton Shilov, TechRadar Pro

Sep 2, 2020

Components For Open-Source Verification | Brian Bailey Semiconductor Engineering

Sep 1, 2020

RISC-V & SoC Architecture Exploration for AI & ML Many-core Compute Arrays | John Min, Andes Technology (YouTube)

Sep 1, 2020

RISC-V Global Forum: Initiate. Innovate. Impact.

Aug 31, 2020

OpenHW open source CORE-V processor IP: a RISC-V story that leads with verification

Aug 28, 2020

Alibaba’s New 16-Core CPU Will Challenge Intel Xeon In Datacenters | Anton Shilov, TechRadar

Aug 28, 2020

RISC-V & ESP32 Based TTGO Handheld T-WATCH K210 AIoT DevKit Works with a 9V Battery | Jean-Luc Aufranc, CNX Software

Aug 27, 2020

RISC-V’s Expanding Footprint | Ed Sperling, Semiconductor Engineering

Aug 27, 2020

Is SiFive the RISC-V Standard Bearer, or a Design Mercenary? | Brandon Lewis, Embedded Computing Design

Aug 27, 2020

Logical & Arithmetic Shifting Of Binary Numbers | John, John’s Basement (YouTube)

Aug 27, 2020

Inspirational Women in STEM and Tech: “When you show up with authentic passion, vision and discipline you become the role model others want to work with” | With Calista Redmond of RISC-V International

Aug 26, 2020

The Future of American Industry Depends on Open Source Tech | Kevin Xu and Jordan Schneider, WIRED

Aug 26, 2020

LPC 2020 – RISC-V MC | Palmer Dabbelt, Linux Plumbers Conference (YouTube)

Aug 26, 2020

LPC 2020 – Testing & Fuzzing MC | Linux Plumbers Conference (YouTube)

Aug 26, 2020

LPC 2020 – Refereed Track – Day 3 | Alexandre Chartre, Linux Plumbers Conference (YouTube)

Aug 26, 2020

SEGGER Embedded Studio for RISC-V with the LDRA Tool Suite: Software Eng. for Functional Safety | LDRA (YouTube)

Aug 26, 2020

Bluespec, Inc. Releases RISC-V Explorer: A Fast, Free, Accurate Way to Evaluate RISC-V

Aug 26, 2020

Unlocking JavaScript: V8-RISCV Open Sourced

Aug 25, 2020

RISC-V Celebrates 10 Years of Open-Source ISA | Jake Hertz, All About Circuits

Aug 24, 2020

Sipeed Maix Amigo is a Portable 64-bit RISC-V AI Development Kit with Display and Cameras | Jean-Luc Aufranc, CNX-Software

Aug 23, 2020

RISC-V Software and Firmware Development in the Cloud Using OpenPiton+Ariane on Amazon F1 By David Wentzlaff and Jonathan Balkind | FOSDEM (YouTube)

Aug 23, 2020

BlackParrot An Agile Open Source RISC-V Multicore for Accelerator SoCs | Dan Petrisko, FOSDEM (YouTube)

Aug 23, 2020

Andes Technology Driving Innovations | Andes Technology Corporation (YouTube)

Aug 22, 2020

Tool Setup To Learn RISC-V Instructions (Module C, Part 1) | LearnRISC-V (YouTube)

Aug 22, 2020

Port Luajit To RISC-V Motivation, First Steps And Perspectives By Anton Kuzmin | FOSDEM (YouTube)

Aug 21, 2020

Past, Present and Future of RISC-V Open Source ISA — Andes' Perspective by Charlie Su | COSCUP 2020 By Charlie Su | COSCUP (YouTube) – Chinese

Aug 21, 2020

FOSS it all the way : FPGA tool, RISC-V and Linux by Ruinland | COSCUP 2020 | COSCUP (YouTube) – Chinese

Aug 21, 2020

Experience on porting HIGHMEM and KASAN to RISC-V Linux by Eric Lin, Nick Hu | COSCUP 2020 | Eric Lin and Nick Hu, COSCUP (YouTube) – Chinese

Aug 21, 2020

Alibaba On The Bleeding Edge Of RISC-V With XT910 | Jeffrey Burt, The Next Platform

Aug 19, 2020

India Selects RISC-V for Semiconductor Self-sufficiency Contest: Use These Homegrown Cores to Build Kit | Simon Sharwood, The Register

Aug 19, 2020

RIOS Laboratory and Imagination Announce Partnership to Grow the RISC-V Ecosystem | Imagine Technologies (Press Release)

Aug 18, 2020

Hot Chips 2020 Live Blog: Manticore 4096-core RISC-V (3:30pm PT) | Dr. Ian Cutress, Anandtech

Aug 18, 2020

SiFive and Innovium Announce Collaboration to Accelerate Innovation in Data Center Networking

Aug 17, 2020

RISC-V Training Partners Bring professional learning to the worldwide community!

Aug 17, 2020

Calista Redmond | Open Hardware Revolution | ICM University of Warsaw (YouTube)

Aug 17, 2020

Lattice: Sentry Stack and Supply Guard Protect Against Malware and Cloning | staff, all-electronics.de (German)

Aug 17, 2020

Hot Chips 2020 Live Blog: Alibaba Xuantie-910 RISC-V CPU | Dr. Ian Cutress, Anandtech

Aug 17, 2020

SiFive Announces OpenFive, an Industry-Leading Custom Silicon Business Unit

Aug 14, 2020

New RISC-V Director of Marketing: Increasing Visibility of the RISC-V Revolution

Aug 13, 2020

New RISC-V CTO on Open Source Chip Architecture’s Global Data Center Momentum | Christine Hall, Data Center Knowledge

Aug 13, 2020

EECE 2020 | GP Presentations | Digital Implementation of The RISC V Based on Open PULP Core | Almohandes Khana (YouTube)

Aug 7, 2020

Learn About The SiFive 20g1 Release In This Short Overview By Drew Barbier, Director, Core IP | Drew Barbier, SiFiveInc

Aug 7, 2020

Picocom Embeds 32 Andes N25F RISC-V Cores Into Its 5G NR Small Cell Baseband SoC

Aug 7, 2020

Tachyum Shows Prodigy Running Existing x86, ARM, And RISC-V Software

Aug 6, 2020

Bickering Apple ARM: Sales Could Increase Acceptance Of RISC-V | Michael Eckstein, Elektronik Praxis (German)

Aug 6, 2020

Linux 5.8 Release – Main Changes, Arm, MIPS, And RISC-V Architectures | Jean-Luc Aufranc, CNX Software

Aug 5, 2020

Dev Kit Weekly: RISC-V GD32V Evaluation Board From IAR Systems And GigaDevice | Perry Cohen, Embedded Computing Design

Aug 5, 2020

Codasip and Metrics Design Automation Announce the Integration of the Metrics Cloud Simulation Platform in Codasip's RISC-V SweRV Core™ Support Package Pro

Aug 4, 2020

Welcoming RISC-V International Board Members

Aug 3, 2020

Verification and Validation in the cybersecure automotive world

Jul 31, 2020

Are we facing a future of virtual events?

Jul 30, 2020

The RISC-V Rundown From DAC 2020 | Caroline Hayes, Electronics Weekly

Jul 29, 2020

20200627 RISC-V Assembly Coding & Coding on Raspberry Pi: From Scratch to Python | Peter Cheung, Hours of Code Hong Kong

Jul 29, 2020

RISC-V Scope of Changes for Custom Instruction | LearnRISC-V

Jul 28, 2020

新华三半导体成功采用赛昉科技RISC-V U7多核处理器

Jul 28, 2020

PolarFire SoC Icicle Kit with Antmicro’s HDMI board

Jul 27, 2020

Aldec @ DAC 2020: Presenting RISC-V Verification Methodologies and Solutions

Jul 27, 2020

DAC 2020: Universal Formal Verification for RISC-V Processors | Dr. Ashish Darbari, Axiomise Formal Verification Channel

Jul 26, 2020

SiFive Hones RISC-V Cores for More Processing Power and Fewer Watts | Steve Bush, Electronics Weekly

Jul 25, 2020

RISC-V in Biometric Applications – 2020 Hsinchu RISC-V Meetup | Todd Lin, Egis Tech

Jul 24, 2020

RISC-V, Present and Future – 2020 Hsinchu RISC-V Meetup | Morris Hung, Andes Technology

Jul 24, 2020

RISC-V in Biometric Applications – 2020 Hsinchu RISC-V Meetup | Todd Lin, Egis Tech

Jul 24, 2020

Codasip’s Expanding RISC-V Offering | Roddy Urquhart, Codasip

Jul 24, 2020

RISC-V Global Forum: Technology. Opportunity. Community.

Jul 24, 2020

Rambus CryptoManager Root of Trust Core – 2020 Hsinchu RISC-V Meetup | Stephen Wu, Rambus

Jul 23, 2020

Opening Remark: RISC-V International CEO Calista Redmond – 2020 Hsinchu RISC-V Meetup | Calista Redmond

Jul 23, 2020

IAR EWRISC-V與Andes RISC-V P-extension 的最佳方案 – 2020 Hsinchu RISC-V Meetup | Ben Tsai, Andes Technology

Jul 23, 2020

Aldec Provides Static Verification for RISC-V Designs with the Latest Release of ALINT-PRO

Jul 23, 2020

Market Trends: Custom ICs Based on RISC-V Will Enable Cost-Effective IoT Product Differentiation | Amy Teng, Gartner

Jul 22, 2020

OpenHW Ecosystem Implements Imperas RISC-V reference models for Coverage Driven Verification of Open Source CORE-V processor IP cores

Jul 22, 2020

Codasip’s Expanding RISC-V Offering

Jul 21, 2020

Codasip Releases the First Linux-Capable RISC-V Core Bk7 Optimized for Domain-Specific Applications

Jul 21, 2020

Project Showcase: Implementing FreeRTOS on SparkFun RED-V

Jul 20, 2020

OneSpin Solutions to Participate at the 57th Design Automation Conference Highlighting Certified IC Integrity Verification Solutions in the Technical Program

Jul 19, 2020

OPTIMIZING RISCV FPGA BY CACHING SPI FLASH IN SRAM AND A NEW OPEN SOURCE SOFT CORE! | Bits Inside by Rene Rebe

Jul 18, 2020

Open Source Paves the Way to More Flexible, More Responsive Processor Designs | David Schiavone, Embedded Computing Design

Jul 17, 2020

Axiomise Announces the Release of the Next-Generation RISC-V® App

Jul 16, 2020

The 57th Design Automation Conference Virtual Experience Filled with Deep Technology Insights and Innovation | DAC 2020

Jul 16, 2020

RISC-V Processor Designing in Chisel and Emulation on FPGA | Muhammad Asad Hussain, Micro Electronic Research Lab UIT

Jul 16, 2020

Oh, One More RISCV FPGA Thing: Double Your Thruput With This Little Trick ;-) | Rene Rebe, More Bits inside

Jul 16, 2020

The HammerBlade RISC-V Manycore A Programmable, Scalable RISC-V Fabric | Michael Taylor and Max H Ruttenberg, FOSDEM

Jul 16, 2020

Oreboot RISC-V Firmware in Rust | Ryan O’Leary, FOSDEM

Jul 14, 2020

VITEC Licenses Codasip Bk5 Core for Multi-purpose Use in Video Products

Jul 14, 2020

VITEC Licenses Codasip BK5 Core for Multi-Purpose Use in Video Products

Jul 10, 2020

SiFive Looks To Foster Worldwide Network Of RISC-V Startups | Peter Clarke, EE News Embedded

Jul 9, 2020

Upcoming SAVVY-V Open Source RISC-V Cluster Board Supports 10GbE via Microsemi PolarFire 64-bit RISC-V SoC | Jean-Luc Aufranc, CNX Software

Jul 9, 2020

Security and Trust Assurance of RISC-V Open-Source Cores RocketCore: Sven Beyer | McKenzie Ross, OneSpin Solutions

Jul 8, 2020

RISC-V Forças e Fraquezas | Rogerio Moreira, Embarcados TV

Jul 8, 2020

BoF: Open Hardware and RISC-V – Drew Fustini & Stephano Cetola

Jul 8, 2020

Unleash Memory and Storage to Enable Next Generation Architectures

Jul 7, 2020

Design an Open-Source SoC with Google SkyWater PDK, Get It Manufactured for Free | Jean-Luc Aufranc, CNX Software

Jul 7, 2020

Improving RISC-V Linux Support in Rust | Tom Eccles, Codethink

Jul 6, 2020

Fixing Rust's Test Suite on RISC-V | Tom Eccles, Codethink

Jul 5, 2020

DAC 2020 Preview: Interest In AI, Ml And RISC-V Grow To New Levels This Year | Nitin Dahad, EE Times

Jul 4, 2020

Software Analysis: Use Trace Techniques Efficiently for RISC-V | Robert Chyla & Thomas Andersson

Jul 3, 2020

The Future of Computation: AI, ARM, and RISC-V | CogX 2020

Jul 2, 2020

Open Source Process Design Kit from Google, SkyWater Technologies and Partners Released

Jul 2, 2020

David Patterson: Computer Architecture and Data Storage | AI Podcast #104 with Lex Fridman

Jul 2, 2020

Luke Hakes, Octopus Ventures: The end of our 10 year journey

Jul 1, 2020

Chris Wade maps out UltraSoC’s development

Jun 30, 2020

About The SweRV Core EH2 | Roddy Urquhart, Semiconductor Engineering

Jun 30, 2020

Open-Source Hardware Momentum Builds | Brian Bailey, Semiconductor Engineering

Jun 30, 2020

A parting view from the Chair: Alberto Sangiovanni-Vincentelli

Jun 29, 2020

Emulsiv: A Visual Simulator for Teaching Computer Architecture Using The RISC-V Instruction Set | Guillaume Savation

Jun 28, 2020

Exploring NG SoC Architectures with Virtual Platforms and RISC-V – Kevin McDermott, Imperas

Jun 27, 2020

IAR Systems Delivers Advanced Trace for RISC-V Based Applications

Jun 26, 2020

Special COVID-19 Edition of Embedded Executive: Naveed Sherwani, CEO, SiFive | Rich Nass, Embedded Computing Design

Jun 25, 2020

SamurAI: a 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000x Peak-to- Idle Power Reduction, 207ns Wake-up Time and 1.3TOPS/W ML Efficiency | Ivan Miro-Panades, Benoit Tain, et al., Design & Reuse

Jun 25, 2020

Huami Unveils New AI Chip for Biometric Wearables | Eric Weiss, MobileIDWorld

Jun 24, 2020

RISC Simulator By Peter Higginson

Jun 23, 2020

It’s time to take the UltraSoC vision to the next level: design for product lifecycle

Jun 23, 2020

Siemens acquires UltraSoC to drive design for silicon lifecycle management

Jun 22, 2020

International Women in Engineering Day: things are changing

Jun 18, 2020

Huami Unveils The Huangshan 2 Chip, A Self Developed Processor For Its Wearables | Sean, GizmoChina

Jun 17, 2020

Intel's Security Woes Continue | DJ Ware

Jun 17, 2020

WCH CH32V103 General-Purpose RISC-V MCU Offers an Alternative to GD32V RISC-V Microcontroller | Jean-Luc Aufranc, CNX Software

Jun 17, 2020

Picocom selects UltraSoC in-system analytics and monitoring IP for 5G New Radio small cell SoC

Jun 16, 2020

RISC-V Twin Cities Meetup: Storage & AI/Machine Learning Applications

Jun 15, 2020

The 2020 Design Automation Conference Unveils Keynotes and SKYtalk Speakers

Jun 14, 2020

RISC-V Crypto Core Is Qualified To Asil-D For Automotive Designs | Nick Flaherty, EENews Europe

Jun 13, 2020

Making FPGA SoC Easier | Kevin Morris, EE Journal

Jun 11, 2020

New Series: OpenHW TV – Open Source IP Verification

Jun 11, 2020

A guide to accelerating applications with just-right RISC-V custom instructions | Lee Moore, Duncan Graham, Embedded Magazine

Jun 11, 2020

Simon Davidmann on Axiomise podcast

Jun 11, 2020

RISC-V Global Forum

Jun 11, 2020

GAP9 for ML at the Edge | Jim Turley, EE Journal

Jun 11, 2020

A Look Back at the CHIPS Alliance’s Incredible Growth

Jun 11, 2020

Andes Technology Steps Up to Premier Membership in RISC-V International; Greatly Expanding its U.S. R&D and Field Application Engineering Staffing

Jun 11, 2020

RISC-V For Linux 5.8 Finishes Bringing Up The Kendryte K210, Adds KGDB Support | Michael Larabel, Phoronix

Jun 11, 2020

Lattice Accelerates FPGA-Based Processor Design With New IP Ecosystem and Design Environment | Lattice Semiconductor

Jun 11, 2020

IAR Systems Launches Support for the RISC-V P Extension for Packed-SIMD Instructions | IAR Systems

Jun 11, 2020

(JP) Japan and RISC-V: The Future Starts Now | Andes Technology

Jun 10, 2020

Green Hills Software Adds Industry-Leading Advanced Software Development Tools Support for RISC-V

Jun 10, 2020

Get Started with IAR Embedded Workbench for RISC-V

Jun 10, 2020

This Is How We're Envisioning The Future Of A Smarter Us – We're Developing An Operating System | The Programming Foundation

Jun 10, 2020

Codasip Extends Swerv Support Package To Include Western Digital Swerv Eh2 & El2 RISC-V Cores

Jun 10, 2020

UltraSoC Enables Ultra-High-Speed Closed-Chassis Analytics And Debug Over Synopsys USB3

Jun 10, 2020

IAR Systems and GigaDevice Evaluation Kit for RISC-V | IAR Systems

Jun 9, 2020

Data61's SeL4 Security Enforcement Now Available to the RISC-V Ecosystem | Asha Barbaschow, ZDNet

Jun 9, 2020

Drew Fustini – How to Run Linux on RISC-V (with open hardware/tools) @ Raspberry Pint 2020 05 26 | Drew Fustini

Jun 9, 2020

Efinix® Announces Availability of Three RISC-V SoCs | EFINIX

Jun 9, 2020

[KAIST CS420, 2020 Spring] Introduction to RISC-V | KAIST Concurrency and Parallelism Laboratory

Jun 9, 2020

Ozark IC to Continue Ultra-High-Temperature Processor Development for NASA | I-Connect007

Jun 9, 2020

What’s So Important About Processor Extensibility? | Brian Bailey, Semiconductor Engineering

Jun 9, 2020

How to Verify Complex RISC-V–based Designs | Zibi Zalewski, EE Times

Jun 8, 2020

seL4 is verified on RISC-V!

Jun 8, 2020

seL4 operating system protects critical systems on RISC-V architecture from cyber-attacks

Jun 4, 2020

What is SweRV Core EH2?

Jun 4, 2020

The RISC-V opportunity for FPGA | Jim Hogan, Vista Ventures LLC

Jun 3, 2020

Strengthening the Internet of Things with a Secure RISC-V IoT Stack

Jun 2, 2020

What’s So Important About Processor Extensibility? | Brian Bailey, Semiconductor Engineering

Jun 2, 2020

We’re working on something special | The Programming Foundation

Jun 2, 2020

Andes Plots RISC-V Vector Heading | Mike Demler, The Linley Group

Jun 2, 2020

DARPA: a hardware-based embedded line of defense at the core

Jun 2, 2020

Codasip Extends SweRV Support Package to Include Western Digital SweRV EH2 & EL2 RISC-V Cores

Jun 2, 2020

UltraSoC enables ultra-high-speed closed-chassis analytics and debug over Synopsys USB3

Jun 2, 2020

Integrating Forces from All Walks of Life to Build an Industrial Ecosystem RISC-V Alliance Gives Taiwan Another Option | DIGITIMES

Jun 1, 2020

Welcome Mark Himelstein, RISC-V International CTO!

Jun 1, 2020

Q&A with RISC-V Ambassador Wei Fu on the Growth and Future of RISC-V

Jun 1, 2020

Optimizing Power And Timing Of RISC-V – IP, Processors And Systems | Tom Jose and Deepak Shankar, VisualSimSolutions

May 31, 2020

Li Jiajie, Chairman of Henderson Group: Accelerating the Ecological Construction of RISC-V Open Source Chips | EE Times China

May 30, 2020

RISC-V, What Is It, The Latest Updates And Consumer Oriented Applications | Dev Bhattacharya and Ted Marena, ActionSpot Talks

May 29, 2020

Domain Specific Accelerators Will Drive Vector Processing on RISC-V | Charlie Cheng, EE Times

May 29, 2020

Andes Sponsors Webinar in Japan

May 28, 2020

RISC-V Vector Extension and NX27V, the First Commercial RISC-V Vector Processor IP | John Min, Andes Technology

May 27, 2020

UltraSoC and Canis Labs partner to secure the CAN bus

May 27, 2020

RISC-V Meetup: Production Grade, Open RISC-V SweRV Core Solutions in CHIPS Alliance, May 20, 2020 | Michael Gielda, Robert Golla and Zvonimir Bandic

May 26, 2020

Engineering students’ perspectives on the future of automotive technology ‘inspiring’

May 22, 2020

Running Linux with Quad-core SMP in LiteX/VexRiscv on Arty A7 | Antmicro

May 21, 2020

SiFive Partners With Coherent Logix for Mission-Critical Processor Solutions

May 21, 2020

Special Edition: Embedded World 2020 – OneSpin

May 21, 2020

ARM Wrestles With RISC-V as Mobile Chip Battle Spills Over Into IoT | Phil Hunter, Rethink Research

May 21, 2020

Open hardware FPGA platform for multi-camera systems | Antmicro

May 21, 2020

Special Edition: Embedded World 2020 – Codasip

May 21, 2020

Special Edition: Embedded World 2020 – GreenWaves

May 21, 2020

SimpleMachines selects UltraSoC embedded analytics to support next-generation compute platform

May 21, 2020

MIPS and RISC-V — Tamara Haidar, Majd Moukalled, Bashar Shlash

May 20, 2020

The Basics of RISC-V and Its Real Life Applications – Nassif Jabbour – Sondos Osman

May 20, 2020

Accelerating Machine Learning Means New Hardware | William G. Wong, Electronic Design

May 19, 2020

Special Edition: Embedded World 2020 – Embecosm

May 19, 2020

Special Edition: Embedded World 2020 – Syntacore

May 19, 2020

After ten years of RISC-V, it’s still all about working together

May 19, 2020

Special Edition: Embedded World 2020 – CloudBear

May 19, 2020

RISC-V Q&A: Question #4 | Shaun Giebel, OneSpin Solutions

May 19, 2020

RISC-V Q&A: Question #3 | Shaun Giebel, OneSpin Solutions

May 19, 2020

RISC-V Q&A: Question #2 | Shaun Giebel, OneSpin Solutions

May 19, 2020

RISC-V Q&A: Question #1 | Shaun Giebel, OneSpin Solutions

May 19, 2020

RISC-V Q&A: Introduction | Shaun Giebel, OneSpin Solutions

May 18, 2020

Happy 10th Birthday RISC-V!

May 18, 2020

Getting Started with RISC-V Verification

May 18, 2020

UltraSoC appoints Jonathan Lucas as VP of Software

May 18, 2020

CHIPS Alliance’s Newly Enhanced SweRV Cores Available to All for Free | CHIPS Alliance

May 16, 2020

Power Side-channel Leakage Evaluation of a RISC-V Microprocessor | Muhammad Arsath

May 16, 2020

Foundries.Io Bringing Secure Linux Solutions For Arm, Intel & Risc-V Based Hardware

May 15, 2020

SiFive: “Vectors are History”: 30 Years Later | Randy Allen, The Linley Group

May 15, 2020

SiFive: The Direction and Magnitude of SiFive Intelligence | Nick Knight, The Linley Group

May 15, 2020

Special Edition: Embedded World 2020 – SiFive

May 15, 2020

RISC-V International Announces Call for Speakers for the Third Annual RISC-V Summit

May 15, 2020

Special Edition: Embedded World 2020 – Imperas

May 15, 2020

Special Edition: Embedded World 2020 – Andes Technologies

May 13, 2020

Trace Techniques for RISC-V – How to Use it Efficiently | Robert Chyla and Thomas Andersson, IAR Systems

May 11, 2020

2020 RISC-V CON Series: The Next Generation RISC-V Processors AndesCore™ 27, 45 Series | Jason Lin & KY Hsieh, Andes Technology

May 11, 2020

(中) 2020 RISC-V CON Series: The Next Generation RISC-V Processors AndesCore™ 27, 45 Series | Jason Lin & KY Hsieh, Andes Technology (Chinese)

May 11, 2020

RISC-V International and GlobalPlatform Partner to Enhance Security Design of IoT Devices

May 10, 2020

Xvisor: Embedded Hypervisor for RISC-V – Anup Patel, Western Digital

May 9, 2020

RISC-V Munich Meetup

May 8, 2020

Developing the RISC-V Hypervisor Extensions in QEMU – Alistair Francis, Western Digital

May 7, 2020

BSC Develops Safety Features Unlocking Full Processor Performance for SELENE Systems

May 7, 2020

Free RISC-V Core For Medical Equipment Projects | Nick Flaherty, EENews Europe

May 7, 2020

The RISC V LLVM Based Compiler | Gaurav Mehta

May 6, 2020

Rapid Embedded Prototyping with SiFive Software | Bernard Murphy, Sam Grove and Bunnaroath Sou, SiFive

May 6, 2020

More than Moore with Domain-Specific Processors

May 6, 2020

An introduction to SERV | Diode Zone

May 6, 2020

Seattle Application Security Virtual Meetup | Ian Gorrie

May 5, 2020

SiFive Joins Open COVID Pledge to Fight Global Pandemic | OA Online

May 5, 2020

Entry Into Development with RISC-V-based Microcontrollers | Rich Miron and Michael Eckstein, Elektronikpraxis (German)

May 4, 2020

RISC-V Meetups: In-Person Learning About the RISC-V Ecosystem | Ted Marena, ElectronicDesign

May 4, 2020

Q&A with RISC-V Ambassador Florian Wohlrab on the Growth and Future of RISC-V

May 1, 2020

UCSC Open-Source Hardware and EDA Seminar: Sagar Karandikar FireSim and FirePerf | Matthew Guthaus

May 1, 2020

Webinar: Multicore RISC-V Designs in AI & Machine Learning Applications | Imperas

May 1, 2020

High Performance RISC-V Emulator | PPT | Aditya Dixit

Apr 30, 2020

Senior Project Spotlight: Anthony Kenny | Harvard University

Apr 30, 2020

Linux 5.8 Seeing The Preliminary Changes Ahead Of RISC-V EFI Support | Michael Larabel, Phoronix

Apr 30, 2020

Ingenic T31 AI Video Processor Combines MIPS & RISC-V Cores | Jean-luc Aufranc, CNX Software

Apr 29, 2020

Embedded Linux Conference Goes Virtual At $50 A Pop | Eric Brown, LinuxGizmos

Apr 29, 2020

SystemVerilog linting and formatting with FuseSoC – Verible integration | Antmicro

Apr 29, 2020

Building Freestanding C and C++ Programs (K4M0-CSCI-463) | John’s Basement

Apr 28, 2020

2020 RISC-V CON Series: TWS Solution Using Andes D25+ACE | Wei Tung, Andes Technology (English)

Apr 28, 2020

(中) 2020 RISC-V CON Series: TWS Solution Using Andes D25+ACE | Wei Tung, Andes Technology (Chinese)

Apr 26, 2020

Why Apple needs to ditch Intel for ARM or RISC | Andre Martin and Karen Haslam, Macworld

Apr 25, 2020

Address Spaces-II & Calling Conventions (K4L0-CSCI-463) | John’s Basement

Apr 24, 2020

GD32VF103 RISC-V Board PlatformIO JTAG Getting Started & Debugging | DVXLab

Apr 24, 2020

RISC-V FPGA SoC Module | Guillem Alsina, Industria Embebidahoy

Apr 23, 2020

RISC-V Lets Us Start With a Clean Slate | Gajinder Panesar, EE Times India

Apr 23, 2020

Imperas Leading RISC-V CPU Reference Model for Hardware Design Verification Selected by Mellanox | EE Journal

Apr 23, 2020

CODASIP RELEASES SUPPORT PACKAGE FOR WESTERN DIGITAL’S FIRST RISC-V SWERV CORE

Apr 23, 2020

Sipeed MaixCube is a Fully Integrated AI Development Platform Powered by Kendryte K210 RISC-V SoC | Jean-Luc Aufranc, CNX Software

Apr 23, 2020

A future of threat detection applications; and updates on SecureCAV

Apr 22, 2020

Hope That RISC-V Architecture Will Become a Strong Opponent of Proprietary Architecture Within 5 Years | LeiFeng.com

Apr 22, 2020

LCG Demo 20191219 | LeWiz

Apr 22, 2020

AI Chip Revelations | A Corporate Soap Opera | The Sounds of a Pandemic | Brian Santo, EE Times

Apr 21, 2020

Virtual Conference Delivers Real Chips | Kevin Krewell, EE Times

Apr 17, 2020

The Challenges of Making Open-Source RISC-V Deployment Effective

Apr 16, 2020

Game of Life on RISCV FPGA – Homage to John H. Conway! | Bits & More by Rene Rebe

Apr 16, 2020

RISCV FPGA Firmware File I/O & Roland MT32 General MIDI patching! | Bits & More by Rene Rebe

Apr 15, 2020

RISC-V Disassembler (K3O0-CSCI-463) | John’s Basement

Apr 15, 2020

2020 RISC-V CON Seires: Andes Custom Extension™ – Accelerating Domain-Specific Architecture | YiChiang Chang, Andes Technology (English)

Apr 15, 2020

(中) 2020 RISC-V CON Seires: Andes Custom Extension™ – Accelerating Domain-Specific Architecture | YiChiang Chang, Andes Technology (Chinese)

Apr 15, 2020

UltraSoC and Agile Analog collaborate to detect physical cyber attacks

Apr 13, 2020

New Video: RISC-V Revolution

Apr 9, 2020

Microcontrollers Attack Low-Power Terminal AI Application Market | Sally Ward-Foxton, EE Times Taiwan

Apr 9, 2020

Celebration of IoT Day 2020: How Open Hardware & Software Is Stimulating IoT Innovation

Apr 9, 2020

Have you checked the hidden costs of deploying an open source RISC-V core?

Apr 9, 2020

RISC-V Seattle Meetup: RISC-V P-Ext and V-Ext and Custom Instructions for AI and ML Applications

Apr 8, 2020

DuctTape – A High-level RISC-V Assembler – Elliot Forbes & Justin Severeid – UWLAX | Midwest Instruction & Computing Symposium

Apr 8, 2020

RISC-V: An Open Source Approach Accelerating EDA Implementations

Apr 8, 2020

How to Create an Embedded System with Mi V Using PolarFire® FPGA | Microchip Technology

Apr 8, 2020

The first 1825 days

Apr 6, 2020

Special Edition: Embedded World 2020 – UltraSoC

Apr 6, 2020

Keeping things moving in Asia during COVID-19

Apr 2, 2020

SiFive to Present at Virtual Linley Spring Processor Conference

Apr 2, 2020

SiFive Launches Advanced Trace and Debug Portfolio, SiFive Insight

Apr 2, 2020

Andes Technology Announces Over 5 Billion Cumulative Shipments of SoCs Embedded with Its CPU IP Since Company Inception

Apr 2, 2020

There Will Be 62.4 Billion RISC-V Processor Cores in Operation by 2025 | François Gauthier, L’Embarqué

Apr 2, 2020

With X86 / Arm Three Minutes, How Many Steps Does RISC-V Need? | Shaoyue Feng, ESMC China

Apr 1, 2020

Linux 5.6 Release – Main Changes, Arm, MIPS & RISC-V Architectures | Jean-Luc Aufranc, CNX-Software

Apr 1, 2020

SEGGER Announces Support for Nuclei RISC-V Processors

Apr 1, 2020

(中) 2020 RISC-V CON Series: Andes Software Solutions for RISC-V

Apr 1, 2020

RISC-V SoC Soft Core w/ MicroPython on MATRIX Voice FPGA | Samreen Islam, Andrés Calderón and Carlos Chacin, Hackster.io

Apr 1, 2020

2020 RISC-V CON Series: Andes Software Solutions for RISC-V | Niraj Dengale, Andes Technology

Mar 31, 2020

Benchmarking RISC-V IL, Implementing Branch and Memory TLBs (Part 2 of 2) | Brandon Falk, Gamozolabs

Mar 31, 2020

Benchmarking RISC-V IL, Implementing Branch and Memory TLBs (Part 1 of 2) | Brandon Falk, Gamozolabs

Mar 31, 2020

How to Create an Embedded System with Mi-V Using PolarFire® FPGA | Microchip Technology

Mar 31, 2020

Calista Redmond: Welcome to the RISC-V Revolution

Mar 31, 2020

SEGGER Announces Comprehensive Support for SiFive Insight Debug/Trace Platform

Mar 30, 2020

Vehicle cybersecurity: a vital never ending journey

Mar 30, 2020

The Importance of a Standardized Processor Trace

Mar 26, 2020

Read a Paper: Design of the RISC-V Instruction Set Architecture | Vivek Haldar

Mar 26, 2020

Linux on RISC-V – Drew Fustini | Foss-north

Mar 26, 2020

High Performance Scalable RTOS for RISC-V Architecture | ELEKTRONIKPRAXIS

Mar 25, 2020

Electronics Let's Play – Litex RISC-V SOC for iCEBreaker FPGA with C and Rust Programming | Piotr Esden-Tempski

Mar 25, 2020

MeganWachs – Keynote RISC-V and FPGAs: Open Source Hardware Hacking | SiFive

Mar 25, 2020

Week In Review: Design, Low Power | Jesse Allen, Semiconductor Engineering

Mar 24, 2020

RTOS and RISC-V Processor | Iris Straw, Markt&Technik

Mar 24, 2020

A perspective from Poland

Mar 24, 2020

Codasip Studio and Codasip CodeSpace 8.3 available

Mar 23, 2020

RISC-V is Here to Stay | Dan Mandell, VDC Research

Mar 22, 2020

Intro to SiFive Insight – A Comprehensive Debug and Trace Solution for RISC-V ISA

Mar 21, 2020

How to Increase the Size of the Data Memory on SiFive FE310 RISC-V | Dumi Loghin, Medium

Mar 20, 2020

Antmicro at Embedded World 2020, FPGA, Edge to Cloud AI, RISC-V Open Hardware and Software, Renode

Mar 20, 2020

Business not quite as usual – but soldiering on

Mar 18, 2020

Codasip Awarded European Union Horizon 2020 Funding for Developing New RISC-V Processors

Mar 17, 2020

MEEP Project: A Flexible System Supporting Next Generation European Open Source Software and Hardware | Cordis – European Commission

Mar 17, 2020

RISC-V Instruction Format | Viator Sun, CSDN

Mar 16, 2020

RISC-V Foundation Booth Tour at Embedded World 2020 Featuring SiFive, Andes, GreenWaves and More | Charbax

Mar 16, 2020

RISC-V: An Open Approach to System Security

Mar 16, 2020

Introduction to RISC V and Assembly Language for Beginners | Bahadir Balban, Dev.to

Mar 15, 2020

GD32 MCU wins Embedded Award 2020 International Top Award | Wei Yuning, Digitimes

Mar 15, 2020

Andes Custom Extensions to the RISC-V V5 CPU Core for Creating Highly Competitive True Wireless Stereo SoC Designs | Global Newswire

Mar 12, 2020

Inaugural class of RISC-V Ambassadors

Mar 10, 2020

RISC-V processor trace now standardized: Even open source needs agreed specs

Mar 9, 2020

RISC-V Foundation Announces Ratification of the Processor Trace Specification

Mar 9, 2020

Gowin FPGA Demo at EW2020 Series #2

Mar 8, 2020

Can China Foster Open Source Hardware Innovation? | Gu Zhengshu, EE Times China

Mar 7, 2020

Wei Fu. Linux on RISC-V–Fedora and Firmware in Practice. Embedded Fest 2019 | Fest Group

Mar 6, 2020

Calista in Conversation with Iris Stroh on the VIP Stage at Embedded World 2020 | Markt & Technik, Elektroniknet.de

Mar 6, 2020

RISC-V and the Revolution in Open Source Hardware | Marco Brigida, MMUL

Mar 5, 2020

Emerging Technology Analysis: Opportunities of Open Instruction Set Architecture RISC-V | Amy Teng and Roger Sheng, Gartner

Mar 5, 2020

Do-It-Yourself Chips Nibble at Mighty Duopoly | Wim De Preter, De Tijd

Mar 5, 2020

Vortex Brings the RISC-V ISA to the World of OpenCL-Compatible General-Purpose GPUs | Gareth Halfacree, Hackster.io

Mar 5, 2020

#ew20 cybersecurity, safety, RISC-V…and much more

Mar 5, 2020

Open Source Hardware: The Rise of RISC-V | David Cassel, The New Stack

Mar 4, 2020

The World is Big Enough! – Calista Redmond, CEO RISC-V | Wisse Hettinga, eeNews Europe

Mar 4, 2020

By 2025, 62.4 Billion RISC-V CPU Cores Will Be Used | Calista Redmond, Elektroniknet.de

Mar 4, 2020

Espressif's 240MHz ESP32-S2 SoCs, Modules, and Boards Enter Mass Production with RISC-V Coprocessor | Gareth Halfacree, Hackster.io

Mar 4, 2020

OneSpin Highlights How to Achieve IC Integrity at Major Global Events and Speaking Engagements

Mar 3, 2020

Unolab Inc. Joined the RISC-V Foundation

Mar 3, 2020

ONiO.zero RISC-V Microcontroller Functions on Harvested Energy | Tope Oluyemi, Electronic Lab

Mar 2, 2020

New System-on-Module M100PFS Based on Microchip's Low-power PolarFire SoC FPGA | Embedded Computing Design

Mar 1, 2020

RISC-V and the Future of Chip Design | VCast Online

Feb 29, 2020

UEFI Boot Support Published for RISC-V on Linux | Michael Larabel, Phoronix

Feb 28, 2020

HIPEAC 2020 Keynote 2: Calista Redmond on the RISC-V Revolution

Feb 28, 2020

RISC-V's Calista Redmond on the Open ISA Revolution | HiPEAC

Feb 28, 2020

Imperas announce first reference model with UVM encapsulation for RISC-V verification

Feb 28, 2020

Opening Doors to Open-Source Hardware, Software and Standards | Richard New, Western Digital

Feb 28, 2020

Embedded Award 2020: And the Winner Is… | EmbeddedWorld.de

Feb 27, 2020

Getting Started with RT-Thread Nano RTOS on RISC-V Processors | Jean-Luc Aufranc, CNX-Software.com

Feb 27, 2020

OneSpin’s Focus on Assuring IC Integrity Across Multiple Sectors Leads to 37% CAGR Over Five Years | Business Wire

Feb 27, 2020

RISC-V Gaining Ground | Nick Farrell, Fudzilla

Feb 27, 2020

RISC-V Reference Models Support Processor Verification | Aimee Kalnoskas, Microcontroller Tips

Feb 26, 2020

OpenHW Group Celebrates Rapid Growth to 40+ Members and New Open-Source Processor Implementations Less Than a Year After Launch

Feb 25, 2020

Bluespec's RISC-V Factory Proves Its Dependable Productization, Helping Calligo Technologies Harness RISC-V for Posit-Enabled Computing | Bluespec

Feb 25, 2020

Adapting the Microcontroller for AI in the Endpoint | Sally Ward-Foxton, EE Times

Feb 24, 2020

Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores | Business Wire

Feb 24, 2020

UltraSoC launches CAN Sentinel to boost automotive cybersecurity

Feb 24, 2020

UltraSoC präsentiert CAN-Sentinel, um die Cybersicherheit in Automobilen deutlich zu erhöhen

Feb 23, 2020

Early Access Program for PolarFire® SoC FPGA | Microchip Technology

Feb 22, 2020

[RISC-V Application Example: Wearable Device] Ultra-Power-Saving SoC Becomes the Key to Battery Life | Yu Zhihao, iThome Online (Chinese)

Feb 21, 2020

Imperas Collaborates with Mentor on RISC-V Core RTL Coverage Driven Design Verification Analysis

Feb 21, 2020

SILICON | China’s Progress on Homegrown CPUs | Stewart Randall, TechNode

Feb 20, 2020

SiFive's Mysterious Learn Inventor kit | Alex Glowaski, Hackster.io

Feb 20, 2020

FPGA System-on-Module for Power-Efficient Computation | Anis Zenadji, IEN Europe

Feb 20, 2020

History of SiFive, Past-Present-Future

Feb 19, 2020

Antmicro GEM ASIC Leverages zGlue Technology to Quickly Bring Custom Arm/RISC-V SoC’s to Market | Jean-Luc Aufranc, CNX Software

Feb 19, 2020

How to Build & Run Linux on Kendryte K210 RISC-V NOMMU Processor | Jean-Luc Aufranc, CNX Software

Feb 19, 2020

RVSoC Offers a Lightweight Linux-Capable RISC-V Core in Just 5,000 Lines of Verilog | Gareth Halfacree, Hackster.io

Feb 18, 2020

Linux Kernel Continues Prepping for RISC-V's Updated Supervisor Binary Interface | Michael Larabel, Phoronix

Feb 18, 2020

Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V | Shubu Mukherjee, Chief SoC Architect of SiFive

Feb 18, 2020

RISC-V is not an "open-source processor" | Krste Asanovic, Chairman of the Board, RISC-V

Feb 18, 2020

RISC-V | Open to the Future | AntTV (Spanish)

Feb 17, 2020

The MCU Dilemma | Brian Bailey, Semiconductor Engineering

Feb 15, 2020

Can China Spawn Open Source Hardware Innovations Like Arduino and RISC-V? | Gu Zhengshu, EETimes China

Feb 14, 2020

David Patterson of UC Berkeley to Present Keynote at HOST 2020 | IEEE Computer Society

Feb 14, 2020

Semiconductor and Chip Technology Trends 2020 | Verdict

Feb 14, 2020

Open computing at the edge: Embedded World 2020 | Antmicro

Feb 14, 2020

A Portable and Linux Capable RISC-V Computer System in Verilog HDL | Junya Miura, Hiromu Miyazaki and Kenji Kise, Cornell University

Feb 13, 2020

IAR Systems Invites Visitors of Embedded World 2020 to Free In-booth Seminars

Feb 13, 2020

Dev Kit Weekly: SiFive Learn Inventor | Brandon Lewis, Embedded Computing Design

Feb 13, 2020

Building Your Own RISC-V CPU with SiFive | Level1Techs

Feb 13, 2020

UltraSoC collaborates with PDF Solutions to prevent in-life product failures using end-to-end analytics and advanced machine learning techniques

Feb 11, 2020

Floating Point Library For RISC-V | Manne Kreuzer, Markt & Technik

Feb 11, 2020

Cybersecurity meetup tackles risks and legislation

Feb 10, 2020

Embedded Controller Floating-Point Library Supports RISC-V | Aimee Kalnoskas, Microcontroller Tips

Feb 9, 2020

Bavarian RISC-V Security Chip With seL4 Microkernel | Christof Windeck, Heise

Feb 8, 2020

Oreboot Continues Advancing For Open-Source, Rust-Based Booting On RISC-V | Michael Larabel, Phoronix

Feb 7, 2020

RISC-V Foundation Showcases Unprecedented Momentum and Growth at Embedded World 2020

Feb 7, 2020

RISC-V Foundation & Members At Embedded World 2020

Feb 7, 2020

SEGGER Releases Floating-Point Library For RISC-V

Feb 6, 2020

Create A Research Network To Boost The Development Of Open Source Hardware | La Vanguardia

Feb 6, 2020

seL4 Microkernel Being Ported To RISC-V | Michael Larabel, Phoronix

Feb 5, 2020

RISC-V Calista Redmond: Exclusive Interview For AT | Andatux Isaac, ArchiTecnologia

Feb 5, 2020

System-On-Module Integrates Multi-Core RISC-V SoC FPGA | Alex Lynn, Electronics Specifier

Feb 5, 2020

High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V | Shubu Mukherjee, SiFive

Feb 4, 2020

M100PFS – PolarFire RISC-V SoC-FPGA Module | Electronics Lab

Feb 4, 2020

Compute Module And Eval Kit Run Linux On RISC-V-Based PolarFire SoC | Eric Brown, LinuxGizmos

Feb 4, 2020

Automotive cybersecurity presents a threat to the OEM business model

Feb 3, 2020

Early Access Programme For PolarFire FPGAs | Dataweek

Feb 3, 2020

UltraSoC extends its commitment to Japanese market with appointment of Ryoden

Feb 1, 2020

SoM Is Built Around Multi-Core RISC-V SoC FPGA | Julien Happich, Semiconductor Engineering

Feb 1, 2020

RISC-V, Open Source Hardware and CHIPS Trends | John Blyler, ChipEstimate

Jan 31, 2020

Emulate 32-Bit And 64-Bit RISC-V In Your Browser With Asami's Open Source rvemu | Gareth Halfacree, Hackster.io

Jan 31, 2020

Cobham Gaisler Successfully Verifies Its First RISC-V Processor, NOEL-V, Using Aldec’s Riviera-PRO for HDL Simulation

Jan 31, 2020

LLVM Founder Changes To RISC-V Specialist | Sebastian Grüner, Golem

Jan 31, 2020

Linux 5.5 Release – Main Changes, Arm, MIPS and RISC-V Architectures | Jean-Luc Aufranc, CNX Software

Jan 31, 2020

Early Access For RISC-V Enabled Low-Power SoC FPGAs | Alex Lynn, Electronic Specifier

Jan 30, 2020

Supercon Keynote: Megan Wachs Breaks Down RISC-V | Elliot Williams, Hackaday

Jan 30, 2020

ESP Open Source Research Platform Enables the Design of RISC-V & Sparc SoC’s with Accelerators | Jean-Luc Aufranc, CNX Software

Jan 30, 2020

Ada and RISC-V Secure Nvidia’s Future | William G. Wong, ElectronicDesign

Jan 27, 2020

Will the UK take the lead on IoT security legislation?

Jan 23, 2020

SiPearl: Company Founded For European CPU With ARM And RISC-V Technology | Christof Windeck, Heise

Jan 23, 2020

RISC-V Breaks All Records | Iris Stroh, Elektronik

Jan 22, 2020

Alibaba’s RISC-V Core Disclosed | Christof Windeck, Heise

Jan 22, 2020

Intel and Softbank Beware. Open Source Is Coming to the Chip Business | Ian King, Bloomberg

Jan 22, 2020

UltraSoC Offers An Open Source Implementation Of A RISC-V Trace Encoder Via The OpenHW Group | Pierrick Arlot, L’Embarqué

Jan 22, 2020

Imagination Technologies Charts Its Future With New Apple Deal And Post-MIPS Strategy | Dean Takahashi, VentureBeat

Jan 22, 2020

Welcome to 2020: cybersecurity, automotive and in-life analytics take center stage

Jan 16, 2020

Microchip Gives Early Access For Its PolarFire FPGA For Efficient, Low-Power Embedded Computing Applications | Military & Aerospace Electronics

Jan 16, 2020

Storage And Memory At The 2020 CES, Part 2 | Tom Coughlin, Forbes

Jan 15, 2020

RISC-V Summit 2019 Videos Posted

Jan 15, 2020

Fast Access to Accelerators: Enabling Optimized Data Transfer With RISC-V | Shubu Mukherjee, SiFive

Jan 15, 2020

Bleeding Edge Information Technology Developments | Yogi Schulz, IT World Canada

Jan 15, 2020

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC | David Schor, WikiChip Fuse

Jan 14, 2020

Andes Technology Takes The Lead In Launching RISC-V Total Solutions And Driving Industry-Academia Collaboration With Over 120 Projects

Jan 14, 2020

How To Get Started With RISC-V-Based Microcontrollers | Jacob Beningo, DigiKey

Jan 13, 2020

Build Your Own Edge AI SoC With SiFive RISC-V CPUs And CEVA AI Chips | Eric Brown, LinuxGizmos

Jan 13, 2020

SiFive And Ceva Partner To Build Mainstream Edge AI Processors | Lucian Armasu, Tom’s Hardware

Jan 13, 2020

Automotive security: Computers on wheels and networks in the fast lane

Jan 12, 2020

ONiO.zero Offers A RISC-V Microcontroller That Runs Without Battery | Ayo Ayibiowu, CNX Software

Jan 11, 2020

Open Source Hardware Risks | Ann Steffora Mutschler, Semiconductor Engineering

Jan 10, 2020

Are Open Source RISC-V CPUs Destined For The Server Market? | Christine Hall, IT Pro

Jan 10, 2020

RISC-V Business: SiFive And CEVA Join Forces To Enable The Development AI-Amenable, Edge-Oriented Processors | Thomas Claburn, The Register

Jan 10, 2020

SiFive And CEVA Partner To Bring Machine Learning Processors To Mainstream Markets

Jan 9, 2020

BSC Coordinates Development of RISC-V ‘Lagarto’ Processor | Barcelona Supercomputing Center, HPC Wire

Jan 9, 2020

10 Leading Tech Trends: How Artificial Intelligence Will Evolve In The Coming Year | DataQuest

Jan 9, 2020

Defense-Grade FPGA Debuts With Early Access | Gina Ross, Embedded.com

Jan 8, 2020

Week In Review: Design, Low Power | Jesse Allen, Semiconductor Engineering

Jan 8, 2020

Polos GD32V Alef Is A Tiny RISC-V MCU Board Selling For $3 | Jean-Luc Aufranc, CNX Software

Jan 8, 2020

RISC-V Lagarto Is First Open Source Chip Developed In Spain | Rich Brueckner, insideHPC

Jan 7, 2020

Bluespec Unveils Groundbreaking “RISC-V Factory” — Empowering Open Source Hardware Developers To Build Faster And More Efficiently

Jan 7, 2020

How RISC-V Is Creating A Globally Neutral, Open Source Processor Architecture | Dean Takahashi, VentureBeat

Dec 31, 2019

ONiO.zero Offers Up To 24MHz Of RISC-V Microcontroller Performance On Nothing But Harvested Energy | Gareth Halfacree, Hackster.io

Dec 29, 2019

Microchip Unveils Details And Opens Early Access Program For RISC-V Enabled Low-Power PolarFire SoC Family | Intelligent Aerospace

Dec 27, 2019

Will Open-Source Processors Cause A Verification Shift? | Ann Steffora Mutschler, Semiconductor Engineering

Dec 23, 2019

What Worked, What Didn’t In 2019 | Brian Bailey, Semiconductor Engineering

Dec 22, 2019

Ultra-Low Power AI Chip Ups The Ante | Sally Ward-Foxton, EE Times

Dec 21, 2019

What's Happening in RISC-V Land? | Paul McLellan, Cadence

Dec 20, 2019

Highlights from the 2019 RISC-V Summit: a Look at the Future of Computing

Dec 19, 2019

HotChips RISC-V Tutorial Video Now Available

Dec 19, 2019

RISC-V Summit 2019 – Proceedings

Dec 19, 2019

AndesCore 27-Series Linux RISC-V SoC Features A Vector Processing Unit | Stephen Vicinanza, CNX Software

Dec 18, 2019

Samsung To Use SiFive RISC-V Cores For SoCs, Automotive, 5G Applications | Anton Shilov, AnandTech

Dec 18, 2019

Veridify Security To Demonstrate DOME A Zero-Touch Onboarding And Device Management Solution For RISC-V Processors | Tiera Oliver, Embedded Computing Design

Dec 18, 2019

RISC-V Summit: Silicon Labs Q&A On IoT Hardware | Brian Buntz, IoT World Today

Dec 18, 2019

Linux-Driven RISC-V Core To Debut On An NXP i.MX SoC | Eric Brown, LinuxGizmos

Dec 18, 2019

Support For RISC-V Expands At Summit | Chris Edwards, Tech Design Forum

Dec 18, 2019

RISC-V and Arm – signs of an open heterogeneous world

Dec 18, 2019

Driving To Data-Centric Architectures And 1B RISC-V Cores | Office of the CTO, Western Digital

Dec 17, 2019

RISC-V Based PolarFire SoC FPGA And Devkit Coming In Q3 2020 | Jean-Luc Aufranc, CNX Software

Dec 17, 2019

Getting Started with RISC-V Europe Roadshow Proceedings

Dec 17, 2019

RISC-V Grows Globally As An Alternative To Arm And Its License Fees | Dean Takahashi, VentureBeat

Dec 17, 2019

RISC-V Xmas Gifts: SiFive Emits Vector-Enabled Cores, Western Digital Teases New SweRVs, VxWorks Hugs ISA, Samsung Rolls It Into 5G | Chris Williams, The Register

Dec 17, 2019

Microchip Announces First RISC-V-Based SoC FPGA To Use Half The Power Of Other FPGAs | Lisa Boneta, All About Circuits

Dec 17, 2019

SiFive Learn Inventor Is A Wireless RISC-V Development Kit Inspired By BBC Micro:bit | Jean-Luc Aufranc, CNX Software

Dec 17, 2019

Codasip Partners With Western Digital On Open‑Source Processors | Julien Happich, eeNews Europe

Dec 17, 2019

Andes’ Core Has RISC-V Vector Instruction Extension | Nitin Dahad, EE Times

Dec 16, 2019

Greenwaves Preps GAP9 IoT Processor On FDSOI | Peter Clarke, eeNews Europe

Dec 16, 2019

Aerendir Mobile Inc. And SiFive Inc. Collaborate To Accelerate The Adoption Of AI-Enabled Processors | Tiera Oliver, Embedded Computing Design

Dec 12, 2019

Curated List of RISC-V Education Materials Now Available

Dec 11, 2019

Cobham Releases RISC-V Processor IP Core

Dec 10, 2019

Hex Five Announces General Availability of MultiZone™ Security for Linux – The First Commercial Enclave for RISC-V processors

Dec 10, 2019

Antmicro and zGlue release rapid turnaround chiplet-based GEM ASIC

Dec 10, 2019

CODASIP TEAMS UP WITH WESTERN DIGITAL TO SUPPORT ADOPTION OF OPEN-SOURCE PROCESSORS

Dec 9, 2019

RISC-V Foundation Seeks Technology Leader

Dec 9, 2019

Tensorflow Lite in Zephyr on LiteX/VexRiscv

Dec 9, 2019

Andes certifies Imperas models and simulator as reference for new Andes RISC-V Vectors Core with lead customers and partners

Dec 5, 2019

RISC-V Foundation Founding Member Andes Technology Turns Platinum

Dec 5, 2019

A RISC-V Fully European Platform For Space | Julien Happich, eeNews Europe

Dec 5, 2019

IAR Systems Updates RISC-V Development Tools With Support For RV32E And Atomic Operations

Dec 5, 2019

A Little Product Renaming Here, A Little RISC-V Magic There, Some Extra Performance, And Voila – Imagination's 10th-Gen PowerVR Is Born | The Register

Dec 4, 2019

Think Silicon® Demonstrates Early Preview Of Industry’s First RISC-V ISA Based 3D GPU At The RISC-V Summit

Dec 4, 2019

NEOX V Announced By Think Silicon As First RISC-V 3D GPU | Michael Larabel, Phoronix

Dec 4, 2019

Yadro Takes Control Of Russian RISC-V Startup | Peter Clarke, eeNews Europe

Dec 4, 2019

An open source SystemVerilog Test Suite | Antmicro

Dec 3, 2019

Antmicro Exhibits At RISC-V Summit 2019: Renode, Fomu And Open Chip Design

Dec 3, 2019

Final Countdown to RISC-V Summit in San Jose

Dec 2, 2019

RISC-V Summit Member Day Schedule UPDATED

Nov 28, 2019

SiFive Welcomes Ann Chin As SiFive IP Business Unit General Manager | staff, SiFive

Nov 28, 2019

Getting Started with Embedded Linux on RISC-V in QEMU | Jean-Luc Aufranc, CNX Software

Nov 27, 2019

Bootlin’s Michael Opdenacker Gets You Started with Embedded Linux on RISC-V in Just 40 Minutes | Gareth Halfacree, AB Open

Nov 27, 2019

SparkFun Picks SiFive's FE310 to Power RISC-V-Based RED-V Thing Plus, RED-V RedBoard Dev Boards | Gareth Halfacree, Hackster.io

Nov 26, 2019

Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V

Nov 25, 2019

Semico Forecasts Strong Growth for RISC-V

Nov 22, 2019

RISC-V Community News Collection: November 22, 2019

Nov 14, 2019

The RISC-V Foundation Announces the “Student of the Year” and “Educator of the Year” Awards

Oct 31, 2019

SiFive Shield is an Open Security Platform for RISC-V Processors | Jean-Luc Aufranc, CNX Software

Oct 31, 2019

SiFive Builds Hardware Crypto and Security for RISC V SoCs | Sebastian Grüner, Golem

Oct 30, 2019

OneSpin Shows How to Achieve IC Integrity at DVCon Europe | OneSpin

Oct 30, 2019

RISC-V Challenges and Opportunities | Ed Sperling, Semiconductor Engineering

Oct 29, 2019

SiFive Shield: An Open, Scalable Platform Architecture for Security | James Prior, SiFive

Oct 28, 2019

GCC Support for the Draft Bit Manipulation Extension for RISC-V | Maxim Blinov, Embescom

Oct 28, 2019

LLVM Support for the Draft Bit Manipulation Extension for RISC-V | Paolo Savini, Embecosm

Oct 22, 2019

Real-Time Visualization Of RISC-V Systems | Joachim Kroll, Elektronik

Oct 21, 2019

Why RISC-V Will Prevail | Marc Sauter, Golem

Oct 20, 2019

LLVM Clang RISC-V Now Supports LTO | Michael Larabel, Phoronix

Oct 20, 2019

Fraunhofer IMS: Trusted Embedded AI With RISC-V | Richard Oed, Elektronik Praxis

Oct 19, 2019

Real-Time System Verification Tool Now Available For RISC-V Embedded Systems | Aimee Kalnoskas, Microcontroller Tips

Oct 19, 2019

SEGGER SystemView for RISC-V Now Available | Segger

Oct 18, 2019

QuickLogic Teams with SiFive to Make eFPGA Technology Available via DesignShare Portfolio | QuickLogic

Oct 17, 2019

CHIPS Alliance Growth Continues With New Members And Design Workshop This November | PR Newswire

Oct 17, 2019

Intel And AMD’s Biggest Cloud Threat May Be An Open X86 Instruction Set | Paul Teich, Forbes

Oct 16, 2019

Samsung To Fabricate RISC-V Chip With 14LPP In Partnership With SemiFive | Ramish Zafar, Wccftech

Oct 16, 2019

Samsung Supports The RISC-V Instruction Set Architecture: The First OEM chip | cnBeta

Oct 16, 2019

SiFive Adds RISC-V Micro-Instruction Cache For Slow Memories | Steve Bush, Electronics Weekly

Oct 15, 2019

Getting Started with RISC-V Europe Roadshow Proceedings

Oct 15, 2019

The RISC-V Foundation Announces Agenda for the Second Annual RISC-V Summit

Oct 11, 2019

RISC-V: Fraunhofer IMS Introduces Microcontroller Core | All-Electronics.de

Oct 10, 2019

How China Is Aiming For A State Of Technological Independence | Paul Dempsey, Engineering and Technology

Oct 10, 2019

SiFive Continues To Foster RISC-V In The Middle East With Tech Symposiums | Swamy Irrinki, Semi Wiki

Oct 10, 2019

RISC-V ay: Andes Offers IP Cores, Accelerators, Tools, And Even A Free Core | Steve Bush, Electronics Weekly

Oct 9, 2019

Wio Lite RISC-V ESP8266 Wireless Development Board | Julian Horsey, Geeky Gadgets

Oct 9, 2019

The Rise Of Open-Source Computing | The Economist

Oct 9, 2019

India Is Trying To Create An Indigenous Chip-Making Industry | The Economist

Oct 5, 2019

A New Blueprint For Microprocessors Challenges The Industry’s Giants | The Economist

Oct 5, 2019

PicoLibC Is A Lightweight C Library For Embedded Systems | Siji Sunny, CNX Software

Oct 5, 2019

RISC-V Day: Greenwaves’ Pushes AI To The Very Edge Of IoT | Steve Bush, Electronics Weekly

Oct 5, 2019

RISC-V Foundation Announces Security-Focused Soft-Core CPU Contest Winners | Gareth Halfacree, ABOpen

Oct 4, 2019

RISC-V Day: Microchip Adds RISC-V Hard IP To PolarFire FPGAs | Steve Bush, Electronics Weekly

Oct 4, 2019

SiFive Extends Portfolio With 7 Series RISC-V Cores | Camille Kokozaki, Semi Wiki

Oct 4, 2019

Andes Technology and Tiempo Secure Announce Strategic Partnership To Enhance RISC-V Platform Security Up To CC EAL5+ Certification | Andes Technology

Oct 4, 2019

Chinese Memory, Kioxia, Micron, Xilinx And SDC | Tom Coughlin, Forbes

Oct 3, 2019

RISC-V Day: Western Digital SweRV Core | Steve Bush, Electronics Weekly

Oct 3, 2019

RISC-V Day: Trinamic Rocinante Motor Drive | Steve Bush, Electronics Weekly

Oct 3, 2019

RISC-V day: Minres For Virtual Prototyping | Steve Bush, Electronics Weekly

Oct 3, 2019

RISC-V Day: Syntacore For Risc-V MCU Core IP | Steve Bush, Electronics Weekly

Oct 2, 2019

Libre RISC-V Hybrid CPU/GPU Looking For Cash | Nick Farrell, Fudzilla

Oct 2, 2019

SiFive Announces New DesignShare IP Partnerships | SiFive

Oct 2, 2019

Renode 1.8 Release With Multi-Core GDB Support And New RISC-V Platforms | AntMicro

Oct 1, 2019

360 Registered Attendees for RISC-V Day Tokyo 2019 | RISC-V Association

Oct 1, 2019

Announcing the Winners of the RISC-V Soft CPU Contest

Sep 30, 2019

Andes and Dover Microsystems Partner to Deliver Professional Network Security Solution for RISC-V | Andes Technology

Sep 30, 2019

Kumico RISC-V Meetup in Japan Oct 23 & 25

Sep 29, 2019

Open ISAs Gaining Traction | Semiconductor Engineering

Sep 28, 2019

The Growing Impact Of Portable Stimulus | Semiconductor Engineering

Sep 27, 2019

SiFive Announces Key Enablement Of Trace And Debug | SiFive

Sep 26, 2019

Andes Technology Announces Coming Up The North America Annual RISC-V CON 2019 Santa Clara | Andes Technology (Press Release)

Sep 26, 2019

FreeRTOS with IAR Embedded Workbench for RISC-V | IAR Systems

Sep 26, 2019

Intensivate Uses SiFive's RISC-V To Develop Accelerator | Neil Tyler, New Electronics

Sep 26, 2019

LLVM 9 Releases With Official RISC-V Target Support, Asm Goto, Clang 9, And More | Vincy Davis, Packt Pub

Sep 24, 2019

第一届中国 RISC-V 论坛 – “征稿通知”

Sep 24, 2019

The First RISC-V China Forum – Call for Papers

Sep 24, 2019

Intensivate Engages SiFive's RISC-V Expertise To Develop Leading Accelerator | SiFive, PRNewswire (Press Release)

Sep 23, 2019

RISC-V Processors: Segger And Andes Agree On Cooperation | Elektronik

Sep 22, 2019

RISC-V FPGA SoC Architecture Enables Real-Time Linux | Tim Morin, All-electronics.de

Sep 21, 2019

SEGGER Makes Its Entire Ecosystem Of Tools Available For AndesCores | Andes Technology, Globe Newswire (Press Release)

Sep 20, 2019

The Top Use Cases For The GAP8 IoT Application Processor | Martin Croome, Embedded Computing Design

Sep 19, 2019

RISC-V: Fast Start In Two Days | Harry Schubert, Elektronik

Sep 19, 2019

IAR Systems Updates RISC-V Development Tools | Alix Paultre, Embedded Computing Design

Sep 19, 2019

A Recap Of The Linux Plumbers Conference 2019 | Vincy Davis, Packt

Sep 18, 2019

OneSpin Addresses The Challenges Of RISC-V Verification Through Series Of Speaking Engagements, Workshop, and Tutorials | Business Wire

Sep 18, 2019

Linux 5.3 Release – Main Changes, Arm, MIPS & RISC-V Architectures | Jean-Luc Aufranc, CNX Software

Sep 18, 2019

Can Carbon Nanotubes Take Us Beyond Silicon? | Nitin Dahad, EE Times India

Sep 18, 2019

How ChocoPy Uses Python And RISC-V To Teach Compiler Creation | James Sanders, TechRepublic

Sep 17, 2019

India's First Three (Out of 60) Supercomputers Are Here | Tom's Hardware

Sep 17, 2019

SiFive to Present at Linley Fall Processor Conference | PR Newswire

Sep 16, 2019

Intrinsic ID Security Summit

Sep 16, 2019

New Electronics article: IAR Systems Updates RISC-V Development Tools

Sep 16, 2019

Elektronik article: Optimizing Code Speed: Update The RISC V Development Tools

Sep 16, 2019

EE Times Asia article: Can Nanotubes Take Us Beyond Moore's Law?

Sep 13, 2019

Security in the Age of RISC-V: Bay Area Meetup Oct 1

Sep 13, 2019

The Journey of RISC-V Implementation

Sep 13, 2019

RISC-V Week in Paris, October 1-3

Sep 13, 2019

Hackaday article: Why Ada Is The Language You Want To Be Programming Your Systems With

Sep 12, 2019

IAR Systems Updates RISC-V Development Tools With Custom Extensions Support And Code Speed Optimizations

Sep 12, 2019

RISC-V EMEA Roadshow Spotlight: Imperas

Sep 12, 2019

Military Embedded Systems article: Using RISC-V In FPGAs For Strategic Defense Systems

Sep 12, 2019

RISC-V EMEA Roadshow Spotlight: AdaCore

Sep 12, 2019

EETimes article: MIT Builds Carbon Nanotube FET Based RISC-V Microprocessor

Sep 11, 2019

Electronics-Lab article: Sipeed Longan Nano – RISC-V GD32VF103CBT6 Development Board

Sep 11, 2019

Seeed Studio Blog: 2019 RISC-V Based Development Boards Collection

Sep 11, 2019

Electronik article: System Design: Many Trusted Environments

Sep 10, 2019

Elektor article: A Microprocessor Made From Carbon Nanotube FETs

Sep 10, 2019

Hackaday article: Hackaday Celebrates 15 Years And Oh How The Hardware Has Changed

Sep 10, 2019

ITBizNews: Design, Manufacturing Capabilities, Challenges, Ecosystems. System Semiconductor Will Grow When We Have 3 Beats

Sep 10, 2019

Codasip article: Better Benchmarks Through Compiler Optimizations: Codasip Jump Threading

Sep 10, 2019

Hackster.io article: Seeed Releases Sipeed’s Longan Nano RISC-V Development Board

Sep 9, 2019

Elektronik article: 32-Bit-Microcontrollers RISC-V for everybody

Sep 9, 2019

Nvidia Turns To RISC-V for RC18 Research Chip IO Core

Sep 9, 2019

RISC-V Gains Momentum as Industry Demands Custom Processors for New, Innovative Workloads

Sep 9, 2019

Elektronic Praxis: MIT And Analog Devices Build RISC-V Processor With Carbon Nanotubes

Sep 9, 2019

Electronics Weekly: More On: MIT’s Carbon Nanotube RISC-V CPU

Sep 9, 2019

Embedded Computing Design: SEGGER Announces Full Support For Flash-Based RISC-V Microcontroller

Sep 8, 2019

eeNews Embedded Article: Open-Source RISC-V MCU With Bumblebee Core

Sep 8, 2019

Zonamovilidad Article: What is RISC-V, Open Hardware Without Limits

Sep 8, 2019

Hackster.io Article: GigaDevice Unveils New RISC-V-Based GD32V Microcontroller

Sep 8, 2019

Hackaday Article: RISC-V Uses Carbon Nanotubes

Sep 5, 2019

RISC-V Training in Munich

Sep 4, 2019

RISC-V EMEA Roadshow Spotlight: Andes Technology

Aug 30, 2019

The Tech Report Article: Researchers Build RISC-V Chip From Carbon Nanotubes

Aug 30, 2019

Electronic Specifier Article: Full Support For First Flash-Based RISC-V Microcontroller

Aug 30, 2019

PC Watch Article: MIT Creates 16-bit RISC-V Processor With Carbon Nanotube Semiconductor

Aug 30, 2019

01net.com Article: Carbon Nanotubes And RISC-V Instructions: This Is (Perhaps) The Processor Of The Future

Aug 29, 2019

Ars Technica Article: 16-bit RISC-V Processor Made With Carbon Nanotubes

Aug 29, 2019

Tom’s Hardware Article: MIT Engineers Build 15,000-Transistor Carbon Nanotube RISC-V Chip

Aug 29, 2019

CNX Software Article: $5 Longan Nano GD32V RISC-V Development Board Comes With LCD Display And Enclosure

Aug 29, 2019

How The Open Source Movement In Hardware Is Catching Up With Software

Aug 28, 2019

RISC-V EMEA Roadshow Spotlight: Microchip Technology

Aug 28, 2019

CNX Software Article: AndesCore N22 RISC-V Core Supports RV32IMAC Or RV32EMAC Instruction Sets

Aug 28, 2019

Innovations Report Article: New Open Source Platform VerSys Allows Early Software Testing Through Virtual Chips

Aug 27, 2019

CNX Software Article: RISC-V Bases And Extensions Explained

Aug 27, 2019

Gizmochina Article: Huami’s Upcoming Huangshan 1S Processor Said To Be Built On 7nm

Aug 27, 2019

Elektronik.de Article: RISC-V Training With The ETH Zurich: PULP Platform RISC-V

Aug 27, 2019

Hackaday Article: GigaDevice Releasing RISC-V MCU’s And Development Boards

Aug 27, 2019

EE Times Article: GigaDevice Intros General-Purpose RISC-V MCUs

Aug 26, 2019

TechTarget Article: DARPA Unveils First SSITH Prototype To Mitigate Hardware Flaws

Aug 23, 2019

CNX Software Article: GigaDevice Releases GD32V RISC-V MCU And Development Boards

Aug 23, 2019

cnBeta Article: The First RISC-V-Based 32-Bit General-Purpose Microcontroller Appeared

Aug 23, 2019

GigaDevice Unveils The GD32V Series With RISC-V Core, In A Brand New 32bit General Purpose Microcontroller

Aug 22, 2019

insideHPC Article: How The European Processor Initiative Is Leveraging RISC-V For The Future Of Supercomputing

Aug 22, 2019

Semiconductor Engineering Article: What Is A Custom Processor?

Aug 21, 2019

China Times Article: Andes Technology Replaces Weapons And Makes Great Efforts To Encroach On The Security Plan

Aug 21, 2019

Data Center Knowledge Article: Western Digital's Long Trip From Open Standards To Open Source Chips

Aug 21, 2019

EE Times China Article: Who Is The "Fixed Star" Of RISC-V?

Aug 21, 2019

RISC-V Day Tokyo Agenda

Aug 21, 2019

RISC-V EMEA Roadshow Spotlight: OneSpin Solutions

Aug 20, 2019

eeNews Europe Article: Lauterbach To Support JTAG Debug For RISC-V Linux

Aug 20, 2019

Android Authority Podcast: Gary Explains RISC-V

Aug 20, 2019

cnBeta Article: The Story Of "China Core" Under The RISC-V Framework

Aug 20, 2019

Elektronik Article: HotChips 2019: ETH Zurich Takes Floating-Point Arithmetic To A New Level

Aug 20, 2019

Researchers Publish Roadmap For RISC-V Opportunities In Space Tech

Aug 20, 2019

How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing

Aug 16, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Aug 16, 2019

News.hqew Article: The Latest Open Source Chip System Level Verification And Prototype Platform Officially Released

Aug 16, 2019

Phoronix Article: QEMU 4.1 Released With Many ARM, MIPS & x86 Additions

Aug 15, 2019

Forbes Article: Seizing Controllers At The FMS

Aug 14, 2019

Elektronikne.de Article: RISC-V Roadshow – Guest Performances In Munich And Berlin

Aug 14, 2019

EE Times Taiwan Article: Embedded Processor Faces Side Channel Attack

Aug 14, 2019

RISC-V EMEA Roadshow Spotlight: GreenWaves Technologies

Aug 13, 2019

Elektronik Praxis Article: RISC-V Foundation Ratifies Specifications For Base And Privileged Architectures

Aug 12, 2019

Packt Article: Red Hat Joins The RISC-V Foundation As A Silver Level Member

Aug 12, 2019

Linux Magazin.de Article: Red Hat Joins RISC-V-Foundation

Aug 12, 2019

Western Digital Announces Technology Leadership Transition

Aug 12, 2019

MuyComputerPRO Article: Red Hat Joins RISC-V To Boost Open Source Chip

Aug 9, 2019

EE Times China Article: Looking At The Market Opportunities Of Domestic MCU Vendors From The Strategic Trends Of ST And NXP

Aug 9, 2019

Phoronix Article: Red Hat Joins The RISC-V Foundation

Aug 9, 2019

Tom’s Hardware Article: Red Hat Joins Foundation For Developing Open-Source RISC-V ISA

Aug 8, 2019

EE Times Taiwan Article: Shipments Have Repeatedly Hit New Highs, MCU Applications Revealed

Aug 8, 2019

Sina Article: Amazfit Mi Healthy Watch For Sale: 7×24 Hour Heart Rate Monitoring

Aug 7, 2019

Tech News Article: Andes Technology Is Committed To Developing RISC-V Processor Applications, And Has Grown Rapidly In The First Half Of 2019

Aug 7, 2019

Semiconductor Engineering Article: A Holistic View Of RISC-V Verification

Aug 7, 2019

RISC-V EMEA Roadshow Spotlight: Western Digital

Aug 6, 2019

Andes Records Rapid Growth of RISC-V Processors Licensing Agreements in the First Half of 2019

Aug 6, 2019

Appuals Article: China Looks At RISC-V As A Viable Replacement For Proprietary CPU Architecture Amid Trade War Tensions

Aug 6, 2019

EE Times China Report: Open Source Chips And Agile Development For Next-Generation Computing

Aug 6, 2019

China Times Article: Andes Technology H1 License Contract Over 60 RISC-V Full Range Of Solutions

Aug 5, 2019

GreenWaves Technologies Blog Post: RISC-V Roadshow In Europe, Sep 16-26, 2019

Aug 2, 2019

Seeking Alpha Article: A Pillar Of Sparks: Interview With The RISC-V Foundation

Aug 2, 2019

Huaqiang Electronic World Network Article: IBM’s Hunger For Red Hat’s Huge Gamble

Aug 1, 2019

CNX Software Article: HuskyLens AI Camera & Display Board Is Powered By Kendryte RISC-V Processor

Jul 31, 2019

Sina Article: Ketron Board Semiconductor Expansion "Core" Opportunity

Jul 31, 2019

36Kr Article: Using The SD Idea To Make Plug AI Chip Modules

Jul 31, 2019

RISC-V EMEA Roadshow Spotlight: MINRES Technologies

Jul 30, 2019

EE Times Japan Article: CEVA Acquires Hillcrest Laboratories

Jul 26, 2019

Semiconductor Engineering Article: Semiconductor’s Dinosaurs

Jul 26, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Jul 25, 2019

Semiconductor Engineering Article: Hardware-Software Co-Design Reappears

Jul 25, 2019

RISC-V EMEA Roadshow Spotlight: Trinamic Motion Control

Jul 24, 2019

RISC-V’s Role In Securing IoT-Connected Devices

Jul 24, 2019

TechNode Article: China’s Chipmakers Could Use RISC-V To Reduce Impact of US

Jul 23, 2019

FierceElectronics Article: CEVA Acquires Sensor Business From InterDigital

Jul 23, 2019

Linux Adictos Article: Linux 5.3: The New Features Of The New Kernel Version

Jul 23, 2019

All-Electronics.de Article: CEVA Acquires Sensor Specialist Hillcrest Laboratories

Jul 23, 2019

RISC-V Foundation Announces Agenda for “Getting Started with RISC-V” Roadshow in EMEA

Jul 22, 2019

Electronics Weekly Article: CEVA Buys Hillcrest Labs

Jul 22, 2019

Sina Article: Chongqing Should Increase Its Voice In The Development Of New Generation Information Technology

Jul 22, 2019

Leiphone Article: Bao Yungang, Institute Of Computing, Chinese Academy Of Sciences: There Is A "Dead Knot" In Open Source Chips, But This Is The Era Of Breaking The Knot | CCF-GAIR 2019

Jul 22, 2019

Elektronik Kalehti Article: Cheap Satellites With Open Source Architecture

Jul 19, 2019

Phoronix Article: RISC-V's Kernel Support Continues Maturing With Linux 5.3

Jul 19, 2019

East Money Article: Huami Technology Joins RISC-V Foundation To Create Smart Wearable

Jul 18, 2019

Leiphone Article: Endurance, Ruisi, Science And Technology, Jianghang Intelligent Won The 2019 AI + Edge Computing Best Growth Award | CCF-GAIR 2019

Jul 18, 2019

Embedded Computing Design Article: Programmable RISC-V-Based AI Reference Camera Supports MicroPython, OpenMV

Jul 17, 2019

IT Biz News Article: System Design Using RISC-V, Core Code Size Reduction

Jul 17, 2019

HelpNetSecurity Article: RISC-V Soft CPU Contest Challenges Designers To Develop A Hardware Secure RISC-V Soft CPU Solution

Jul 15, 2019

Hank Yung Article: Semiconductor Design Is Also Open-Source

Jul 15, 2019

El Androide Libre Article: The First Processors Based On RISC-V Increasingly Closer: What Is RISC-V?

Jul 15, 2019

EE Times Article: AI At The Very, Very Edge

Jul 15, 2019

RISC-V Foundation Launches Design Contest to Drive Security Innovation and Advance the Development of Secure RISC-V Solutions

Jul 15, 2019

Enter the RISC-V Soft CPU Contest to Drive Security Innovation

Jul 12, 2019

Semiinsights Article: The Application Of RISC-V Is Heating Up In China.

Jul 12, 2019

Huaqiang Electronics Article: Ratification Of The RISC-V Base ISA And Privileged Architecture Specifications

Jul 12, 2019

Leiphone Article: How Does China Find Out The Breakthrough In The Field Of Open-Source? RISC-V Will Be A Golden Opportunity

Jul 12, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Jul 11, 2019

CNbeta Article: RISC-V Foundation Approves RISC-V Basic Instruction Set Architecture And Privilege Architecture Specification

Jul 11, 2019

CNX Software Article: Linux 5.2 Release – Main Changes, Arm, MIPS & RISC-V Architectures

Jul 11, 2019

Bit-Tech Article: RISC-V Foundation Ratifies ISA Specifications

Jul 11, 2019

CNbeta Article: How Can China Find A Breakthrough In The Field Of Open Source Chips? RISC-V Will Be A Great Opportunity

Jul 11, 2019

Golem.de Article: RISC-V Base Frozen And Ratified

Jul 11, 2019

Developpez Article: RISC-V Foundation Announces Ratification Of RISC-V Core ISA Specifications

Jul 11, 2019

RISC-V Foundation CEO Calista Redmond to Give Keynote at Open Source Summit Japan

Jul 10, 2019

IT BitNews Article: Core System Validation 'No Problem' … "Enhanced Ecosystem, Increasing Utilization Of RISC-V Core"

Jul 10, 2019

Fabcross Article: Switch Science Launches M5Stack AI Camera And Sipeed AI Development Board

Jul 10, 2019

IT Home Article: The RISC-V ISA Explained

Jul 10, 2019

RISC-V Foundation Announces Ratification of the RISC-V Base ISA and Privileged Architecture Specifications

Jul 9, 2019

CHIPS Alliance Brings Powerful Players Into Open Source Hardware Collaboration

Jul 9, 2019

Phoronix Article: LLVM's RISC-V Compiler Back-End Looks To Go Official For 9.0 Release

Jul 9, 2019

Open Memory-Centric Architectures Enabled By RISC-V And OmniXtend

Jul 9, 2019

The RISC-V Foundation Receives Donation from Arduino to Further Strengthen its Open Source Community

Jul 8, 2019

36Kr Article: Is India Semiconductors Rising?

Jul 8, 2019

MyNavi Article: Rapidly Changing Processor Industry

Jul 8, 2019

Data Center Insider Article: What Is RISC? And What Is CISC?

Jul 8, 2019

EE Times Japan Article: China Where RISC-V Utilization Has Begun To Make It’s Mark

Jul 3, 2019

CNX Software Article: GAPPoc AI Development Boards Based On The GAP8 RISC-V Chip

Jul 3, 2019

Tom’s Hardware Article: Deep Dive – Nvidia Inference Research Chip Scales To 32 Chiplets

Jul 3, 2019

EDN China Article: Create A Custom Processor With RISC-V

Jul 2, 2019

SiFive Expands DesignShare IP Ecosystem To 20 Partner Companies

Jul 2, 2019

Tom’s Hardware Article: India's First CPUs Are Ready For App Development

Jul 2, 2019

Electronics Weekly Article: SiFive Adds IP To DesignShare Ecosystem

Jul 2, 2019

EET China Article: NXP – Cross-Border Products, Double-Sided Attributes

Jul 2, 2019

My Drivers Article: India's First CPU Turned Out: Eight Series Of Software Development Started

Jul 2, 2019

Notebookcheck Article: India Is Ready To Test Its Own Line Of RISC-V Desktop CPUs

Jul 2, 2019

Phoronix Article: Longtime X11/Linux Developer Joins SiFive To Work On RISC-V Processors

Jul 1, 2019

SemiDrive Technology Officially Became A Member Of The RISC-V Foundation

Jul 1, 2019

EET Taiwan Article: Andes Technology Launches RISC-V CPU FreeStart Project

Jul 1, 2019

Sohu Article: What Is China's Largest Integrated Circuit Design Company?

Jul 1, 2019

Andes Technology And Silex Insight Announce Strategic Partnership For RISC-V Based Root-Of-Trust IP Solutions

Jun 28, 2019

Linux Addicts Article: The Servers With Chips Based On The ISA RISC-V Could Arrive Soon

Jun 28, 2019

Newspaper Business Forum Article: US Startup Chips "Circumvent The Law" To Help China Design The Chip Itself

Jun 28, 2019

Sohu Article: Jianan Generation AI Chip Surveying K210 Power Consumption Is Only 0.3W To Accelerate The Lightweight Of Domestic AIOT Architecture

Jun 28, 2019

Mydrivers Article: Open Source Instruction Set RISC-V Progress Fast: 2 Years Into The Mobile Phone Market, 5 Years Into The Server Market

Jun 28, 2019

EEFOCUS Article: Andes Technology Launches RISC-V FreeStart Program With Its Commercial-Grade CPU N22

Jun 27, 2019

Semiconductor Engineering Article: Enabling The RISC-V Ecosystem

Jun 27, 2019

MONOist Article: Launches RISC-V RTOS, Helps Improve IoT Equipment Performance And Price

Jun 27, 2019

Semiconductor Engineering Article: Open Source Processors: Fact Or Fiction?

Jun 26, 2019

Bit-Tech Article: SiFive CEO Predicts RISC-V Smartphones, Servers Within Five Years

Jun 26, 2019

NanoSemi Relies On OneSpin Automated Formal Verification Tools To Verify SystemC Designs For 5G ASICs

Jun 26, 2019

Semiconductor Engineering Article: Complete Formal Verification Of RISC-V Processor IPs For Trojan-Free Trusted ICs

Jun 26, 2019

IT BizNews Article: "Future Semiconductor Market Will Depend On Chip Diversity, Not Micro-Process Technology"

Jun 26, 2019

Elektroniknet.de Article: 32 Bit RISC Processor With 2.5 μW / MHz

Jun 26, 2019

Tech News Article: Look At The Prospects Of China's RISC-V! SiFive: I Have Set Up An Independent Company In China To Sprint

Jun 26, 2019

EENews Europe Article: Fully-Integrated Wi-Fi Solution Connects To Alibaba Cloud

Jun 25, 2019

EE Times Article: UltraSoc Gets £5M For Hardware-Level Cybersecurity

Jun 25, 2019

CEVA Introduces Fully-Integrated Wi-Fi Solution To Connect IoT Devices To The Alibaba Cloud

Jun 25, 2019

China Times Article: Grab The Commercial Market, Andes Technology, Push RISC-V New Product N22

Jun 25, 2019

UDN Article: Andes Technology Adopts The Initial Authorization Method To Push RISC-V New Products

Jun 25, 2019

Data Center Knowledge Article: SiFive CEO Says RISC-V Servers Are 'Five Years Away'

Jun 24, 2019

Western Digital Extends Openness Of PlatformIO And Enhances Its RISC-V Portfolio To Accelerate Data-Centric Innovation

Jun 24, 2019

Monoist Article: Open Source Processor IP "SweRV Core" Expands Performance And Development Environment

Jun 24, 2019

all-electronics.de Article: Western Digital Extends Its RISC V Portfolio

Jun 24, 2019

Pulse 2.0 Article: How SiFive Helps SoC Designers Reduce Time-To-Market And Find Cost Savings

Jun 21, 2019

SemiInsights Article: What Does RISC-V Mean For The Chip Industry?

Jun 21, 2019

China Electronics News Article: ARM Needs A Competitor, Will RISC-V Dominate Future Computing?

Jun 21, 2019

OpenHW Group Created And Announces CORE-V Family Of Open-Source Cores For Use In High Volume Production SoCs

Jun 21, 2019

Mynavi Article: Western Digital Enhances Its Own RISC-V Core "SweRV RISC-V Core"

Jun 21, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Jun 21, 2019

Packt Article: Debian GNU/Linux Port For RISC-V 64-Bits: Why It Matters And Roadmap

Jun 20, 2019

Silicon Hill News Article: SiFive Opens Austin Office

Jun 20, 2019

Electronics Weekly Article: Western Digital Extends RISC-V Involvement

Jun 20, 2019

Evertiq Article: SiFive Expands With Second Location In Austin, Texas

Jun 19, 2019

NotebookCheck Article: Perf-V: An FPGA Based RISC-V Developer Board, Which Costs US$79

Jun 19, 2019

SiFive Enhances Silicon Hills Operations With Office In Austin, Texas

Jun 19, 2019

all-electronics.de Article: Raven: X-Fab And Efabless Have Developed RISC-V-SoC

Jun 19, 2019

all-electronics.de Article: Solution To Ensure The Integrity Of RISC V Core

Jun 18, 2019

Embedded Insiders Podcast: Does The OpenHW Group Make RISC-V Real?

Jun 18, 2019

Western Digital Blog Post: OmniXtend™ Cache-Coherent Fabric Drives Innovation With RISC-V

Jun 18, 2019

CHIPS Alliance Builds Momentum And Community With Newest Members Imperas Software And Metrics

Jun 18, 2019

Kai Xian TV Article: Will RISC-V Dominate Future Computing?

Jun 18, 2019

The Next Platform Article: Europe Will Enter Pre-Exascale Realm With Marenostrum 5

Jun 18, 2019

Zephyr Project Blog Post: Zephyr RTOS Featured In RISC-V Getting Started Guide

Jun 17, 2019

jqknews Article: Turing Award Winners Lead Tsinghua And Berkeley To Build RISC-V International Open Source Laboratory

Jun 17, 2019

cnBeta Article: Berkeley And Tsinghua Establish RIOS Laboratory; RISC-V Is Expected To Upgrade To The Most Advanced Level

Jun 17, 2019

ScienceNet Article: Turing Award Winners Build RISC-V International Open Source Lab

Jun 17, 2019

KIPOST Article: Open Source Architecture RISC-V At A Glance … Cy5 Five Technology Symposium

Jun 17, 2019

My Drivers Article: NVIDIA Also Looks At The RISC-V Architecture: Incorporating Deep Neural Network Accelerators

Jun 17, 2019

EE Times Article: X-FAB And Efabless Deliver Open Source Mixed-Signal SoC

Jun 17, 2019

Phoronix Article: The State Of RISC-V For Debian 10 "Buster"

Jun 17, 2019

EETimes On Air: Risking RISC-V, Engineers & The Gig Economy, Chiplets

Jun 17, 2019

EE Times Article: RISC-V Moving Beyond Academia, New Group Offers Hardened SoCs

Jun 17, 2019

CNX Software Article: Perf-V Is Another FPGA Based RISC-V Development Board

Jun 14, 2019

Embedded Computing Design Article: X-FAB, Efabless Release First Silicon of “Raven” RISC-V SoC

Jun 14, 2019

EENews Europe Article: X-FAB Silicon Foundries Tapes-Out Open-Source RISC-V MCU

Jun 14, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Jun 14, 2019

Leiphone Article: Berkeley Hands In Tsinghua To Set Up RIOS Laboratory, RISC-V Is Expected To Upgrade To The Most Advanced Level?

Jun 14, 2019

EEFocus Article: Huami Technology: Huangshan No. 1 Chip Is Currently Using The Future Or Open Cooperation

Jun 14, 2019

Sina Article: Qualcomm Invests Heavily In RISC-V Companies

Jun 13, 2019

RISC-V Workshop Zurich Proceedings

Jun 12, 2019

TechRadar Article: Security Is Now A Board Level Issue: How To Secure The Data Supply Chain

Jun 12, 2019

EET India Article: Embedded Benchmark Needs Support

Jun 12, 2019

EETimes Article: Andes Technology Launches FreeStart To Boost RISC-V Adoption

Jun 12, 2019

all-electronics.de Article: OpenHW Group Develops Open Source Cores For SoCs

Jun 12, 2019

Sohu Article: Huami's Huangshan No. 1 Chip Started Commercial! Launched Two New Smartwatches

Jun 12, 2019

Elektroniktidningen Article: The Future Of RISC-V From The Creator's Perspective

Jun 11, 2019

Imperas And Metrics Collaborate To Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator

Jun 11, 2019

Elektroniktidningen Article: New Forum For Open Hardware

Jun 11, 2019

Elektroniktidningen Article: Taiwanese Risc-V With Extras

Jun 11, 2019

New Electronics Article: SiFive Attracts Strong Venture Backing Raising $65M

Jun 11, 2019

RISC-V Foundation Announces Call for Papers for the 2nd Annual RISC-V Summit

Jun 10, 2019

The Next Platform Article: Europe's Homegrown HPC Compute Begins To Take Shape

Jun 10, 2019

Andes Technology Launches RISC-V FreeStart Program With Its Commercial-Grade CPU N22

Jun 10, 2019

EETimes Article: Qualcomm Takes Stake in SiFive

Jun 10, 2019

HPCwire Article: Qualcomm Invests In RISC-V Startup SiFive

Jun 7, 2019

Golem Article: European Initiative Wants Its Own ARM And RISC-V CPUs

Jun 7, 2019

KIPOST Article: Received Orders For 101 SiFive And RISC-V Processor Cores

Jun 7, 2019

Tom's Hardware Article: European Processor Initiative Delivers First Designs

Jun 7, 2019

SiFive Secures $65.4 Million In Series D Funding

Jun 7, 2019

SiFive Celebrates Historic 100 Design Win Milestone

Jun 6, 2019

IT Leaders Article: Real-Time OS "TOPPERS-Pro / ASP" Supports RISC-V, Provided By Ubiquitous AI

Jun 6, 2019

CIO Article: Western Digital Is Fast Moving To Being A Data Infrastructure Company: Stephen Milligan

Jun 6, 2019

EE Times Article: Side-Channel Attacks On Embedded Processors

Jun 6, 2019

Electronics Weekly Article: OpenHW To Boost Adoption Of Open Source Processors

Jun 6, 2019

Imperas Delivers First RISC-V Simulator For New Vector And Bit Manipulation Specifications To Lead Customers

Jun 6, 2019

OpenHW Group Created and Announces CORE-V Family of Open-Source Cores for Use in High Volume Production SoCs

Jun 5, 2019

The Register Article: HPC Processor Project Tosses Architectural Designs On Desk Of The European Commission

Jun 5, 2019

TechNews Article: The EU Is Progressing With The Processor For A European Supercomputer

Jun 5, 2019

Phoronix Article: Libre RISC-V Snags $50k EUR Grant To Work On Its RISC-V 3D GPU Chip

Jun 5, 2019

Get Ready for the RISC-V Workshop Zurich!

Jun 4, 2019

Sa.ylib Article: The Last Glimpse of Open Source: RISC-V Processor

Jun 4, 2019

Tweakers Article: NLNet Supports Open Source RISC-V-SoC And GPU For Mobile Devices

Jun 4, 2019

Andes Technology Corp. Senior VP, Emerson Hsiao To Be Panelist For “Open Source ISAs – Will The IP Industry Find Commercial Success?” At DAC 2019 In Las Vegas

Jun 4, 2019

Data Center Dynamics Article: European Processor Initiative Delivers First Architectural Designs To The European Commission

Jun 4, 2019

Electronics Weekly Article: SiFive Hooks Up With Avatar For Physical IP

Jun 3, 2019

GreenWaves Technologies Named A 2019 “Cool Vendor” in AI Semiconductors By Gartner

Jun 3, 2019

Golem Article: Internet PIONEERS Fund Work On Free RISC V-SoC

Jun 3, 2019

cnBeta Article: UW Technology Introduces World's First PD Plus Controller Chip with Integrated RISC-V Core

May 30, 2019

Semiconductor Engineering Article: Why IP Quality Is So Difficult To Determine

May 30, 2019

Getting Started with RISC-V China Roadshow Proceedings

May 29, 2019

Pixilica Licenses SiFive's RISC-V Embedded Processor IP

May 29, 2019

ZDNet Korea Article: KunTech, 30-Day Open Source Processor Design Methodology Seminar

May 29, 2019

Semico Announces Agreement with RISC-V Foundation for RISC-V Research Report

May 28, 2019

EEPW Article: The RISC-V Ecosystem Is In Its Infancy And Developers Are Welcome To Adopt, Share And Improve

May 28, 2019

Elektronik Article: RISC V Processor Cores Or Compliance

May 28, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

May 28, 2019

Data Center Knowledge Article: Companies Pushing Open Source RISC-V Silicon Out To The Edge

May 28, 2019

Hackaday Article: New Part Day: A 64-Bit RISC-V CPU In Raspberry Pi Hat Form

May 28, 2019

Hex Five Adds MultiZone™ Security To The AdaCore Software Ecosystem

May 24, 2019

EET Taiwan Article: Open Hardware To Help Procurement Work

May 24, 2019

Elektroniktidningen Article: Premiere For IAR's RISC-V Compiler

May 23, 2019

Root.CZ Article: SiFive RISC-V Chips Can Be Paired With PowerVR GPUs

May 23, 2019

ESM China Article: The European And American Open Source Community Complains That China Contributes Less, And The Head Said That This Is A Prejudice

May 23, 2019

Electronics Weekly Article: Toolchain Supports RISC-V Cores

May 23, 2019

OneSpin’s Newest App Assures Quality Of RISC-V Processor Cores For Safety-, Security-Critical Applications

May 23, 2019

AnandTech Article: SiFive Acquires USB 2.0 And 3.x IP Portfolio To Strengthen RISC-V SoCs

May 22, 2019

RISC-V Sessions at DAC 2019 in Las Vegas

May 22, 2019

IAR Systems Takes RISC-V To The Next Level With Launch Of Professional Development Tools With Leading Performance And Ensured Code Quality

May 22, 2019

eeNews Europe Article: C/C++ Compiler And Debugger Toolchain Supports RISC-V Cores

May 22, 2019

Innovative Logic USB IP Portfolio Strengthens RISC-V Ecosystem

May 22, 2019

CNX Software Article: Maixduino SBC Combines RISC-V AI, Arduino Form Factor, And ESP32 Wireless Module

May 22, 2019

Antmicro Launches Renode 1.7 With TSN, PTP Support, PicoRV32, Murax SoC

May 21, 2019

IT Biz News Article: Open Source Chip Design Architecture, Pay Attention To 'RISC-V'!

May 21, 2019

Electronic Products World Article: RISC-V + IoT OS! Zhongke Lanxun And RT-Thread Strategically Cooperate To Promote The Ecological Development Of Autonomous Internet Of Things

May 20, 2019

Techzine Article: Google Bets On Open Source Chips

May 17, 2019

SemiInsights Article: What Do You Think About RISC-V?

May 17, 2019

EET China Article: SoC Chip Design Focuses On The "Invisible Champion" Of Security IP

May 17, 2019

EET Taiwan Article: Open Source RISC-V Is Becoming The Future Of Hardware Design

May 17, 2019

lowRISC Expands And Appoints New Members To The Board Of Directors From Google And ETH Zurich

May 17, 2019

Elektronik Praxis Article: Rigid RISC-V CPU: New Chip Stops Attacks Before They Start

May 17, 2019

Google Blog Post: Google Fosters The Open Source Hardware Community

May 17, 2019

Bit-Tech Article: Google Extends lowRISC FOSSi Partnership

May 16, 2019

PULP Platform Partners With GreenWaves, Bitcraze For RISC-V AI Drone Controller

May 15, 2019

All Electronics Article: Embedded Design: What Innovations RISC-V Leads To

May 15, 2019

An Introduction To The RISC-V-Based SweRV Core

May 15, 2019

UltraSoC Blog Post: The RISC-V Ecosystem Has Many Layers

May 13, 2019

All Electronics Article: Onespin Joins The RISC-V Foundation

May 13, 2019

Seeed Studio Opens Pre-Orders For RISC-V-Based Grove AI HAT Board

May 13, 2019

Phoronix Article: GDB 8.3 Debugger Brings RISC-V, Terminal Styling, C++ Injection, IPv6 Connections

May 13, 2019

PowerVR GPU And NNA Available On SiFive Platform

May 11, 2019

Verification Challenges for RISC-V Adoption | OneSpin

May 10, 2019

Elektronik Article: RISC V Workshop At ETH Zurich

May 10, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

May 9, 2019

Wccftech Article: University Of Michigan May Have Developed First Unhackable Processor

May 9, 2019

LinuxGizmos.com Article: Latest Grove Add-On For The Pi Includes RISC-V NPU For Edge AI Duty

May 9, 2019

Geeky Gadgets Article: Raspberry Pi Grove AI HAT For Edge Computing $24

May 9, 2019

ElectronicsWeekly Article: Raspberry Pi HAT Brings RISC-V, AI, Edge Computing

May 8, 2019

ElectronicsWeekly Article: UltraSoC Adds Cycle-Accurate Trace To Analytics Capability

May 8, 2019

Elektronik Praxis Article: RISC-V Foundation Continues To Grow: OneSpin Introduces Key Integrity Checking Tool

May 8, 2019

TechRepublic Article: $25 Raspberry Pi Add-On Gets You Started With Edge Computing AI

May 8, 2019

Leiphone Article: What Is One Of The Keys To The Rapid Introduction Of RISC-V Processors In Western Digital?

May 8, 2019

Embedded Computing Design Podcast: Five Minutes With…Calista Redmond, CEO, RISC-V

May 8, 2019

Media Alert: SiFive Tech Symposiums On RISC-V Coming To Europe This Month

May 8, 2019

Michigan News Article: Unhackable: New Chip Stops Attacks Before They Start

May 8, 2019

Embarcados Webinar: An Introduction To RISC-V ISA And Its Ecosystem

May 7, 2019

EDN China Article: Why Is Cycle-Accurate Tracking Important In SoC Design?

May 7, 2019

OneSpin Joins The RISC-V Foundation

May 7, 2019

Cycle-Accurate Trace Boosts Performance Optimization Capabilities Of UltraSoC Embedded Analytics Infrastructure

May 7, 2019

Evertiq Article: SiFive Expands Into Portland Area’s Silicon Forest

May 6, 2019

Fudzilla Article: Boffins Claim To Have Invented Unhackable Chip

May 6, 2019

CNX Software Article: Linux 5.1 Release – Main Changes, Arm, MIPS And RISC-V Architectures

May 6, 2019

Hackster.io Article: Now On GroupGets: RISC-V LoFive R1

May 6, 2019

Codasip Presence At Upcoming Events: China Roadshow, DAC 2019, And RISC-V Workshop Zurich

May 3, 2019

Bit-tech Article: Researchers Unveil 'Unhackable' Morpheus Processor

May 2, 2019

Tech Xplore Article: New Chip Stops Attacks Before They Start

May 1, 2019

SiFive Expands Into Silicon Forest With New Development Office In Beaverton, Oregon

Apr 30, 2019

Electronics360 Article: Four Reasons To Use RISC-V For Aerospace And Defense Applications

Apr 30, 2019

The Linley Group Article: Cortus FPS69V Uses 64-Bit RISC-V

Apr 30, 2019

RISC-V Foundation Kündigt Agenda Für RISC-V Workshop In Zürich An

Apr 30, 2019

RISC-V Foundation Announces Agenda For RISC-V Workshop Zurich

Apr 29, 2019

Stacey On IoT Article: IoT News Of The Week For April 26, 2019

Apr 26, 2019

SiFive Announces Strategic Partnership With QuickLogic And Launches SoC Templates For Rapid Chip Design

Apr 25, 2019

The Register Article: QEMU 4 Arrives With Toys For Arm Admirers, RISC-V Revolutionaries, POWER Patriots… You Get The Idea

Apr 24, 2019

Qamcom Joins The RISC-V Foundation

Apr 22, 2019

EE Times Article: RISC-V, DARPA Advance Security

Apr 22, 2019

CTIMES Article: Andes Launches First DSP Instruction Set For RISC-V Multi-Core Processors To Challenge The HPC Market

Apr 19, 2019

HiNet Article: This Year's RISC-V New Licensing Contract Is Expected To Double The Growth Of Andes Technology's Annual Revenue And Double-Digit Growth

Apr 19, 2019

Electronics Lab Article: The Maixduino – Sipeed’s New Neural Network Maix-Based Board

Apr 18, 2019

Microchip Technology Video: First RISC-V SoC FPGA For Real-Time With Linux

Apr 18, 2019

Open Hardware Group – CHIPS Alliance – Building Momentum And Community With Newest Member Antmicro

Apr 18, 2019

RISC-V基金会宣布在中国五座城市开展RISC-V免费入门活动

Apr 18, 2019

DesignNews Article: 8 RISC-V Companies To Watch

Apr 18, 2019

Press Release: Open Hardware Group – CHIPS Alliance – Building Momentum And Community With Newest Member Antmicro

Apr 17, 2019

The Linley Group Article: Andes Strengthens Its RISC-V Arsenal

Apr 17, 2019

RISC-V Foundation Announces Free Getting Started With RISC-V Events In Five Cities In China

Apr 16, 2019

Finance Sina Article: Turing Award Winner David Patterson: Dawan District Needs Excellent Talent Open Source System To Help R & D

Apr 16, 2019

TechTarget Article: Open Source Virtualization Expands VM Hardware And OS Options

Apr 16, 2019

Hackster.io Article: Doing Machine Learning From The Arduino Development Environment?

Apr 16, 2019

Decreasing The Length Of Design Cycle In Co-Designed SoCs With Renode

Apr 15, 2019

Western Digital Boasts Of “Gratifying” SweRV Response, Releases FPGA Reference Design

Apr 12, 2019

Prohardver Article: Multi-Sheet Experimental Design Was Designed By NVIDIA To Scale Machine Learning

Apr 12, 2019

China Times Article: Andes Technology Held RISC-V Forum In May To Promote Open Source Instruction Set Architecture

Apr 12, 2019

Electronics Lab Article: SiFive Launches The World’s Smallest Commercial 64-Bit Embedded Core

Apr 12, 2019

Bit-tech Article: Synaptics Announces Shift To RISC-V Processors

Apr 11, 2019

Semiconductor Engineering Article: More Memory And Processor Tradeoffs

Apr 11, 2019

EE Journal Article: When Tubes Were Better Than Transistors

Apr 11, 2019

CNX Software Article: SiFive S2 RISC-V Core May Be The World’s Smallest 64-Bit Embedded Core

Apr 11, 2019

RISC-V Foundation Finalizes Schedule For RISC-V Workshop Zurich

Apr 11, 2019

SiFive Tapes Out First In A Series Of 7nm IP Enablement Platforms

Apr 11, 2019

Shanghai RISC-V Meetup: Bob Hu's RISC-V Chinese Book Signing & RISC-V Meetup

Apr 10, 2019

China Times Article: "Semiconductor" Smart RISC-V ASIC Solution To Promote Mass Production Of AIoT SoC

Apr 10, 2019

Electronic Design Article: Electronic Design Products Of The Week (4/8-4/12)

Apr 10, 2019

SmartDV’s DVCon China Exhibit To Showcase Extensive Verification IP Portfolio

Apr 10, 2019

SiFive Launches The World's Smallest Commercial 64-Bit Embedded Core

Apr 10, 2019

Electronics Weekly Article: Asic Service Offers RISC-V For IoT And AI

Apr 9, 2019

Circuit Cellar Article: RISC-V Processor Family Spans From Low-End To 64-Bit With FPU

Apr 9, 2019

Electronic Design Article: Delivering High Performance RISC-V Platforms

Apr 9, 2019

Elektronik Article: High Demand For RISC V Cores In 2018

Apr 9, 2019

NDSS Symposium Video: NDSS 2019 TIMBER-V: Tag-Isolated Memory Bringing Fine-grained Enclaves to RISC-V

Apr 9, 2019

Western Digital Video: The Future Of Supervisor Binary Interface(SBI) In RISC-V

Apr 9, 2019

Celebrating IoTDay: How RISC-V Enables IoT Innovation

Apr 8, 2019

CNews Article: Basalt SPO Provided Support For The RISC-V Architecture In The Sisyphus Repository

Apr 8, 2019

PCGamesN Article: Nvidia’s 36-Module Research Chip Is Paving The Way To Multi-GPU Graphics Cards

Apr 8, 2019

Andes Records A Rapid Growth Of Design Wins In 2018 For Its New Family Of RISC-V Processor Cores

Apr 5, 2019

Getting Started with RISC-V North America Roadshow Proceedings

Apr 5, 2019

QuickLogic Blog Post: eFPGA And PULP – The Ultimate (Low) Power Couple

Apr 4, 2019

Military & Aerospace Electronics Article: Built-in Trusted Computing And Cyber Security For Complex Digital Chips

Apr 3, 2019

Sohu Article: China's First RISC-V High-Performance Home Appliance Chip Was Born In Qingdao

Apr 3, 2019

VDC Research Article: 5 Key Takeaways From The RISC-V Roadshow In Boston

Apr 2, 2019

SiFive To Present At Leading IP, Processor Conferences

Apr 1, 2019

RISC-V Foundation Announces Agenda for Free, Half-Day Getting Started with RISC-V Events

Apr 1, 2019

Key Priorities for Accelerating the RISC-V Revolution

Mar 29, 2019

EEBoard Article: ESP32 Combined With RISC-V – A New Upgraded Version Of The HiFive1 Rev B Development Board

Mar 29, 2019

Digitized House Article: Future Connected Home Devices Likely To Be Powered By New Processor Architectures

Mar 29, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Mar 28, 2019

eeNews Embedded Video: How RISC-V Can Have Supercomputer Powers

Mar 28, 2019

Linux.com Article: RISC-V Roadshow China

Mar 28, 2019

Keeping RISC-V-Based Embedded System Design Flexible With Linux And Zephyr microPlatforms

Mar 28, 2019

Semiconductor Engineering Article: RISC-V At Embedded World

Mar 27, 2019

Hackster.io Article: Running FreeRTOS On The VEGA RISC-V Board

Mar 27, 2019

Running Hard Real-Time Applications and Linux on PolarFire SoC

Mar 26, 2019

Linux Journal Article: Why We Need Our Nonprofits

Mar 26, 2019

OSnews Article: Digging Into RISC-V

Mar 25, 2019

TechNoticias Article: RISC-V Foundation Hosting World Series RISC-V Introductory Events

Mar 25, 2019

Electronics Lab Article: Grove Hat For Raspberry Pi Features A New RISC-V-Based AI Chip

Mar 25, 2019

RISC-V Foundation Hosting Worldwide Series Of Getting Started With RISC-V Events

Mar 25, 2019

Cortus Announces The General Availability Of A RISC-V Processor Family – From Low End Embedded Controller To 64 Bit Processor With Floating Point

Mar 22, 2019

eeNews Embedded Video: We Can Expect Interesting RISC-V Implementations – EENews Video Interview With Ted Marena

Mar 22, 2019

Bluespec Co-Hosts Captivating Boston RISC-V Technical Symposium

Mar 22, 2019

Elektronik Video: VIP Stage: RISC-V – Fast Growing Innovation Driver

Mar 22, 2019

Elektronik Video: VIP Stage: Making RISC-V The Most Secure Platform Ever

Mar 22, 2019

Elektronik Video: VIP Stage: Enabling AI At The Very Edge

Mar 22, 2019

RISC-V Workshop Zurich

Mar 21, 2019

Kaldata Article: Linux Foundation Has Been Working On Developing Open Source Chips

Mar 21, 2019

Embedded Computing Design Article: Determine Whether RISC-V Should Play A Role In Your Next Design

Mar 21, 2019

How Data-Centric Applications Can Capitalize On RISC-V Processor Innovation

Mar 21, 2019

JoinUp Article: Sweden, Denmark, Estonia, Latvia Join EuroHPC Joint Undertaking

Mar 20, 2019

SemiWiki Article: The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part II

Mar 20, 2019

Moore Core News Article: RISC-V Adds Icing To AI Edge Computing Chip Development

Mar 20, 2019

L'Embarque Article: Andes Adds RISC-V Processor Core To DSP Instruction Set

Mar 20, 2019

How To Utilize The RISC-V Instruction Set CKB-VM

Mar 19, 2019

SemiWiki Article: The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part I

Mar 19, 2019

Phoronix Article: SiFive Rolls Out RISC-V HiFive1 Rev B Development Platform, $49 USD With FE310-G002 SoC

Mar 19, 2019

TechRepublic Article: Start Developing For RISC-V With The $49 HiFive1 Revision B

Mar 19, 2019

Media Alert: OneSpin Solutions To Feature RISC-V Integrity Verification Solution At GOMACTech

Mar 19, 2019

Elektronik Article: New CEO Comes From IBM

Mar 19, 2019

Embedded Computing Design: Determine Whether RISC-V Should Play a Role in Your Next Design

Mar 19, 2019

EEVBlog2 Video: NES On A 64Bit RISC-V Sipeed MAIX

Mar 19, 2019

Andes Technology Strengthens The RISC-V EasyStart Alliance To 15 ASIC Design Service Partners

Mar 19, 2019

EETimes Japan Article: More And More Groups Are Set Up For Open Hard Development

Mar 19, 2019

News.hqew Article: "AI+IoT" Integration Scheme Has Its Advantages And Disadvantages. MCU Generalization And Specificity Are Difficult To Balance

Mar 19, 2019

Hackster.io Article: The Return Of The RISC-V HiFive1

Mar 19, 2019

ElE Times Article: CPU Soft IP For FPGAs Delivers HDL Optimization And Supply Chain Integrity

Mar 18, 2019

RISC-V Workshop Taiwan Proceedings

Mar 15, 2019

RISC-V Foundation Announces Agenda For Free, Half-Day Getting Started With RISC-V Events

Mar 15, 2019

Enginnering.com Article: Electronics Weekly – Cadence Silicon-Proven IP System, RS Components Interconnectivity Series And More

Mar 15, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Mar 15, 2019

eSpeak Article: Run A Micropython NES Emulator On RISC-V Dev Boards

Mar 15, 2019

Moore Core News Article: In The Internet Of Things Era, RISC-V Architecture Leads The New Trend

Mar 15, 2019

Geeky Gadgets Article: HiFive1 Rev B Wireless Open Source RISC-V Development Platform

Mar 14, 2019

Elektroniktidningen Article: The Linux Foundation Adopts RISC-V

Mar 14, 2019

Calista Redmond Named As RISC-V Foundation CEO

Mar 14, 2019

LinuxGizmos Article: Multi-Core, Linux-Ready RISC-V Cores Feature DSP

Mar 14, 2019

insideHPC Article: Calista Redmond Named CEO Of RISC-V Foundation

Mar 14, 2019

SDxCentral Article: Intel, Linux Foundation Launch Open Source Silicon Groups

Mar 14, 2019

Hackaday Article: NES On RISC-V

Mar 13, 2019

EET Taiwan Article: Small RISC-V Core Targets Embedded And Entry-Level MCU Applications

Mar 13, 2019

TechNews Article: China Actively Develops Its Own CPU, Can RISC-V Assist?

Mar 13, 2019

All Electronics Article: Ex-IBM Manager Calista Redmond Becomes CEO Of RISC-V-Foundation

Mar 13, 2019

Elektronik Article: Calista Redmond Becomes New CEO

Mar 13, 2019

Crowd Supply Article: HiFive1 Rev B

Mar 13, 2019

CKB-VM As A RISC-V Instruction Set: Inspiration, Design, And Benefits

Mar 12, 2019

FierceWireless Article: Open Source Silicon Project Innovates Chips In Communications Networks

Mar 12, 2019

EET China Article: RISC-V Brought To China, Not A High-Rise Rendering

Mar 12, 2019

Silicon Republic Article: All Aboard The Compute Express: Intel Forges New Cloud Chip Pact

Mar 12, 2019

EE Times Article: Intel, RISC-V Rally Rival Groups

Mar 12, 2019

Linux Foundation To Host CHIPS Alliance Project To Propel Industry Innovation Through Open Source Chip And SoC Design

Mar 12, 2019

Electronics Weekly Article: One I Missed: Ultra-Low-Power Multi-Core RISC-V At ETH Zurich

Mar 12, 2019

Andes Technology Announces RISC-V Single-Core And Multicore Processors With DSP Instruction Set

Mar 12, 2019

VentureBeat Article: Node.js And JS Foundations Are Merging To Form OpenJS

Mar 12, 2019

Bit-tech Article: Linux Foundation Launches FOSSi-Focused CHIPS Alliance

Mar 12, 2019

Fossbytes Article: The Linux Foundation Announces CHIPS Alliance To Open-source Chip Designs

Mar 12, 2019

The RISC-V Foundation Appoints Calista Redmond As Chief Executive Officer

Mar 11, 2019

Andes And SEGGER Partner To Deliver Professional Development Solutions For RISC-V

Mar 11, 2019

ZDNet Article: Open Source Advances Deeper Into Hardware: The CHIPS Alliance Project

Mar 11, 2019

Hackaday Article: Hackaday Links: March 10, 2019

Mar 11, 2019

Elektronik Article: From The Basics To The Prototype

Mar 11, 2019

Pro-Linux Article: Report From The Plasma Mobile Sprint In Berlin

Mar 11, 2019

Sohu Article: Core Interconnect Technology Develops RISC-V IP Core, MCU General-Purpose Chip Developed Successfully

Mar 8, 2019

ChinaNews Article: One Year Invested In Several Semiconductor Companies Neglected Wal-Mart "Core" Layout

Mar 8, 2019

IT Toolbox Article: AWS Amplify Console Now Supports Instant CDN Cache Invalidation

Mar 8, 2019

Phoronix Article: RISC-V's Linux Kernel Support Is Getting In Better Shape, Maturing On HiFive Unleashed

Mar 8, 2019

Hackster.io Article: A New RISC-V-Based AI HAT For The Raspberry Pi From Seeed Studio

Mar 8, 2019

Taiwan News Article: RISC-V Taiwan Established To Herald Era Of AIoT, 5G Networks

Mar 7, 2019

Codasip To Demonstrate Technology Leadership And Commitment To Open Standards At Taiwan RISC-V Workshop

Mar 7, 2019

Semiconductor Engineering Article: Next Wave Of Security For IIoT

Mar 7, 2019

CTimes Article: Layout Of The AIOT Era Taiwan RISC-V Alliance Officially Started On The 7th

Mar 7, 2019

EET Asia Article: Edge Intelligence The Focus At Embedded World

Mar 7, 2019

Embedded Insiders Podcast: Five Minutes With…Quentin Ochem, Director, AdaCore

Mar 6, 2019

EE Journal Article: RISC-V Business

Mar 6, 2019

SemiWiki Article: A Preview Of Spring Symposium On AIoT

Mar 6, 2019

Electronica AZI Article: Double Telemetry Support To Reduce The Cost Of Satellite Services

Mar 6, 2019

Elektronik Article: Embedded World With Significantly More Exhibitors

Mar 6, 2019

Semi Insights Article: RISC-V CON Shanghai, Shenzhen Debut In March To Focus On The Latest Developments In RISC-V

Mar 6, 2019

CNX Software Article: FreeRTOS Kernel Now Supports RISC-V Architecture

Mar 6, 2019

Semiconductor Engineering Article: The Other Side Of Makimoto’s Wave

Mar 6, 2019

Hackaday Article: Google Launches AI Platform That Looks Remarkably Like A Raspberry Pi

Mar 5, 2019

DVCon U.S. 2019 Announces Stuart Sutherland Best Paper And Best Poster Winners, Attendance Numbers

Mar 5, 2019

Esperanto Technologies Appoints Nick Aretakis As VP Of Sales And Marketing

Mar 5, 2019

CNMO News Article: RISC-V Is Free To Use And Is Intended To Break The Monopoly Of The Processor Market

Mar 5, 2019

Introduction To The RISC-V Instruction Set CKD-VM And Its Requirements

Mar 4, 2019

Video Interview with Andes Technology at Embedded World 2019

Mar 4, 2019

Video Interview with GreenWaves Technologies at Embedded World 2019

Mar 4, 2019

Video Interview with UltraSoC at Embedded World 2019

Mar 4, 2019

Video Interview with SiFive at Embedded World 2019

Mar 4, 2019

Video Interview with Imperas at Embedded World 2019

Mar 4, 2019

Video Interview with CloudBEAR at Embedded World 2019

Mar 4, 2019

Video Interview With Syntacore At Embedded World 2019

Mar 4, 2019

Blocks & Files Article: Western Digital Wants To Be The Everything Storage Company. How Does Its Ambition Stack Up?

Mar 4, 2019

Hackaday Article: Hackaday Links: March 3, 2019

Mar 4, 2019

CNX Software Article: Linux 5.0 Release – Main Changes, Arm, MIPS And RISC-V Architectures

Mar 4, 2019

ZDNet Article: RISC-V Opens Up Processor Design

Mar 1, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Mar 1, 2019

Stacey On IoT Article: IoT News Of The Week For March 1, 2019

Mar 1, 2019

iThome Article: IoT Operating System Amazon FreeRTOS Core Now Supports RISC-V Instruction Set Architecture

Mar 1, 2019

Elektroniktidningen Article: Fault Tolerant RISC-V From Gothenburg

Mar 1, 2019

Bit-tech Article: SiFive Hires Intel Capital's Hiren Majmudar

Mar 1, 2019

Business Insider Article: 19 Open Source Software-Related Startups That Will Blow Up In 2019, According To VCs

Mar 1, 2019

EE Times Article: Wearables Firm Invests $8 Million In RISC-V Startup

Feb 28, 2019

Electronics Weekly Article: Embedded World: Trinamic Chooses RISC-V For Intelligent Motor Driver Chip

Feb 28, 2019

Semiconductor Engineering Article: The Challenge Of RISC-V Compliance

Feb 28, 2019

SiFive Welcomes Former Intel Corporate VP To Executive Team

Feb 28, 2019

Semiconductor Engineering Article: Formal Verification Of RISC-V Cores

Feb 28, 2019

Semiconductor Engineering Article: The Rapid Rise Of RISC-V

Feb 28, 2019

Semiconductor Engineering Article: Hot Technologies In Cold Weather

Feb 28, 2019

Elektroniktidningen Article: RISC-V In Motor Control Circuit

Feb 27, 2019

SemiWiki Article: eSilicon Expands Expertise In 7nm

Feb 27, 2019

Phoronix Article: Amazon Adds RISC-V Support To FreeRTOS

Feb 27, 2019

Elektroniktidningen Article: Imagination Technologies Develops RISC-V Processor

Feb 27, 2019

CCIDnet Article: Is RISC-V Getting Better Opening Into The Mainstream Market?

Feb 27, 2019

ASW Blog Post: RISC-V Support In The FreeRTOS Kernel

Feb 27, 2019

IT Toolbox Article: AWS’s RISC-V Support Now Available For FreeRTOS Kernel For Creating IoT Applications

Feb 26, 2019

The Next Platform Article: On-Chip Wizardry To Optimize Performance At Scale

Feb 26, 2019

Electronics Weekly Article: Embedded World: UltraSoC Demos New IDE

Feb 26, 2019

Elettronica News Article: IAR Systems Focuses On IoT Security, Functional Safety And RISC-V

Feb 26, 2019

Imagination And Andes Collaborate To Enable Ultra-Low Power Connected Microprocessors For IoT

Feb 26, 2019

Cobham Joins RISC-V Foundation

Feb 25, 2019

RISC-V Workshop Taiwan Agenda

Feb 25, 2019

Electronics Point Article: RISC-V’s Ted Marena Discusses His Career And The Benefits Of An Open Set Architecture

Feb 25, 2019

Hex Five And wolfSSL Announce The First Secure IoT Stack For RISC-V

Feb 25, 2019

Phoronix Article: RISC-V Support Added To The GRUB Bootloader

Feb 25, 2019

ZDNet Article: Open Source AI Chips Making Green Waves: Bringing Energy Efficiency To IoT Architecture

Feb 25, 2019

DinoplusAI Partners With SiFive To Develop Mission-Critical AI Processor Platform For High Performance Processing With Ultra-Low Latency

Feb 22, 2019

UltraSoC Announces Support For Western Digital RISC-V SweRV Core And OmniXtend Cache-Coherent Interconnect

Feb 22, 2019

Media Alert: RISC-V Comes To DVCon

Feb 22, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Feb 22, 2019

Electronics Weekly Article: UltraSoC Supports RISC-V SweRV Core

Feb 22, 2019

SemiWiki Article: The RISC-V Revolution Is Going Global!

Feb 21, 2019

Bluespec To Co-Host SiFive Technical Symposium

Feb 21, 2019

OneSpin Launches First Formal RISC-V Integrity Verification Solution

Feb 21, 2019

EE Times Article: UltraSoC Extends Monitoring To ‘See’ Into Complex ML, AI Chips

Feb 21, 2019

RISC-V Foundation Announces 2019 “Getting Started with RISC-V” One-Day Events Roadshow

Feb 20, 2019

Monoist Article: New Open Source Innovation To Promote RISC-V Development

Feb 20, 2019

Root.cz Article: Western Digital Has Released Its RISC-V SweRV Processor As Open Source

Feb 20, 2019

WCH Adds Upcoming RISC-V Bluetooth LE Microcontroller To CH57x Family

Feb 20, 2019

RISC-V Workshop Zurich Call For Speakers Now Open

Feb 20, 2019

RISC-V Foundation Membership Exceeds 100 Percent Growth Over The Past Year

Feb 19, 2019

RISC-V Foundation Announces Call for Speakers for RISC-V Workshop Zurich

Feb 19, 2019

EE Times Article: RISC-V Eases Innovation In Military/Aerospace Designs

Feb 19, 2019

Elektronik Article: Ultra Low Power Processor With RISC-V IoT Processor For AI Applications

Feb 19, 2019

Elektronik Article: Open Source Hardware RISC-V The Way To Industrial Application

Feb 19, 2019

Elektronik Article: Open Source Hardware RISC-V Ready For Series Production

Feb 19, 2019

Phoronix Article: Libre RISC-V GPU Aiming For 2.5 Watt Power Draw Continues Being Plotted

Feb 19, 2019

EE Times Japan Article: RISC-V Interest Is High But Presents A Barrier To Popularization

Feb 19, 2019

Andes Technology Records 1 Billion SoC Shipments In 2018 Containing Its CPU IP And 3.5 Billion Since Inception

Feb 19, 2019

ExtremeTech Article: Western Digital’s RISC-V ‘Swerv’ Core Now Available For Free

Feb 19, 2019

Electronics Weekly Article: UltraSoc Adds Features To On-Chip Analytics

Feb 19, 2019

EE Times On Air Podcast: Weekly Briefing: February 15, 2019

Feb 19, 2019

RISC-V E-Newsletter Winter 2019

Feb 15, 2019

UltraSoC Extends On-Chip Analytics Architecture For The Age Of Machine Learning, Artificial Intelligence And Parallel Computing

Feb 15, 2019

GOWIN Semiconductor To Participate At Embedded World 2019

Feb 15, 2019

AnandTech Article: Western Digital's RISC-V "SweRV" Core Design Released For Free

Feb 15, 2019

Hackaday Article: New Part Day: A RISC-V CPU For Eight Dollars

Feb 15, 2019

EBN Article: Open Source Hardware Benefits Procurement Practices

Feb 15, 2019

EE Times Article: SiFive Sees Big Year For RISC-V

Feb 15, 2019

EE Times Article: RISC-V Climbs Software Mountain

Feb 15, 2019

EDN Article: Creating A Custom Processor With RISC-V

Feb 15, 2019

EE Times Article: RISC-V On The Verge Of Broad Adoption

Feb 15, 2019

Military And Aerospace Electronics Article: AdaCore And NVIDIA Team On Ada And SPARK Programming Languages For Safety-Critical Software

Feb 15, 2019

RISC-V基金会公布RISC-V台湾地区研讨会日程

Feb 15, 2019

RISC-V基金會公佈RISC-V臺灣地區研討會議程

Feb 15, 2019

Stacey On IoT Article: Episode 203: Amazon’s Eero Buy And RISC-V

Feb 15, 2019

OpenSourceForU.com Article: How Open Source Technologies Accelerate Innovation

Feb 13, 2019

SiFive To Host Over 50 RISC-V Technology Symposia Throughout The World

Feb 13, 2019

Hackaday Article: Western Digital Releases Their RISC-V Cores To The World

Feb 12, 2019

RISC-V Foundation Announces Agenda For RISC-V Workshop Taiwan Region

Feb 12, 2019

Elektroniikkalehti Article: Efficiency In Telemetry And Cost Of Satellite Services Down

Feb 12, 2019

CNX Software Article: ARIES M100PF PolarFire FPGA System-On-Module Targets Industrial Applications, RISC-V Development

Feb 12, 2019

EEWorld Article: AdaCore Expands RISC-V Ecosystem

Feb 12, 2019

Andes Technology Corp. Targets Deeply Embedded Protocol Processing And Entry-Level MCUs With The New N22, The Smallest RISC-V Core In Its V5 Family

Feb 12, 2019

Hackster.io Article: You Can Now Build a RISC-V PC That Runs Fedora Linux

Feb 12, 2019

SecureRF Blog Post: Will Enterprise Prioritize IoT Security Over Innovation In 2019?

Feb 12, 2019

eeNews Embedded Article: The Value Is In The Data. eeNews Interview With Martin Fink, CTO Of Western Digital At The RISC-V Workshop

Feb 12, 2019

FOSDEM Video: Lessons Learned From Porting HelenOS To RISC-V Pros Cnd Cons Of RISC-V From A Microkernel OS Point …

Feb 11, 2019

Commercial Times Article: RISC-V Workshop Debuts In Taiwan For The First Time

Feb 11, 2019

Open Electronics Article: iCEBreaker FPGA Development Board Specifically Designed For You

Feb 11, 2019

Auto Connected Car News Article: Automotive Cybersecurity: Practices, RISC-V, Sensors, Argus Cybersecurity, NVIDIA

Feb 11, 2019

Hackaday Article: Building A RISC-V Desktop

Feb 11, 2019

Phoronix Article: The State Of Debian And Fedora On The RISC-V Architecture

Feb 11, 2019

OSnews Article: Building A RISC-V PC

Feb 8, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Feb 8, 2019

Job Posting for RISC-V Foundation CEO

Feb 7, 2019

Embedded World 2019: IAR Systems To Showcase Offering For IoT Security, Automotive Functional Safety And RISC-V

Feb 6, 2019

Electronics-Lab Article: Catena 4710 – Lorawan Based Feather-Compatible FPGA Board With RISC-V Core

Feb 6, 2019

Bit-tech Article: Nvidia, AdaCore Partnership Telegraphs RISC-V Shift

Feb 6, 2019

SmartDV Supports RISC-V Movement With TileLink Verification IP For RISC-V Based Systems

Feb 6, 2019

RISC-V Foundation Showcases Continued Momentum And Growth At Embedded World 2019

Feb 5, 2019

AdaCore Enhances Security-Critical Firmware With NVIDIA

Feb 5, 2019

Heise Article: RISC-V Board For Students With Bluetooth And ARM Cores

Feb 4, 2019

Data Center Knowledge Article: Top 10 Data Center Stories Of The Month: January 2019

Feb 4, 2019

PacktPub Article: AdaCore Joins The RISC-V Foundation, Adds Support For C And Ada Compilation

Feb 4, 2019

Hackaday Article: OpenISA Launches Free RISC-V Vegaboard

Feb 4, 2019

RISC-V Foundation & Members At Embedded World 2019

Feb 1, 2019

Techworld Article: Hardware Security Trend Of Semiconductor Companies

Feb 1, 2019

Leiphone Article: Turing Award Winner Long Report: What Opened The New Golden Decade Of Computer Architecture?

Feb 1, 2019

EET China Article: What Medicine Is Sold In The Flat-Headed Gourd That Is Backed By Alibaba?

Feb 1, 2019

Semiconductor Engineering Article: Week In Review: Design, Low Power

Jan 31, 2019

EEFocus Article: RISC-V Workshop Registered For Early Bird Discount Before Feb. 8 Debut In Taiwan

Jan 31, 2019

Semiconductor Engineering Article: Using Memory Differently

Jan 31, 2019

Feature-Rich RISC-V IDE Available For Free Download

Jan 31, 2019

Rambus Blog Post: The Next Vulnerability: Looking Back On Meltdown And Spectre One Year Later

Jan 31, 2019

Semiconductor Engineering Article: EDA Grabs Bigger Slice Of Chip Market

Jan 31, 2019

Electronic Design Article: 11 Myths About The RISC-V ISA

Jan 31, 2019

eeNews Europe Article: Feature-Rich RISC-V IDE Available For Free Trial

Jan 31, 2019

RISC-V Community Releases OpenSBI to Foster Continued Ecosystem Growth

Jan 30, 2019

Embedded Software Engineering Article: AdaCore Becomes A Member Of The RISC-V Foundation

Jan 30, 2019

Semiconductor Engineering Article: Building Security Into RISC-V Systems

Jan 29, 2019

Bluespec Returns From Landmark RISC-V Summit; CTO Nikhil Leads Discussion On ISA Formal Spec

Jan 29, 2019

ABOpen Article: Western Digital Releases SweRV RISC-V Core Source Code

Jan 29, 2019

AdaCore Joins The RISC-V Foundation To Provide C And Ada Compilation Support

Jan 28, 2019

Golem Article: Western Digital Lanches Its Own RISC-V Designs

Jan 28, 2019

EEJournal Article: Priming The RISC-V Pump

Jan 28, 2019

PacktPub Article: Western Digital RISC-V SweRV Core Is Now On GitHub

Jan 28, 2019

The RISC-V Foundation Announces A Search For A Chief Executive Officer

Jan 24, 2019

GOWIN Semiconductor Licenses Intrinsic ID’s BroadKey To Deliver Hardware Root Of Trust For IoT Security

Jan 24, 2019

Galois Blog Post: 2018: Year in Review

Jan 24, 2019

eWEEK Article: Six Trends Experts See For Advancement of RISC-V In 2019

Jan 23, 2019

MSN Article: RISC-V Promotion Shows Initial Results, Andes Technology Operates Positively

Jan 22, 2019

Semiconductor Engineering On RISC-V, FOSSi’s Growing Potential

Jan 22, 2019

Sohu Article: Detailed RISC-V-Based AndeStar V5 Architecture Innovation And Application

Jan 18, 2019

China Times Article: Andes Custom Extension Makes The Efficient RISC-V Processor Further Enhanced

Jan 17, 2019

Semiconductor Engineering Article: Mostly Upbeat Outlook For Chips

Jan 17, 2019

yamNews Article: Andes Technology Core V5 Processor Re-Evolution Plus ACE Function Is Easier To Add Custom Instructions

Jan 17, 2019

Elektronik Praxis Article: World's First FOC Motor Controller With RISC-V As A Single-Chip Solution

Jan 15, 2019

Linux Insider Article: Introduction To RISC-V: Nikos Kosyfidis Introduces Us To The World Of New Open Processor Architecture

Jan 15, 2019

RISC-V Summit 2018 Highlight Video Celebrates A Banner Year

Jan 14, 2019

AB Open Article: CRU: Raspberry Pi Goes RISC-V, New FOSS Business Model, KiCon 2019, And More

Jan 14, 2019

Rambus Blog Post: India Tech Pursues RISC-V ISA

Jan 14, 2019

The Next Platform Article: CPU Wars And Exascale Clarity: HPC In 2019

Jan 14, 2019

Geeky Gadgets Article: Fomu FPGA Dev Board Is Small Enough To Fit Inside A USB Port

Jan 14, 2019

RISC-V Summit 2018 Highlights Video

Jan 14, 2019

Sohu Article: On Wednesday, Top RISC-V Technology Big Cow Hu Zhenbo Talks About The Design And Development Of Open Source RISC-V Processor For Internet Of Things

Jan 11, 2019

RISC-V Foundation Announces Call For Speakers For RISC-V Workshop Taiwan Region

Jan 11, 2019

Hex Five Security Blog Post: Hex Five’s Don Barnetson Joins RISC-V Foundation Marketing Committee As Co-Chair

Jan 11, 2019

HiPEAC Video: Opportunities In RISC-V

Jan 11, 2019

EE World Article: Shanghai To Increase Efforts To Support RISC-V Chip Development And Mass Production

Jan 10, 2019

Storage Insider Article: Six Forecasts From Western Digital

Jan 10, 2019

EET India Article: Open-Silicon And SiFive To Chisel RISC-V In India

Jan 9, 2019

DesignNews Article: 2019 Will Be The Year Of Open Source

Jan 8, 2019

RISC-V基金會宣布徵集RISC-V台灣地區研討會演講嘉賓 (Traditional Chinese)

Jan 8, 2019

RISC-V基金会宣布征集RISC-V台湾地区研讨会演讲嘉宾 (Simplified Chinese)

Jan 8, 2019

Raspberry Pi Foundation Announces RISC-V Foundation Membership

Jan 8, 2019

Sohu Article: RISC-V Ecological Status And Development Examples

Jan 7, 2019

Hackster.io Article: Raspberry Pi Becomes A Member Of The RISC-V Foundation

Jan 4, 2019

CCIDnet.com Article: Top Ten News Events Of China's Semiconductor Industry In 2018

Jan 4, 2019

EET Asia Article: Riding The IoT Wave With Wi-Fi HaLow

Jan 4, 2019

Phoronix Article: More Details On The Proposed Simple-V Extension To RISC-V For GPU Workloads

Jan 4, 2019

EET India Article: Krste Asanović : RISC-V Momentum Is Massive In India

Jan 4, 2019

OpenSystems Media Newsletter: IoT Design Weekly – 01.03.2018

Jan 3, 2019

Forbes Article: Digital Storage Projections For 2019, Part 2

Jan 3, 2019

Electronic Specifier Article: Optimizing Performance In High-Performance AI Chip

Jan 2, 2019

Andes Technology Video: The Promises And Pitfalls Of RISC-V, From SoC Design Perspective (D&R IP SoC Day Panel)

Jan 1, 2019

Cloud Atomic Laboratory Blog Post: Why RISC-V?

Dec 28, 2018

MuyComputer Article: AMD Will Join RISC-V To Manufacture Open Source Chips (Updated)

Dec 28, 2018

UltraSoC Blog Post: RISC-V Summit: Automotive Developments, System-Level Design, WD SweRV Core, And More…

Dec 27, 2018

Hackaday Article: 2018: As The Hardware World Turns

Dec 27, 2018

SemiWiki.com Article: You Will Not Get Fired for Choosing RISC-V

Dec 27, 2018

EDN China Article: RISC-V Will Help China Occupy The Center Of The SoC Field

Dec 25, 2018

Hackaday Article: How A Microcontroller Hiding In A USB Port Became An FPGA Hiding In The Same

Dec 23, 2018

Phoronix Article: GDB 8.2.1 Debugger Brings Support For RISC-V ELF

Dec 22, 2018

EET China Article: How Is The Commercial Situation Of Each RISC-V Product?

Dec 21, 2018

RISC-V ISA Motivates Youth

Dec 21, 2018

Forbes Article: Digital Storage Projections For 2019, Part 1

Dec 21, 2018

Building Out The RISC-V Ecosystem

Dec 21, 2018

Semiconductor Engineering Article: Beyond The RISC-V ISA

Dec 21, 2018

CNX Software Article: Bluespec Flute Is A 5-Stage Open Source RISC-V Processor

Dec 20, 2018

Semiconductor Engineering Article: Fundamental Shifts In 2018

Dec 20, 2018

TechNode Article: China Looks To Private Capital, Open Source Technology For Global Tech Game Advantage

Dec 19, 2018

Dover Microsystems’ Revolutionary Silicon IP Cybersecurity Approach Fuels Momentum

Dec 19, 2018

Western Digital SweRVs Towards Open Source With New RISC-V Core, ISS, And Cache Coherency

Dec 19, 2018

Open Electronics Article: RISC-V, The Era Of Open Source CPU Has Begun

Dec 19, 2018

The Economic Times Article: IIT Madras- Thales Tie Up For Fault Tolerant Shakti Processor

Dec 19, 2018

Sohu Article: SiFive Will Trigger An Open Source Chip Design Revolution

Dec 19, 2018

IIT Madras To Partner With Digital Firm Thales To Design Shakti Processors With Highest Global Safety Critical Standard

Dec 18, 2018

RISC-V Summit in Review: Growing Momentum and Adoption Driving the Ecosystem Forward

Dec 14, 2018

Inaugural RISC-V Summit Proceedings

Dec 14, 2018

Xataka Article: RISC-V Wants To Be The Safest (Open Source Or Not) Processor In The World, And The Secret Will Be In Its Hardware Enclave

Dec 14, 2018

Round-Table Discusses RISC-V, FOSSi Impact On Hardware Security

Dec 14, 2018

Bluespec, Inc. Releases A Second Family Of Open-Source RISC-V Processors To Spur Open Innovation

Dec 14, 2018

CRU: Free RISC-V Boards, Security In The FOSSi Era, And More

Dec 13, 2018

RISC-V SoftCPU Contest Highlights

Dec 13, 2018

CCIDnet.com Article: Kriste Asanovic, Chairman Of The RISC-V Foundation: The RISC-V Ecology Continues To Grow And Develop

Dec 13, 2018

CNX Software Article: BOOM Open Source RISC-V Core Runs On Amazon EC2 F1 Instances

Dec 13, 2018

EE Journal Article: Microsemi Joins RISC-V Love Fest With SoC FPGA

Dec 13, 2018

Hackaday Article: RISC-V Will Stop Hackers Dead From Getting Into Your Computer

Dec 12, 2018

Semiconductor Engineering Article: Security And Open-Source RISC-V Hardware

Dec 12, 2018

EE Journal Article: RISC-V: The Groundswell Continues

Dec 12, 2018

SiFive Recognized As Most Respected Private Semiconductor Company

Dec 12, 2018

Embedded Computing Design Podcast: Embedded Insiders Tackle RISC-V Summit; Get Our Take On WD, NXP Announcements

Dec 11, 2018

Next Gen News Article: A Feather-Compatible FPGA Board Running A RISC-V Core With LoRaWAN

Dec 11, 2018

UltraSoC Blog Post: RISC-V To Help China Take Its Place At The center Of The SoC Universe

Dec 11, 2018

The Linley Group Article: Esperanto Maxes Out RISC-V

Dec 11, 2018

eeNews Analog Article: Mythic AI Adopts RISC-V Core From Codasip

Dec 11, 2018

Forbes Article: Western Digital Takes A RISC

Dec 11, 2018

Events For Gamers Article: RISC-V Summit 2018 Keynote: Facebook, Silicon And Augmented Reality

Dec 10, 2018

Mythic Chooses Codasip To Deliver RISC-V Computing In Their Revolutionary Neural Network Platform

Dec 10, 2018

Hackster.io Video: RISC-V Summit 2018 Recap

Dec 10, 2018

Hackaday Article: VexRISC-V Exposed

Dec 10, 2018

Cadence Blog Post: RISC-V: Real Products In Volume

Dec 10, 2018

Tom Verbeure On The VexRiscV CPU: “A New Way To Design”

Dec 7, 2018

Linux Press Article: RISC-V Summit Debuts To Showcase Open Source ISA

Dec 7, 2018

ExtremeTech Article: Western Digital Announces Plans For Its Own RISC-V Processor

Dec 7, 2018

eeNews Embedded Article: New Core And Tools Make Implementing RISC-V Quicker

Dec 7, 2018

Embedded Computing Design Article: Western Digital Announces New “Open” Solutions, Including A RISC-V Core

Dec 7, 2018

Semiconductor Engineering Article: Week In Review: Design, Low Power

Dec 7, 2018

Electronics Weekly Article: A View From The RISC-V Summit

Dec 7, 2018

Electronic Design Article: Hard-Core RISC-V Cores Mate With FPGA

Dec 6, 2018

Codasip Releases Studio 8, A Breakthrough In RISC-V Automation, And The Bk7 RISC-V Processor Core For Real-Time Computing Applications

Dec 6, 2018

EE World Article: CPU Cores With RISC-V Technology Now Support The Custom Extension

Dec 6, 2018

EE World Article: Design Verification Platform For RISC-V-Based AI And ML Semiconductor Solutions

Dec 6, 2018

*Andes Custom Extension™ Further Accelerates Your High Performance RISC-V Processors

Dec 6, 2018

Renode 1.6 Released Making Linux-Enabled RISC-V Microchip PolarFire SoC Available To Everyone

Dec 6, 2018

RISC-V SoftCPU Contest Winners Demonstrate Cutting-Edge RISC-V Implementations For FPGAs

Dec 5, 2018

ABOpen Article: Western Digital Unveils Open SweRV RISC-V Core

Dec 5, 2018

Linus Tech Tips Video: Design Your Own CPU!!!

Dec 5, 2018

AnandTech Article: Western Digital Reveals SweRV RISC-V Core, Cache Coherency Over Ethernet Initiative

Dec 5, 2018

Tom's Hardware Article: Western Digital Bets Big On RISC-V With Own Processor, Other Innovations

Dec 5, 2018

UltraSoC Blog Post: Systemic Complexity: Time For RISC-V To Rise To The Challenge

Dec 5, 2018

Valtrix STING DV Platform Selected By AI Chipmaker Esperanto Technologies

Dec 5, 2018

eeNews Embedded Article: Take PolarFire FPGA And RISC-V, Just Add Linux And Your New Development Platform Is Ready

Dec 5, 2018

Embedded Computing Design Video: RISC-V Has Officially Arrived

Dec 5, 2018

ServeTheHome Article: Western Digital NAS Powered By SiFive Microsemi And RISC-V

Dec 5, 2018

Embedded Computing Design Article: Microchip’s New PolarFire SoC Architecture Provides Real-Time To Linux

Dec 5, 2018

TechRepublic Article: Western Digital Will Open Source SweRV RISC-V CPU Designs And Tools

Dec 5, 2018

Embedded Computing Design Article: Five Minutes With…Robert Oshana, VP, NXP

Dec 5, 2018

CNXSoft Article: Microsemi Introduces PolarFire FPGA & RISC-V SoC

Dec 5, 2018

ITPro Today Article: RISC-V Summit Debuts To Showcase Open Source ISA

Dec 5, 2018

OpenISA Launches New, Free RISC-V VEGAboard

Dec 5, 2018

Bit-Tech Article: Western Digital Unveils Open-Source SweRV RISC-V Core

Dec 5, 2018

Finsmes Article: Codasip Secures $10M In Series A Financing

Dec 5, 2018

Phoronix Article: Western Digital To Open-Source The "SweRV" RISC-V Core In 2019

Dec 4, 2018

Embedded Computing Design Video: World's First RISC V Based FPGA SoC Brings An Open Source Ecosystem With It

Dec 4, 2018

Imperas Expands Commercial Operations With Quantum Leap Sales For US Market Growth

Dec 4, 2018

EETimes Article: RISC-V Takes A Leap Forward

Dec 4, 2018

The Register Article: Early To Embed And Early To Rise? Western Digital Drops Veil On SweRVy RISC-V Based Designs

Dec 4, 2018

Daniel Lustig, Chairman Of The RISC-V Memory Model Task Group, Receives Inaugural 2018 RISC-V Foundation Board Of Directors’ Award At The RISC-V Summit

Dec 4, 2018

Western Digital Delivers New Innovations To Drive Open Standard Interfaces And RISC-V Processor Development

Dec 4, 2018

Electronics Weekly Article: IAR Systems And SiFive Collaborate On RISC-V

Dec 4, 2018

SiFive Announces Multiple Technical Advances At RISC-V Summit

Dec 4, 2018

Electronics Weekly Article: Microsemi Adds To RISC-V Based FPGAs

Dec 4, 2018

Industry's First RISC-V SoC FPGA Architecture Brings Real-Time To Linux, Giving Developers The Freedom To Innovate In Low-Power, Secure And Reliable Designs

Dec 4, 2018

Codasip Secures $10M In Series A Financing To Expand RISC-V Processor Technology Offerings

Dec 3, 2018

Andes Technology Corp. To Present and Serve On Security Panel At 2018 RISC-V Summit In Santa Clara

Dec 3, 2018

See Lattice At RISC-V Summit 2018

Dec 3, 2018

QuickLogic CTO, Tim Saxe, To Present At The RISC-V Summit

Dec 3, 2018

Media Alert: Rambus To Demo CryptoManager Root Of Trust At The RISC-V Summit In Santa Clara

Dec 3, 2018

Imperas And Valtrix Announce Partnership For RISC-V Processor Verification

Dec 3, 2018

Embedded Computing Design Article: Imperas, Valtrix Partner For RISC-V Processor Verification

Dec 1, 2018

Embedded Computing Design Article: Andes RISC-V Cores Add Hex Five TEE To GOWIN FPGAs

Nov 30, 2018

New Electronics Article: UltraSoC Launches “Any Processor” Lockstep Solution For Safety-Critical Systems

Nov 30, 2018

Semiconductor Engineering Article: Week In Review: Design, Low Power

Nov 30, 2018

Embedded Computing Design Article: Imperas RiscvOVPsim Brings Free, Open-Source Modeling And Simulation To RISC-V Ecosystem

Nov 29, 2018

Protected: RISC-V Summit Press Kit

Nov 29, 2018

UltraSoC Launches “Any Processor” Lockstep Solution For Safety-Critical Systems

Nov 29, 2018

IAR Systems And Andes Collaborate To Boost Performance For RISC-V Users

Nov 29, 2018

Electronics Weekly Article: UltraSoc Lockstep Monitor Checks Cores

Nov 29, 2018

DataCenter Knowledge Article: Open Source RISC-V Silicon Project And Linux Foundation Form Partnership

Nov 29, 2018

Phoronix Article: The EOMA68 Libre Computer Developer Wants To Tackle A Quad-Core RISC-V Libre SoC Design

Nov 29, 2018

Electronics Weekly Article: Andes And IAR Systems Link On RISC-V

Nov 28, 2018

LinuxGizmos.com Article: RISC-V And Linux Foundation Partner Up

Nov 28, 2018

TechRepublic Article: RISC-V And Linux Foundations Will Partner To Promote Open Source CPU

Nov 28, 2018

Electronics Weekly Article: Linux And RISC-V Foundations Cosy Up

Nov 28, 2018

SiFive To Present Latest Technology Developments At RISC-V Summit

Nov 27, 2018

Western Digital Blog Post: Five Reasons The RISC-V Summit Is A Can’t-Miss Event

Nov 27, 2018

Apacer Launches 32-Bit SODIMM For Arm & RISC-V Systems

Nov 27, 2018

SureCore Joins The RISC-V Foundation

Nov 27, 2018

GreenWaves Technologies Named Finalist For The 2018 Electronic Products’ “Product Of The Year Awards”

Nov 27, 2018

Western Digital CTO Martin Fink To Address New Era Of Open Processor Innovation With Keynote Address At RISC-V Summit

Nov 27, 2018

Embedded Computing Design Article: Linux, RISC-V Foundations To Collaborate On Open Architectures

Nov 27, 2018

The Register Article: Linux Lobby Org Joins With RISC-V Bods To Promote Open Chip Spec

Nov 27, 2018

The Linux Foundation And RISC-V Foundation Announce Joint Collaboration To Enable A New Era Of Open Architecture

Nov 26, 2018

Silex Insight Joins RISC-V Foundation

Nov 26, 2018

ABOpen Article: Thales Joins RISC-V Foundation, Praises ISA’s Protection From “Cyber Threats”

Nov 26, 2018

IoT World Today Article: RISC-V And The Rise Of Open Source Hardware Community

Nov 26, 2018

Hackaday Article: RISC-V CPU Gets A Peripheral

Nov 26, 2018

Thales Joins RISC-V Foundation To Help Secure Open-Source Microprocessors

Nov 20, 2018

TechNode Article: Smartwatches Will Replace Smartphones, Says Huami CEO

Nov 19, 2018

Financial Express Article: Food Cafe: ‘Batteries Are The New Oil’, IIT Madras Director Bhaskar Ramamurthy Explains How India Needs To Catch Missed Buses In Technology

Nov 19, 2018

Sipeed Launches Crowdfunder For RISC-V MAIX AI Dev Boards

Nov 19, 2018

Sohu Article: OURS Technology Released 64-bit AI SoC Based on RISC-V

Nov 19, 2018

SiFive Appoints VP To Growing SoC IP Group

Nov 16, 2018

See Esperanto Technologies At The Inaugural RISC-V Summit, December 2018

Nov 16, 2018

SemiWiki.com Article: SiFive Extends Portfolio With 7 Series RISC-V Cores

Nov 16, 2018

Electronics Weekly Article: RISC-V Open Virtual Platform Simulator

Nov 16, 2018

ITNews Article: Western Digital Takes The Risk And Leads An Open Computing Revolution With RISC-V

Nov 15, 2018

EE Times Article: RISC-V Momentum Seen Growing In China

Nov 14, 2018

Elektronikknett Article: Can RISC-V Be The Solution?

Nov 14, 2018

eeNews Europe Article: Esperanto Raises Funds For AI Superchip

Nov 14, 2018

LinuxGizmos.com Article: This Under-$6 SBC Runs Linux On C-SKY ISA Chip

Nov 13, 2018

Moortec’s 7nm In-Chip Monitoring Subsystem IP Chosen By Esperanto Technologies To Optimize Performance And Reliability In Its High-Performance AI Chip

Nov 13, 2018

LinuxGizmos.com Article: Linux-Driven 96Boards SBC Features AI And RISC-V Companion Chips

Nov 13, 2018

lowRISC Blog Post: Tutorial For The v0.5 lowRISC Preview Release

Nov 13, 2018

Watch Out For “Made In China” Open Source Artificial Intelligence Chipsets

Nov 13, 2018

Andes Technology And INVECAS Announce Partnership To Win RISC-V-Based SoC Designs For Advanced Processes

Nov 13, 2018

SiFive, Credo And Open-Silicon Showcase End-To-End Solutions For HPC And Networking Applications At SC18 In Dallas

Nov 13, 2018

ElectronicDesign Article: Startup Esperanto Technologies Raises $58 Million

Nov 9, 2018

Electronics Weekly Article: RISC-V Foundation Sets Up In China

Nov 9, 2018

Hex Five Adds MultiZone Security To The Andes RISC-V Cores On GOWIN FPGAs

Nov 9, 2018

Last Week in RISC-V: Friday November 9, 2018

Nov 9, 2018

Semiconductor Engineering Article: Week In Review: Design, Low Power

Nov 9, 2018

TechNode Article: Briefing: China Sets Up Domestic Chip Alliance

Nov 8, 2018

LinuxGizmos.com Article: RISC-V Linux Development In Full Swing

Nov 7, 2018

方之熙博士被任命為 RISC-V 基金會中國顧問委員會主席，加快推行 RISC-V ISA 在中國的應用 (Traditional Chinese)

Nov 7, 2018

方之熙博士被任命为RISC-V基金会中国顾问委员会主席，加速RISC-V ISA在中国的应用 (Simplified Chinese)

Nov 7, 2018

Dr. Jesse Zhixi Fang Appointed as Chair of the RISC-V Foundation China Advisory Committee to Accelerate Adoption of the RISC-V ISA in China

Nov 7, 2018

TechSpark Article: UltraSoC Hosts Bristol RISC-V Meetup As It Looks To Expand

Nov 6, 2018

Elektronik Article: RISC-V Instruction Set Architecture

Nov 6, 2018

VentureBeat Article: Esperanto Technologies Raises $58 Million For 7-Nanometer AI Chips

Nov 6, 2018

Imperas Empowers RISC-V Community With riscvOVPsim

Nov 5, 2018

Bit-tech Article: Esperanto Pulls $58m For RISC-V Many-Core Accelerators

Nov 5, 2018

Esperanto Technologies Secures $58 Million In Series B Investment For AI Chips

Nov 5, 2018

Last Week In RISC-V: Friday October 26, 2018

Nov 2, 2018

AutomatedBuildings.com Article: What Is Edge Computing?

Nov 2, 2018

Semiconductor Engineering Article: The Week In Review: Design

Nov 1, 2018

Gadgets Now Article: IIT-Madras Develops India's First Microprocessor Shakti

Nov 1, 2018

Hex Five Security Announces Creation Of Strategic Advisory Board

Nov 1, 2018

MyNavi Article: RISC-V In Tokyo 2018 – Esperanto Aiming At Servers With RISC-V

Nov 1, 2018

Electronics Weekly Article: SiFive Launches More Powerful RISC-V Core

Oct 31, 2018

LinuxGizmos.com Article: SiFive Unveils Octa-Core RISC-V Designs, Including Two Linux-Ready Models

Oct 31, 2018

VentureBeat Article: SiFive Launches RISC-V Processor Cores For Real-Time Applications

Oct 31, 2018

UltraSoC Blog Post: RISC-V Day Tokyo

Oct 31, 2018

Andes RISC-V CON Debuts At Hyatt Regency Santa Clara November 13; Linley Group, MediaTek, Andes, Faraday, GOWIN, Imperas Software, Hex Five, And XtremeEDA To Detail RISC-V Technology Advance

Oct 31, 2018

Netronome Announces Open Chiplet Architecture For Advanced SoC Designs

Oct 29, 2018

Phoronix Article: C-SKY Architecture Approved For The Linux Kernel, Might Be The Last New CPU Arch

Oct 26, 2018

SiliconIndia Article: Researchers Of IIT Madras Design And Fabricate India's First Indigenously Developed 'RISC-V Microprocessor'

Oct 25, 2018

UltraSoC And ResilTech Partner To Further Functional Safety In Automotive Systems

Oct 25, 2018

Embedded Computing Design Video: Hex-Five Multi-Zone Security For RISC V Simplifies The Terrible TEEs

Oct 24, 2018

MyNavi Article: RISC-V In Tokyo 2018 – SiFive's Cloud Design Service

Oct 22, 2018

Electronic Products & Technology: Hardware Root Of Trust Boosts RISC-V AI Application Processor

Oct 22, 2018

Last Week In RISC-V: Friday October 19, 2018

Oct 19, 2018

CNX Software Article: $50 Kendryte KD233 Board Features K210 Dual Core RISC-V SoC

Oct 19, 2018

EnterpriseTech Article: Penguin’s New Practice For Piecing AI Strategies Together

Oct 19, 2018

Nikkei Electronics Article: Optimize Both Open Source Waves, Soft And Hard To Microcontrollers

Oct 18, 2018

ElectronicDesign Article: Startup Adds Artificial Intelligence To Debugging Tool

Oct 16, 2018

UltraSoC Announces Integrated Multi-Core Debug, Visualization And Data Science / Analytics Suite

Oct 16, 2018

Electronics Weekly Article: UltraSoC Launches UltraDevelop 2 IDE

Oct 15, 2018

Hackaday Article: Hackaday Links: October 14, 2018

Oct 15, 2018

Semiconductor Engineering Article: RISC-V: More Than A Core

Oct 12, 2018

EET Taiwan Article: Choose AI Hardware Acceleration Scheme For Different Applications

Oct 12, 2018

Andes Announces Over 1.2 GHz RISC-V Cores Series At 28nm: A25/AX25 And N25F/NX25F

Oct 12, 2018

Power Electronics Article: The Semiconductor Industry Is In Transition

Oct 10, 2018

RISC-V Foundation Launches Soft CPU Design Contest

Oct 10, 2018

ECN Article: Roundtable Part 2: Experts Examine New Innovations And Share Advice For Future Engineers

Oct 9, 2018

ECN Article: Roundtable Part 1: Experts Discuss Current Trends And Future Obstacles

Oct 9, 2018

RBC Article: How Scientists And Startups Compromised Intel's Hegemony

Oct 9, 2018

Hackaday Article: Programming A RISC-V Softcore With Ada

Oct 9, 2018

Hackaday Article: New Part Day: The RISC-V Chip With Built-In Neural Networks

Oct 9, 2018

Codasip Studio And Codasip Codespace 7.2 Available

Oct 9, 2018

CRU: FOSSi Growth Scares Arm, Verilator 4.0 Launched, And More

Oct 9, 2018

Prisma News Article: The 11th FOSSCOMM 2018 Conference In Heraklion

Oct 8, 2018

RISC-V SoftCPU Contest

Oct 8, 2018

RISC-V Design Contest Calls On Embedded Designers To Push The Limits Of Innovation

Oct 5, 2018

EETAsia Article: TSMC To Start 5nm Production In April

Oct 3, 2018

Anue News Article: RISC-V Architecture Products Stabilized Shipments, Jingxinke's Share Price Broke Through The Monthly Line Back Pressure

Oct 3, 2018

RISC-V Ecosystem Highlights Innovative RISC-V Projects at RISC-V Day Tokyo

Oct 2, 2018

PacktPub Article: A Libre GPU Effort Based On RISC-V, Rust, LLVM And Vulkan By The Developer Of An Earth-Friendly Computer

Oct 2, 2018

SiFive Welcomes Former Tesla Executive To Lead Global Growth Strategy

Oct 2, 2018

See Esperanto Technologies At The RISC-V Day Tokyo, October 2018

Oct 1, 2018

EE World Article: SiFive Seminar in Beijing

Oct 1, 2018

MyNavi News Article: "BROOM" High-Performance RISC-V Core

Oct 1, 2018

Semiconductor Engineering Article: RISC-V Inches Toward The Center

Oct 1, 2018

Top 500 Article: Europeans Budget 1.4 Billion Euros To Build Next-Generation Supercomputers

Oct 1, 2018

GOWIN Semiconductor Licenses Andes Technology RISC-V CPU Core For Its Arora® GW-2A FPGA Family Products

Oct 1, 2018

RISC-V Foundation Announces The Agenda For Its Inaugural RISC-V Summit

Sep 28, 2018

Phoronix Article: There's A New Libre GPU Effort Building On RISC-V, Rust, LLVM & Vulkan

Sep 28, 2018

Hackaday Article: Three Part Deep Dive Explains Lattice iCE40 FPGA Details

Sep 27, 2018

GreenWaves Technologies Licenses Intrinsic ID Hardware Root Of Trust For RISC-V AI Application Processor

Sep 26, 2018

Join Andes Technology Corporation At The TSMC Open Innovation Platform® Ecosystem Forum

Sep 26, 2018

Recap Of The Third Bay Area RISC-V Meetup At Rambus

Sep 25, 2018

EET Taiwan Article: 3D NAND Saves Mobile Phone Space Shortage Anxiety?

Sep 23, 2018

Esperanto Technologies Blog Post: See Esperanto At The RISC-V Summit In Silicon Valley December 2018

Sep 19, 2018

Agenda For RISC-V Day Tokyo on Oct. 18

Sep 19, 2018

Agenda For Inaugural RISC-V Summit in Santa Clara, Calif. from Dec. 3-6

Sep 19, 2018

BioSpectrum Article: Huami Launches Health Band 1S And Smart Wearable AI Chip

Sep 19, 2018

ComputerWorld Article: Data61 Partners With German Vendor To Protect Global Defense Systems

Sep 19, 2018

My Smart Price Article: Huami All Set To Launch An AI Powered SmartWatch – Huangshan No.1

Sep 19, 2018

Gizmochina Article: Huami Announces Huangshan No. 1, The World’s First AI-Powered Wearable Chipset

Sep 19, 2018

Wearable Article: Huami's 'First AI-Powered Wearable Chipset' Takes Aim At Apple Watch

Sep 19, 2018

Engadget Article: Huami’s New Watch And Bracelet Are Coming

Sep 18, 2018

PULP Platform Announces HERO: Open Heterogeneous Research Platform

Sep 18, 2018

All Hype Or Real Hope For The Processor Market?

Sep 14, 2018

The Telegraph Article: Platform For Chip Designing

Sep 13, 2018

Wasiela Brings Encryption, FEC And Connectivity IP To DesignShare

Sep 11, 2018

The Register Article: Arms Race: SiFive, Hex Five Build Code Safe Houses For RISC-V Chips

Sep 10, 2018

Rambus Blog Post: No Need To Reinvent The Wheel: How Easy It Is To Build With RISC-V

Sep 10, 2018

Embecosm Blog Post: Supporting The RISC-V Vector Extension In GCC And LLVM

Sep 10, 2018

Hex Five Security Adds MultiZone™ Trusted Execution Environment To The SiFive Software Ecosystem

Sep 10, 2018

Codasip Expands Its Global Reach By Signing Channel Partnerships Throughout Asia

Sep 10, 2018

RISC-V Foundation Announces Initial Keynote Speakers For Inaugural RISC-V Summit

Sep 4, 2018

SiFive And Open-Silicon Host The Final RISC-V Tech Symposium 2018 In New Delhi

Sep 4, 2018

The Register Article: Boffins Are Building An Open-Source Secure Enclave On RISC-V

Aug 30, 2018

ElectronicDesign Article: Security First: Implementing Trust By Design

Aug 30, 2018

Phys.org Article: Novel Architecture Boosts Energy And Spectrum Efficiency For Internet Of Things Wireless Communication

Aug 27, 2018

Rambus Blog Post: Lowering Risks With RISC-V

Aug 27, 2018

NewsBarons Article: SiFive And Open-Silicon Partner To Host RISC-V Tech Symposiums In India

Aug 27, 2018

GOWIN Semiconductor Corp. Announces RISC-V Microprocessor Implementation for GOWIN FPGA Solutions And Expands Sales Channels In The Americas Region

Aug 26, 2018

RISC-V Instruction Sets | Devopedia

Aug 24, 2018

Fish Fry Podcast: Big World, Big Data

Aug 24, 2018

Focus Article: RISC-V Is Slowly "Changing The World"

Aug 23, 2018

SiFive Announces Open Source-Focused SoC Development Platform Based On RISC-V And NVDLA

Aug 23, 2018

As AI and IoT Space See A Major Boom, Open Source RISC-V Chips Can Address The Computing Needs

Aug 22, 2018

Linus Tech Tips Video: An Open Source CPU!?

Aug 22, 2018

TECHIExpert Article: RISC-V Symposium Tech In Hyderabad

Aug 22, 2018

EET Asia Article: Microsoft And Google Planning Silicon-Level Security

Aug 21, 2018

Update on the Development of the RISC-V Software Toolchain

Aug 21, 2018

Sensors Online Article: Open-Source RISC-V-Based SoC Platform Enlists Deep Learning Accelerator

Aug 21, 2018

The Hindu Article: ‘RISC-V Seeing Open ISA Momentum’

Aug 20, 2018

JoinUp Article: Building Microprocessor Architectures On Open-Source Hardware And Software

Aug 20, 2018

Zephyr Project RTOS Gets RISC-V Partners, Board Support

Aug 20, 2018

Telangana Today Article: RISC-V To Help India’s Electronics Sector

Aug 20, 2018

EE Times Article: AI Startup Hires Two Tesla EEs

Aug 20, 2018

TechRadar Article: One Of The World's Largest Storage Companies Is Investing Into Processing, Here's Why

Aug 20, 2018

Linux.com Article: Zephyr Project Embraces RISC-V With New Members And Expanded Board Support

Aug 20, 2018

Esperanto Technologies Expands AI Engineering Leadership Team

Aug 20, 2018

Gowin Announces RISC-V Implementation Of Arora FPGA And An Alcom Electronics Distribution Tie-up In Europe

Aug 20, 2018

SiFive Announces First Open-Source RISC-V-Based SoC Platform With Nvidia Deep Learning Accelerator Technology

Aug 17, 2018

Electronic Specifier Article: Software Heads Into The Clouds And SoCs Take Center Stage

Aug 16, 2018

LinuxGizmos.com Article: Embedded Linux Conference Europe Tackles Tech’s Diversity Problem

Aug 15, 2018

Charbax Interview With RISC-V Executive Director, Rick O'Connor At Embedded

Aug 15, 2018

Bluespec, Inc. Releases A New Family Of Open-Source RISC-V Processors

Aug 14, 2018

Session Lineup At Open Source Summit Europe And Embedded Linux Conference + OpenIoT Summit Europe Offers Complete Overview Of The Open Source Ecosystem

Aug 14, 2018

UltraSoC Selects MosChip To Support Its Growth In India

Aug 14, 2018

Antmicro And SiFive Join Forces To Propose Complete RISC-V Offering

Aug 9, 2018

Utilizing Open Source Hardware in Academic Environments

Aug 8, 2018

Andes Technology Forms A Multinational Alliance With ASIC Design Service Companies To Provide RISC-V Total Solutions

Aug 8, 2018

QuickLogic Collaborates With ETH Zurich To Integrate eFPGA Into PULP Platform

Aug 8, 2018

Bit-tech Article: SiFive's RISC-V Cores Launch In Two SSD Families

Aug 7, 2018

FADU Launches Industry Leading SSD Solutions Powered By SiFive RISC-V Core IP

Aug 7, 2018

eSilicon Licenses Industry-Leading SiFive E2 Core IP For Next-Generation SerDes IP

Aug 7, 2018

Mobiveil Inc. And SiFive Partner To Develop RISC-V Based Configurable SSD Platform For Data Center And Enterprise Storage Applications

Aug 7, 2018

TechNode Article: Lack Of Support For Young Researchers Is Holding Back China's Innovation

Aug 7, 2018

EE Times Article: India Startup Preps RISC-V, AI Cores

Aug 6, 2018

RISC-V Foundation Announces Call For Papers And Registration Promotions For Inaugural RISC-V Summit

Aug 1, 2018

UltraSoC Brings SEGGER J-Link To Embedded Debug And Analytics Environment

Aug 1, 2018

LinuxGizmos.com Article: Linux Boots On New “Shakti” RISC-V Chip

Aug 1, 2018

HardOCP Article: India Develops Processor Based On Open Source RISC-V Design

Aug 1, 2018

EE Times Article: Ex-Q'commers Prep RISC-V Blockchain Chip

Jul 31, 2018

UltraSoC Blog: The Future of RISC-V In China Is Bright

Jul 30, 2018

Fossbytes Article: Linux Boots On “Shakti” — India’s First Ever RISC-V Based Silicon Processor

Jul 30, 2018

Electronics Weekly Article: RS Details RISC-V Processing Hardware In The Shape Of Arduino

Jul 25, 2018

eeNews Europe Article: UltraSoC's Alibaba Design Win Underlines China's Significance

Jul 25, 2018

Electronics Weekly Article: C-SKY Micro KLicenses UltraSoC

Jul 25, 2018

China Integrated Circuit Magazine: RISC-V Leads the Revolution of Chip Customization

Jul 24, 2018

NXP and Dover Microsystems Join Forces to Deliver Unprecedented Network Security, Safety, and Privacy for Processors

Jul 24, 2018

Semiconductor Engineering Article: Safety, Security and PPA Tradeoffs

Jul 24, 2018

Open-Silicon and Credo Demonstrate Solutions for Deep Learning and Networking Applications at TSMC OIP and Symposium in Amsterdam

Jul 24, 2018

Embedded Computing Design: RISC-V Foundation Forms Security Committee

Jul 24, 2018

Dolphin Integration: New Release of Our Innovative IDE for the RISC-V Ecosystem

Jul 23, 2018

SemiInsight Article: Is RISC-V Ready to Change the World?

Jul 23, 2018

UltraSoC Blog: India And RISC-V: Tasty Ecosystems, Fast Data, And Bright Futures

Jul 20, 2018

VLSI System Design: RISC-V Workshop @IIT Madras – Day 2

Jul 19, 2018

RISC-V Workshop in Chennai Proceedings

Jul 19, 2018

VLSI System Design Article: RISC-V Workshop @IIT Madras – Day 1

Jul 19, 2018

EE Journal Article: RISC-V Aims for World Domination

Jul 18, 2018

News by Careers360: RISC-V ISA Begins At IIT Madras

Jul 17, 2018

IEEE Spectrum Article: DARPA Plans A Major Remake Of U.S. Electronics

Jul 17, 2018

EE Times Article: Is This The Moment For RISC-V?

Jul 17, 2018

The Register Article: EU Plans For Domestic Exascale Supercomputer Chips: A RISC-y Business

Jul 17, 2018

EEFocus Article on the Progress of RISC-V in China

Jul 17, 2018

AB Open Article: CRU: RISC-V Security, LoRaWAN Tutorial, Fog Computing, And More

Jul 17, 2018

Linux Magazine Article: Open Hardware – RISC-V

Jul 11, 2018

EE Times Article: Healthy Discussion of Architectural Choices

Jul 11, 2018

EDN Article: AI Hardware Acceleration Needs Careful Requirements Planning

Jul 11, 2018

UltraSoC Blog: RISC-V Is About To Open The Door To A Wave Of New Chip Startups In India

Jul 10, 2018

SiFive: Terminus Circuits Brings Complete ASIC Solutions To DesignShare

Jul 10, 2018

RISC-V Foundation Announces Agenda For RISC-V Workshop In Chennai

Jul 9, 2018

EDA Café Interview of Rick O'Connor at DAC 2018

Jul 9, 2018

Top 500 Article: European Program To Develop Supercomputing Chips Begins To Take Shape

Jul 9, 2018

Phoronix Article: Ada Language Support For RISC-V With Latest GCC Patches

Jul 9, 2018

Antmicro: Renode 1.4 Released: 64-bit RISC-V HiFive Unleashed Support, Multiple Silicon Labs Targets, And More

Jul 5, 2018

RISC-V Foundation at Design Automation Conference (DAC) Proceedings

Jul 5, 2018

RISC-V Day in Shanghai Proceedings

Jul 3, 2018

RISC-V ISA Wins Prestigious Electrons d'Or Award, Validating Industry’s Commitment to the RISC-V Ecosystem

Jul 3, 2018

Sensors Online Article: Partners Support Agile RISC-V SoC Design Platform With NoCs

Jul 2, 2018

RISC-V Foundation Announces Security Standing Committee, Calls Industry To Join In Efforts

Jun 29, 2018

EE Journal Fish Fry Podcast By Amelia Dalton: To The Cloud And Beyond

Jun 29, 2018

SiliconANGLE Article: China, Blockchain And Chips: Western Digital Looks Beyond Storage

Jun 28, 2018

Semiconductor Engineering Article: Wednesday At DAC 2018

Jun 28, 2018

Inside Secure And Andes Join Forces To Deliver Secure IoT Solutions To Chipmakers For Greater China And Asia Markets

Jun 28, 2018

RISC-V: Opening A New Era Of Innovation For Embedded Design

Jun 25, 2018

Hackday Article: SiFive Releases Smaller, Lower Power RISC-V Cores

Jun 25, 2018

SiFive Unveils E2 Core IP Series For Smallest, Lowest Power RISC-V Designs

Jun 25, 2018

Embedded Computing Design Article: RISC-V Arrives

Jun 25, 2018

Embedded Computing Design Article: Open-Source RISC-V Architecture Is Changing The Game For IoT Processors

Jun 25, 2018

Embedded Computing Design Article: Open Compute With RISC-V And Memory Fabrics

Jun 22, 2018

Andes Technology Corp. To Present At The TSMC OIP Theater During Design Automation Conference 2018 To Feature New RISC-V CPU Cores In Booth 2658

Jun 22, 2018

Electronics Weekly Article: UltraSoc Links With Imperas

Jun 21, 2018

ElectronicDesign Article: Not Your Father’s FPGAs Anymore

Jun 21, 2018

UltraSoC Embedded Analytics And Imperas Virtual Platforms Combine To Enhance Multicore Development And Debug

Jun 21, 2018

Andes Certifies Imperas Models And Simulator As A Reference For Andes RISC-V Cores

Jun 20, 2018

RISC-V Workshop in Chennai

Jun 20, 2018

RISC-V Ecosystem Highlights Momentum Across Asia At RISC-V Day In Shanghai

Jun 19, 2018

Dolphin Integration Makes Available In Free Download Its Innovative IDE SmartVision, For The RISC-V Ecosystem

Jun 13, 2018

RISC-V Day in Shanghai

Jun 13, 2018

RISC-V Summit – Call for Papers

Jun 12, 2018

Growing RISC-V Ecosystem To Share New Developments And Momentum At DAC 2018

Jun 7, 2018

ACM Video: John Hennessy And David Patterson 2017 ACM A.M. Turing Award Lecture

Jun 7, 2018

RISC-V E-Newsletter Summer 2018

Jun 5, 2018

SemiWiki Article: The Dawn Of A New RISC

May 31, 2018

Embedded Computing Design Article: A Look Back At The RISC-V Workshop In Barcelona And The RISC-V Ecosystem’s Growth

May 31, 2018

Design & Reuse Article: Dolphin Integration Announces The Availability Of Its RISC-V Subsystem: RV32 Tornado

May 29, 2018

RISC-V At Design Automation Conference (DAC)

May 29, 2018

Fast Company Article: This Tiny Drone With A Tiny Brain Is Smart Enough To Fly Itself

May 29, 2018

Embedded Computing Design Article: Put RISC-V In Your Design

May 29, 2018

eeNews Embedded Interview With Dave Ditzel: 'We develop New AI Processors On The Open RISC-V Architecture'

May 29, 2018

Electronics Weekly Article: DAC Explores The Role Of AI And ML Across The Markets

May 25, 2018

RISC-V Day in Shanghai – Call for Papers

May 24, 2018

eeNews Embedded: 'We Develop New AI Processors on the Open RISC-V Architecture' | eeNews Interview with Dave Ditzel

May 23, 2018

RISC-V Workshop in Chennai – Call for Papers

May 23, 2018

Brite Semiconductor Joins SiFive's DesignShare Program

May 23, 2018

Andes Technology Corporation And XtremeEDA Corporation Cooperate To Develop Joint Design Wins On Emerging RISC-V Designs

May 18, 2018

Recode Interview: Full transcript: Dave Patterson And John Hennessy On Recode Decode

May 18, 2018

UltraSoC Blog Post: RISC-V: Are We There Yet…?

May 18, 2018

Electronics Weekly Article: Esperanto Licenses NetSpeed AI IP

May 18, 2018

Data Center Knowledge Article: SiFive Releases 'Expansion Board' To Build Interest In RISC-V Processor

May 18, 2018

Embedded Computing Design Article: Impressions From The Recent RISC-V Workshop In Barcelona

May 17, 2018

eeNews Embedded: A Hotel Room, Engineers, an Mi-V Board? | Ted Marena from Microsemi Can Tell the Whole Story

May 17, 2018

SiFive Inc. And Andes Technology Corporation Join Forces To Promote RISC-V

May 16, 2018

RISC-V Workshop in Barcelona Recap

May 16, 2018

UltraSoC Blog: RISC-V Workshop: Security, Scalability, And Super Mario

May 16, 2018

The Register Article: Boffins Build Smallest Drone To Fly Itself With AI

May 16, 2018

Sensors Online Article: IoT Platform Supports Potent Processors

May 16, 2018

Engineering News Network Article: Enabling Linux Software And Firmware Developers To Build RISC-V PCs For The First Time

May 14, 2018

eeNews Embedded Interview: Hardware Is From Mars, Software Is From Venus – eeNews Interview With Rob Oshana, VP Software Engineering NXP At The RISC-V Workshop In Barcelona

May 14, 2018

Dolphin Integration Joins The RISC-V Foundation

May 11, 2018

DesignNews Article: HiFive-Unleashed Expansion Board Opens Door For RISC-V PCs

May 11, 2018

Semiconductor Engineering Article: The Week In Review: Design

May 11, 2018

eeNews Embedded Interview With Martin Fink, CTO Of Western Digital At The RISC-V Workshop

May 10, 2018

eeNews Embedded Article: RISC-V Has Supercomputer Powers

May 10, 2018

Inside HPC Article: Mateo Valero On How RISC-V Can Play A Major Role In New Supercomputer Architectures

May 10, 2018

Read IT Quick Article: Express Logic Announces X-Ware IoT Platform Support For AndesCore N25 And NX25 RISC-V Processors

May 10, 2018

TechNode Article: Core Technology And Startups: What Can We Expect In The Post-ZTE Era?

May 9, 2018

Express Logic’s X-Ware IoT Platform Brings Industrial-Grade IoT Device Connectivity To The AndesCore™ N25 And NX25 RISC-V Processors

May 9, 2018

TechCrunch Article: Intel Capital Pumps $72M Into AI, IoT, Cloud And Silicon Startups, $115M Invested So Far In 2018

May 9, 2018

eeNews Embedded Interview: Happening Now! RISC-V Is In The Rise – eeNews Report From The RISC-V Workshop In Barcelona

May 9, 2018

LowRISC Blog Post: Barcelona RISC-V Workshop: Day Two

May 9, 2018

Antmicro Blog: Renode Website Launch And 64-bit Linux-enabled RISC-V Support Announced In Barcelona

May 8, 2018

RISC-V Workshop in Barcelona Proceedings

May 8, 2018

SiFive Announces Investment From Intel Capital

May 8, 2018

Antmicro Reveals Partnership With Thales On The Disruptive RISC-V Open ISA

May 8, 2018

SiFive Challenge Calls For RISC-V Hardware Innovations

May 8, 2018

Western Digital Blog: Top Five From RISC-V

May 8, 2018

LowRISC Blog Post: Barcelona RISC-V Workshop: Day One

May 7, 2018

Embedded Computing Design Article: Develop Your Linux Apps On This RISC-V Board

May 7, 2018

Sensors Online Article: Expansion Board Enhances Popular RISC-V Development Board

May 7, 2018

Electronics Weekly Article: Esperanto To Use UltraSoC Analytics

May 7, 2018

Microsemi And SiFive Launch HiFive Unleashed Expansion Board, Enabling Linux Software And Firmware Developers To Build RISC-V PCs For The First Time

May 7, 2018

NetSpeed And Esperanto Partner To Power SoCs For Artificial Intelligence

May 7, 2018

UltraSoC Analytics IP Selected By Esperanto Technologies For RISC-V Many-core Parallel Processing In AI And ML Applications

May 7, 2018

Embecosm Blog: Surveying The Free And Open Source RISC-V Ecosystem

May 7, 2018

Andes Technology Corp. To Make Two Presentations At The 2018 RISC-V Workshop In Barcelona

May 4, 2018

eeNews Europe Article: RISC-V Expansion Board For Linux Software And Firmware Developers

May 3, 2018

Esperanto Technologies Engineers To Present At RISC-V Workshop Barcelona

May 2, 2018

EE Journal Article: Imperas And Andes Extend Partnership, Delivering Models And Virtual Platforms For Andes RISC-V Cores With New AndeStar V5m Extensions

May 1, 2018

Imperas And Andes Extend Partnership, Delivering Models And Virtual Platforms For Andes RISC-V Cores With New AndeStar V5m Extensions

May 1, 2018

Electronic Design Article: Low-Power Play: GAP8 Weds Multicore RISC-V With Machine Learning

Apr 30, 2018

UltraSoC Selected By Andes For RISC-V Development With Trace And Debug

Apr 23, 2018

eeNews Europe Article: Codasip Wins RISC-V Business In Motor Control ICs

Apr 23, 2018

The Register Article: Brains Behind seL4 Secure Microkernel Begin RISC-V Chip Port

Apr 23, 2018

RISC-V Founding Member Antmicro Turns Platinum To Bring A Software-Driven Perspective

Apr 23, 2018

Dongwoon Anatech Licenses Codasip's Bk3 RISC-V Processor For Motor Control ICs For Mobile Camera

Apr 23, 2018

RISC-V Foundation And Informa Announce First Annual RISC-V Summit In Silicon Valley And 2018 Workshop Schedule

Apr 19, 2018

RISC-V Workshop in Barcelona

Apr 19, 2018

Computer Business Review Article: Rambus Releases Programmable Chip In Wake Of Spectre, Eyes Automotive Market

Apr 18, 2018

Australian Innovation To Enhance Security Of Billions Of Connected Devices

Apr 18, 2018

ComputerWorld Article: Data61 Ports SeL4 Microkernel To RISC-V Architecture

Apr 17, 2018

HPC Wire Article: Hennessy & Patterson: A New Golden Age For Computer Architecture

Apr 17, 2018

EE Times Article: Rambus Taps RISC-V For Root Of Trust

Apr 17, 2018

Electronics Weekly Article: Rambus Launches CryptoManager RISC-V Core

Apr 17, 2018

Bit-Tech Article: Rambus Picks RISC-V For New Crypto Chip

Apr 17, 2018

Microsemi's Mi-V Ecosystem Continues To Expand As New Member Antmicro Joins To Develop Mi-V RISC-V Processor Subsystems For PolarFire FPGAs

Apr 16, 2018

RISC-V Foundation Announces Agenda For Workshop In Barcelona

Apr 16, 2018

Rambus Launches CryptoManager RISC-V Root Of Trust Programmable Secure Processing Core

Apr 12, 2018

Dover Microsystems Brings Secure Silicon IP to SiFive's DesignShare

Apr 12, 2018

WIRED Article: Using Open Source Designs To Create more Specialized

Apr 4, 2018

SatMagazine Article: Improving Space Systems Designs Using FPGAs With RISC-V Cores—A Microsemi Tech Focus

Apr 3, 2018

EE World Article: Why RISC-V Is Becoming More And More Popular

Apr 2, 2018

TechCrunch Article: SiFive Gets $50.6M To Help Companies Get Their Custom Chip Designs Out The Door

Mar 30, 2018

Amelia Dalton's Fish Fry Podcast (EE Journal): RISC-V And The New Frontier Of Microprocessors

Mar 29, 2018

EE Journal Article: Fifty (Or Sixty) Years Of Processor Development…For This?

Mar 28, 2018

Dover Microsystems Blog Post: How RISC-V Is Changing The Game

Mar 23, 2018

KCBS Interview: David Patterson Interview

Mar 22, 2018

Register for the Upcoming RISC-V Workshop in Barcelona: May 7-10, 2018

Mar 21, 2018

Future Electronics Video: Microsemi: Future RISC V Creative Board Unboxing

Mar 21, 2018

WIRED Article: 'Computing's Nobel Prize" Winners Paved The Way To Smartphone Chips

Mar 21, 2018

CNET Article: RISC Reward: Turing Award Goes To Computer Chip Inventors

Mar 21, 2018

New York Times Article: Computer Chip Visionaries Win Turing Award

Mar 21, 2018

The Register Article: Google Gives Its $1m Turing Prize To, Er, Top Google Bods: RISC Men Hennessy, Patterson

Mar 21, 2018

David Patterson, Vice Chair of the Board at the RISC-V Foundation, Receives Prestigious 2017 ACM A.M. Turing Award

Mar 20, 2018

A Look Back at the Evolution of RISC-V and a Peek at What’s Next from Krste Asanović

Mar 14, 2018

Semiconductor Engineering Article: Heterogeneous Hubbub

Mar 14, 2018

DesignNews Article: First Open-Source RISC-V SoC For Linux Released

Mar 14, 2018

ElectronicsWeekly Article: QuickLogic Joins RISC-V Foundation

Mar 14, 2018

EE Times Article: Time for 'Open Innovation,' Not Just Open Source

Mar 13, 2018

RISC-V Foundation Embedded World 2018 Recap

Mar 12, 2018

QuickLogic Joins RISC-V Foundation

Mar 9, 2018

Opensource.com Article: Open Standards In Processor Innovation With RISC-V

Mar 8, 2018

eeNews Europe Interview With Rick O'Connor Of RISC-V Foundation

Mar 6, 2018

Stacey On IoT Article: GreenWaves Technologies Joins The Race For Machine Learning At The Edge

Mar 1, 2018

VentureBeat Article: GreenWaves Technologies Unveils Gap8 Processor For AI At The Edge

Mar 1, 2018

Embedded Computing Design Interview With UltraSoC At Embedded World 2018

Mar 1, 2018

Embedded Computing Design Interview With GreenWaves Technologies At Embedded World 2018

Mar 1, 2018

Embedded Computing Design Interview With VectorBlox At Embedded World 2018

Mar 1, 2018

Embedded Computing Design Interview With Imperas At Embedded World 2018

Mar 1, 2018

Embedded Computing Design Interview With Antmicro At Embedded World 2018

Mar 1, 2018

Embedded Computing Design Interview With RISC-V Foundation At Embedded World 2018

Feb 28, 2018

Trinamic Licenses Codasip's Bk3 RISC-V Processor for Next Generation Motion Control Applications

Feb 28, 2018

EE Journal Video: Mi-V Ecosystem For RISC-V Developers — Microsemi

Feb 28, 2018

EE Journal Article: GreenWaves Puts Another Spin On IoT Chips

Feb 27, 2018

CUBEConversation With Martin Fink and Dave Tang

Feb 27, 2018

Android Headlines Article: GreenWaves Intros Open-Source AI Processor GAP8

Feb 27, 2018

Read IT Quik Article: GreenWaves Technologies Unveils GAP8 IoT Application Processor

Feb 27, 2018

Sensors Online Article: Moore’s Law Is Dead: So, Let’s Talk About The Future Of SoCs

Feb 26, 2018

CEVA Extends Its IP Platforms For Bluetooth And Wi-Fi With RISC-V

Feb 26, 2018

RISC-V RV64GC High-Performance Extendable Platform Kit For Fast Linux Execution Released By Imperas

Feb 26, 2018

Ashling And Imperas Partner To Extend The RISC-V Ecosystem

Feb 26, 2018

New Electronics Article: IoT Apps Processor Boasts Eight RISC-V Cores

Feb 26, 2018

EETimes Article: AI Comes To Sensing Devices

Feb 26, 2018

GreenWaves Technologies Unveils GAP8, The Industry’s Lowest Power IoT Application Processor, Enabling Groundbreaking Embedded Artificial Intelligence At The Very Edge

Feb 23, 2018

RISC-V E-Newsletter Winter 2018

Feb 23, 2018

Embedded Computing Design Article: Open source RISC-V Architecture Is Changing The Game For IoT Processors

Feb 22, 2018

SiliconANGLE Article: RISC-V Plans To Fulfill Open-source Architecture Innovation Dreams

Feb 22, 2018

Sensors Magazine Article: Industrial-Grade IoT Platform Supports RISC-V Architecture

Feb 22, 2018

Embedded Computing Design Article: A New Era Of Storage: Open Compute With RISC-V And Memory Fabrics

Feb 20, 2018

Design News Article: First Open-Source RISC-V SoC For Linux Released

Feb 20, 2018

Design & Reuse Article: UltraSoC And Lauterbach RISC-V Collaboration Furthers Vendor-neutral Debug And Development Environment

Feb 20, 2018

Electronics Weekly Article: Embedded World: Lauterbach And UltraSoC Back RISC-V

Feb 15, 2018

RISC-V Workshop in Barcelona – Call for Papers

Feb 14, 2018

Military Embedded Systems Article: Using RISC-V In FPGAs For Strategic Defense Systems

Feb 12, 2018

RISC-V Ecosystem Shares ISA Developments At Embedded World 2018

Feb 12, 2018

Linux Blog Post: First Linux-Based RISC-V Board Prepares For Take-Off

Feb 12, 2018

Hackday Article: A RISC-V That The Rest Of Us Can Understand

Feb 9, 2018

theCube Video: Western Digital Talks RISC-V and the Freedom to Innovate

Feb 7, 2018

Bit-tech Article: SiFive announces 64-bit 1.5GHz RISC-V HiFive Unleashed SBC

Feb 7, 2018

SiFive Launches World’s First Linux-Capable RISC-V Based SoC

Feb 5, 2018

TechRepublic Article: Hi-Five Unleashed: The First Linux-Capable RISC-V Single Board Computer Is Here

Jan 31, 2018

ElectronicDesign Article: 11 Myths About The RISC-V ISA

Jan 29, 2018

Sensors Online Article: RISC-V Processor Trace IP An Industry First

Jan 25, 2018

The Benchmark Company Session: RISC‐V Positioned to Drive Processor Industry Innovation Across SoC/MCU Development Roadmaps

Jan 25, 2018

Electronics Weekly Article: RISC-V Processor Trace IP Available

Jan 24, 2018

EENews Europe Article: Codasip's Studio: 7th Edition For The Easy Configuration Of RISC-V Processors

Jan 23, 2018

Codasip Announces Studio 7, Design and Productivity Tools for Rapid Generation of RISC-V Processors

Jan 22, 2018

Barron's Article: Nvidia, Western Digital At Chips’ Frontier

Jan 19, 2018

RISC-V At Embedded World 2018

Jan 18, 2018

Semiconductor Engineering Article: Predictions: Manufacturing, Devices And Companies

Jan 17, 2018

Microsemi Announces Its Entire Product Portfolio Is Unaffected By Spectre And Meltdown Vulnerabilities

Jan 17, 2018

Electronics Weekly Article: Microsemi Products Free From Spectre And Meltdown Vulnerabilities

Jan 17, 2018

EE Journal Article: The Bisquick Alternative

Jan 12, 2018

eeNews Europe: Dresden Firm Takes FDSOI Down To 0.4V

Jan 10, 2018

Future Ships Avalanche FPGA Dev Board With RISC-V Core

Jan 10, 2018

New Electronics Article: Avalanche Board Featuring Microsemi’s PolarFire FPGAs

Jan 9, 2018

Sensors Online Article: Dev Board Supports PolarFire FPGAs

Jan 5, 2018

Reduced Energy Microsystems Joins FDXcelerator Program To Bring RISC-V IP To GLOBALFOUNDRIES' 22FDX Technology Process

Jan 5, 2018

Forbes Article: Western Digital Gives A Billion Unit Boost To Open Source RISC-V CPU

Jan 5, 2018

Tom's Hardware Article: RISC-V Foundation Trumpets Open-Source ISAs In Wake Of Meltdown, Spectre

Jan 4, 2018

Building a More Secure World with the RISC-V ISA

Jan 4, 2018

AB Open Article: Esperanto Announces 4,112-Core RISC-V AI Chip

Jan 4, 2018

Semiconductor Engineering Article: Reflection On 2017: Design And EDA

Jan 4, 2018

Seeking Alpha Article: Benchmark: WDC, NVDA Adding Fuel To RISC-V Movement

Jan 4, 2018

Barron's Article: Western Dig, Nvidia On Board with ‘RISC-V,’ So Pay Attention, Says Benchmark

Jan 4, 2018

Electronic Design Article: These 2017 Embedded Trends Will Thrive in 2018

Jan 2, 2018

Semiconductor Engineering Article: Reflections On 2017: Manufacturing And Markets

Jan 2, 2018

EETimes Article: 8 Top Innovations Of 2017

Jan 2, 2018

Fuse Article: Esperanto Exits Stealth Mode, Aims At AI With A 4,096-core 7nm RISC-V Monster

Dec 22, 2017

EE Times Japan article on RISC-V Day 2017 Tokyo

Dec 15, 2017

Sensors Online Article: Extendable Platform Kit Drives FPGA-Based RISC-V Designs

Dec 15, 2017

AnandTech Article: Western Digital To Use RISC-V For Controllers, Processors, Purpose-Built Platforms

Dec 15, 2017

EE Journal Article: Visualizing Real-Time Issues Swedish Company Gives Developers Better Insight

Dec 15, 2017

eeNews Europe Article: Extendable Platform Kit To Ease Adoption Of FPGA-Based RISC-V Designs

Dec 15, 2017

Electronics Weekly Article: Microsemi And Imperas Develop RISC-V ISS

Dec 13, 2017

Embedded Computing Design Podcast: Five Minutes With…Jack Kang, VP Of Product And Business Development, SiFive

Dec 11, 2017

Embedded Computing Design Article: Inflection Point For RISC-V: The 7th RISC-V Workshop In Silicon Valley

Dec 11, 2017

Product Design and Development Article: SiFive, Microsemi Collaborate On RISC-V Development

Dec 11, 2017

ElectronicDesign Article: Getting “Creative” With RISC-V

Dec 9, 2017

7th RISC-V Workshop Recap

Dec 9, 2017

7th RISC-V Workshop Proceedings

Dec 8, 2017

SEGGER Presents RTOS, Stacks, Middleware For RISC-V

Dec 7, 2017

Embedded Computing Design Podcast: Five Minutes With…Rick O’Connor, Executive Director, RISC-V Foundation

Dec 7, 2017

SiFive Joins Microsemi's New Mi-V Ecosystem To Accelerate Adoption Of RISC-V Open Instruction Set Architecture

Dec 6, 2017

Forbes Article: Western Digital Gives A Billion Unit Boost To Open Source RISC-V CPU

Dec 6, 2017

DesignNews Article: Western Digital Transitions To RISC-V Open-Source Architecture For Big Data, IoT

Dec 6, 2017

Andes Announces Advanced SoC Development Environment for V5 AndesCore™ N25 And NX25 Processors With Tool Partners

Dec 6, 2017

UltraSoC Selected By Microsemi For Growing RISC-V Product Range

Dec 4, 2017

Intrinsix Cryptographic IP Selected By DARPA For Use In CHIPS Program, Featuring RISC-V Security Processor

Dec 1, 2017

The Register Article: WDC To Move All Its Stuff To RISC-V Processors, Build Some Kind Of Super Data-Wrangling Stack

Dec 1, 2017

Forbes Article: RISC-V Enables Smart Storage Devices

Nov 29, 2017

eWeek Article: How WD Plans to Lead Major Changeover to RISC-V Processing

Nov 29, 2017

Embedded Computing Design Article: Codasip Releases 64-bit RISC-V Processor

Nov 29, 2017

Embedded Computing Design Article: Inside Secure Releases RISC-V Root-of-Trust Engine

Nov 29, 2017

Data Economy Article: Western Digital Steps Up Game In The Cloud Data Center and Edge Computing Markets

Nov 29, 2017

eeNews Europe Article: Startup Plans 4k RISC-V Cores on 7nm Chip

Nov 29, 2017

Tom's Hardware Article: Big Tech Players Start To Adopt The RISC-V Chip Architecture

Nov 29, 2017

SiFive Building RISC-V Ecosystem, One Partnership at a Time

Nov 29, 2017

RISC-V Processor Developer Suite Announced by Imperas

Nov 28, 2017

Rust Comes to RISC-V

Nov 28, 2017

Embedded Computing Design Article: Esperanto Technologies to Develop Energy-Efficient AI Chips on RISC-V Architecture

Nov 28, 2017

EE Times Article: RISC-V Spins into Drives, AI

Nov 28, 2017

Esperanto Technologies Plans Energy-Efficient Chips for Artificial Intelligence and Machine Learning, Based on the Open RISC-V Standard

Nov 28, 2017

Western Digital to Accelerate the Future of Next-Generation Computing Architectures for Big Data and Fast Data Environments

Nov 28, 2017

SiFive Advances Custom Silicon Industry with New Partnerships, Products at 7th RISC-V Workshop

Nov 28, 2017

SiFive Joins FDXcelerator Program to Bring RISC-V Core IP to GLOBALFOUNDRIES’ 22FDX Process Technology

Nov 28, 2017

Reduced Energy Microsystems Joins RISC-V Foundation

Nov 28, 2017

Renode 1.2 With RISC-V Support To Be Presented At 7th RISC-V Workshop

Nov 28, 2017

SiFive and Microsemi Expand Relationship with Strategic Roadmap Alignment and a Linux-Capable, RISC-V Development Board

Nov 28, 2017

Codasip Announces Bk5-64, A New 64-Bit RISC-V Processor

Nov 23, 2017

SEGGER Embedded Studio Supports RISC-V Architecture

Nov 21, 2017

Check Out the Open Source Electronic Badge for the 7th RISC-V Workshop

Nov 20, 2017

Andes Announces Advanced SoC Development Environments for V5 AndesCore N25 and NX25 Processors with Tool Partners

Nov 20, 2017

Andes and Imperas Partner to Deliver Models and Virtual Platforms for Andes RISC-V Cores

Nov 20, 2017

Embedded Tools Provider Ashling Joins RISC-V Foundation

Nov 15, 2017

Rambus Selects Codasip Studio for SDK Development of RISC-V Processor

Nov 15, 2017

Inside Secure Unveils Industry’s First Root-of-Trust Solution Based on RISC-V Processor

Nov 15, 2017

Inside Secure Joins RISC-V Foundation

Nov 14, 2017

UltraSoC Selected by Microsemi for Growing RISC-V Product Range

Nov 9, 2017

FactorDaily Article: Meet The Brains Behind India’s Ambitious Processor Project From IIT, Madras

Nov 7, 2017

RISC-V Ecosystem Surpasses 100 Members Globally, Paving the Way for the Next 50 Years of Computing Design and Innovation

Nov 2, 2017

SemiAccurate Article: FlexLogix Joins SiFive’s DesignShare Program

Oct 31, 2017

Flex Logix to Provide Embedded FPGA IP to 'DesignShare' for SiFive Freedom Platform

Oct 25, 2017

SemiWiki.com Article: Open Source RISC-V ISA Brings A New Wrinkle To The Processor Market

Oct 24, 2017

Andes 32-bit CPU IP Cores Implemented on GLOBALFOUNDRIES 22FDX® Process Technology

Oct 24, 2017

Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores

Oct 24, 2017

EE Journal Article: The People’s Processor, Microsemi Rolls Out “Mi-V” RISC-V Ecosystem

Oct 23, 2017

Electronic Design Article: RISC-V FPGA Design Leaps Forward with Mi-V

Oct 20, 2017

RISC-V E-Newsletter October 2017

Oct 19, 2017

Papers from the First Workshop on Computer Architecture Research with RISC-V (CARRV 2017)

Oct 19, 2017

Microsemi Launches Mi-V Ecosystem to Accelerate Adoption of RISC-V

Oct 18, 2017

7th RISC-V Workshop Showcases Breadth of the RISC-V Ecosystem with More Than 45 Sessions Featuring Technology Leaders

Oct 8, 2017

7th RISC-V Workshop Agenda

Oct 6, 2017

Design News Article: Linux Now Has its First Open Source RISC-V Processor

Oct 3, 2017

RISC-V Ecosystem to Present at 15th International System-on-Chip (SoC) Conference, Exhibit & Workshops

Sep 26, 2017

RISC-V Ecosystem to Showcase New Implementations of RISC-V ISA at Linley Processor Conference 2017

Sep 7, 2017

7th RISC-V Workshop Registration

Aug 16, 2017

RISC-V Foundation to Showcase Growth of New Architecture at Hot Chips 29

Jun 30, 2017

RISC-V E-Newsletter June 2017

Jun 29, 2017

7th RISC-V Workshop Call for Papers

Jun 4, 2017

7th RISC-V Workshop Save the Date

May 28, 2017

6th RISC-V Workshop Proceedings

May 1, 2017

6th RISC-V Workshop Agenda

Apr 22, 2017

The RISC-V Memory Consistency Model

Mar 10, 2017

RISC-V Enters Mainstream at Embedded World 2017

Mar 3, 2017

6th RISC-V Workshop Registration and Call for Papers

Feb 17, 2017

IIT Madras RIC2017 April 2017

Feb 17, 2017

Open Source Silicon with RISC-V March 2017

Feb 13, 2017

RISC-V at EmbeddedWorld March 2017

Feb 5, 2017

RISC-V at FOSDEM February 2017

Jan 12, 2017

RISC-V Chosen as Best Technology of 2016

Dec 11, 2016

5th RISC-V Workshop Proceedings

Oct 28, 2016

5th RISC-V Workshop Agenda

Aug 25, 2016

5th RISC-V Workshop Registration and Call for Papers

Jul 26, 2016

RISC-V Founding Members and 4th Workshop Wrap Up

Jul 25, 2016

4th RISC-V Workshop Proceedings

Jul 11, 2016

4th RISC-V Workshop Final Agenda

Jun 10, 2016

Hands-On RISC-V Tutorial

Jun 9, 2016

RISC-V Foundation Appoints Board of Directors

May 30, 2016

RISC-V Sessions at DAC 2016

Apr 13, 2016

RISC-V Presentation at ESC Boston

Apr 1, 2016

RISC-V Offers Simple, Modular ISA

Mar 3, 2016

Charting a New Course for Semiconductors

Mar 1, 2016

4th RISC-V Workshop Registration and Call for Papers

Feb 20, 2016

4th RISC-V Workshop at MIT

Jan 23, 2016

3rd RISC-V Workshop Proceedings

Jan 10, 2016

3rd RISC-V Workshop Presentations & Breakouts

Dec 9, 2015

Prelim Agenda 3rd RISC-V Workshop

Nov 8, 2015

RISC-V Draft Compressed ISA version 1.9 released

Oct 1, 2015

RISC-V Talk at IoT Meetup, Mountain View, Calif.

Oct 1, 2015

RISC-V Talks at ORCONF-2015

Sep 11, 2015

RISC-V in Verilog

Aug 16, 2015

RISC-V at HotChips

Aug 5, 2015

Save the Date for the 3rd RISC-V Workshop, Jan. 5-6, 2016

Aug 5, 2015

RISC-V Foundation Incorporated!

Jul 29, 2015

2nd RISC-V Workshop Proceedings

Jul 14, 2015

EE Times: Open Source Core Advances

Jul 1, 2015

Thanks to Everyone for a Successful 2nd RISC-V Workshop!

Jun 25, 2015

Open vs. Proprietary ISAs at CARD 2015

Jun 2, 2015

Preliminary Agenda for the 2nd RISC-V Workshop is Posted!

May 29, 2015

RISC-V Draft Compressed ISA Version 1.7 Released

May 9, 2015

RISC-V Draft Privileged Architecture Version 1.7 Released

Apr 29, 2015

2nd RISC-V Workshop Call for Contributions

Apr 21, 2015

Registration Now Open!! 2nd RISC-V Workshop June 29 – 30, 2015

Apr 14, 2015

2nd RISC-V Workshop, June 29-30, 2015, Berkeley, CA.

Feb 9, 2015

RISC-V Github Organization

Feb 8, 2015

RISC-V Tutorial at HPCA 2015

Feb 5, 2015

RISC-V Tutorial at HPCA 2015

Jan 28, 2015

Videos of Talks from the 1st RISC-V Workshop and Bootcamp are now Online!

Jan 19, 2015

1st RISC-V Workshop, a Resounding Success!

Jan 14, 2015

1st RISC-V Workshop Proceedings

Jan 13, 2015

A Linux Distribution for RISC-V

Jan 13, 2015

Announcing the RISC-V GCC 4.9 Port and New ABI

Dec 11, 2014

First RISC-V Workshop Space Running Out!

Nov 20, 2014

Early Bird Registration for the First RISC-V Workshop is Ending Soon!

Oct 15, 2014

Video of Stanford EE380 Talk on RISC-V Available Online

Oct 14, 2014

Get Answers On Stack Overflow!

Oct 12, 2014

Why Not Build on OpenRISC?

Oct 11, 2014

RISC-V Article in Swedish Magazine Elektronik Tidningen

Oct 7, 2014

Launching the Open-Source Rocket Chip Generator!

Oct 7, 2014

About our Dhrystone Benchmarking Methodology

Sep 26, 2014

RISC-V at ESSCIRC-2014

Sep 25, 2014

RISC-V Analysis by Adapteva Founder

Sep 24, 2014

"Instruction Sets Should be Free" tech report, now available in Russian

Sep 24, 2014

ARM's rebuttal to RISC-V: "The Case for Licensed Instruction Sets"

Sep 12, 2014

Hear about RISC-V on EE Times Radio

Aug 12, 2014

RISC-V at HotChips-26

Aug 7, 2014

RISC-V on EE Times

Aug 5, 2014

RISC-V Just Got a New Logo!

Jul 29, 2014

RISC-V QEMU port

Jul 2, 2014

RISC-V GDB port

May 6, 2014

RISC-V User-Level ISA Version 2.0 is released!

Mar 6, 2014

RISC-V LLVM released!

Mar 5, 2014

Boot RISC-V Linux in your web browser!

Jan 18, 2014

ISA Specification Version 2.0-1e-4 Now Available

Aug 26, 2013

RISC-V Poster at Hot Chips Conference!

Aug 2, 2013

New Draft ISA Specification Version 1.999 Available

Jul 26, 2013

Draft Website is Up to Public!

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Becoming a member of RISC-V International allows companies and individuals to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs.