Open Standard RISC-V Verification Interface (RVVI) for SOC testing | Nick Flaherty, EE News Europe

Imperas Software in the UK has extended the RVVI (RISC-V Verification Interface) with virtual peripherals to support asynchronous events and system level interrupts.

RVVI is an open specification with a common methodology for the key components of the testbench to connect the RISC-V processor RTL instruction trace and reference models to fully support the lock-step-compare co-simulation.

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