Claude (AI) Codes a RISC-V Core in TL-Verilog

TL-Verilog has the promise to help humans and LLMs collaborate effectively and safely on digital circuits. But first, we need to teach LLMs TL-Verilog. I explore the ability of today’s LLMs to learn TL-Verilog conversationally by giving Claude the opportunity to successfully complete the course “Building a RISC-V CPU Core”.

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