The tool suite automatically analyzes shared memory and measures worst-case execution time to ensure deterministic execution time for RISC-V processors.
Developers working on real-time and safety-critical systems—particularly in aerospace, automotive, medical, and industrial sectors—have long struggled with one persistent issue: predicting and verifying worst-case execution time in multicore environments.
With its March 2025 update, LDRA has taken a direct step to remove this barrier for RISC-V users. The company’s tool suite now automates key analysis tasks that were once time-consuming and expensive, helping engineering teams build systems that are not only safe and secure but also deterministic and certifiable.