The Register Article: Brains Behind seL4 Secure Microkernel Begin RISC-V Chip Port

Last week, the first RISC-V port of its seL4 microkernel was released by the Data61 division of the Australian government’s Commonwealth Scientific and Industrial Research Organisation (CSIRO).
seL4 is an open-source and highly secure version of the L4 microkernel that aims to be mathematically proven to be bug free, in that it works as expected as per its specifications. Meanwhile, RISC-V is an open-source instruction-set architecture, and is used as the blueprint for various open-source processor core designs – some of which are now shipping as real usable silicon, such as chips from SiFive and Greenwaves.
To read more, please visit: http://www.theregister.co.uk/2018/04/23/risc_v_sel4_port/