The De-RISC Project celebrates its second year through the introduction of a market-ready hardware-software platform based on the RISC-V instruction set architecture (ISA), productizing a multi-core RISC-V system-on-chip and an efficient time and space partitioning hypervisor.
“I am proud of the great achievements that the De-RISC team have reached in these two years,” Paco Gómez-Molinero, coordinator of the project, said. “With hard work and enthusiasm, we managed to achieve the major project goals, and the team is highly motivated to continue with the positive development effort of the project”.
This H2020 project started in October 2019 and continues paving its way after two years of intense work which will run until September 2022. Throughout the project’s second year, the four members of the consortium have been able to progress not only in different hardware and software developments, but also in the validation strategy which will cover the different tests required to ensure that the system adheres to specification.