Skip to main content

RISC-V Summit China 2025 begins THIS WEEK! | July 16-19 | Register Today

Ecosystem News

Claude (AI) Codes a RISC-V Core in TL-Verilog

By September 20, 2023No Comments

TL-Verilog has the promise to help humans and LLMs collaborate effectively and safely on digital circuits. But first, we need to teach LLMs TL-Verilog. I explore the ability of today’s LLMs to learn TL-Verilog conversationally by giving Claude the opportunity to successfully complete the course “Building a RISC-V CPU Core”.

Read the full article.