Proceedings & Reports

RISC-V Global Forum: Proceedings

By September 30, 2020No Comments

The RISC-V Global Forum was held as a virtual event on September 3, 2020. The event spanned 18 hours and included keynotes and presentations from around the world. It was attended by more than 700 people across 42 countries.

The Global Forum had three tracks comprising Keynotes, Technical talks, and Industry talks. All are cataloged here.


Keynote: RISC-V Right here. Right now.Calista Redmond, CEO, RISC-V Internationalnone
Keynote: RISC-V in ChinaDr. Guangnan Ni, Academician of the Chinese Academy of Engineeringnone
Keynote: RISC-V in Academia and EducationStefan Wallentowitz, Professor, Munich University of Applied Sciences & Calista Redmond, CEO, RISC-V Internationalnone
Keynote: RISC-V - A User's PerspectiveLoic Lietar, CEO GreenWaves Technologies SASnone
Keynote: RISC-V State of the UnionKrste Asanovic, Chairman of the Board, RISC-V InternationalSlides
Keynote: EPI, The European Approach for Exascale ages. The Road Toward SovereigntyJean-Marc Denis, Chair of the Board, European Processor InitiativeSlides
Keynote: CHIPS Alliance: The Open Source Hardware RoadmapZvonimir Bandic, Chairman, CHIPS Alliance & Sr Director, Western Digital Corporationnone
Keynote: NVIDIA’s secure RISC-V processorFrans Sijstermans & Joe Xie, NVIDIAnone
Keynote: The First Decade of RISC-V: A Worldwide PhenomenonDavid Patterson, Vice Chair, RISC-V InternationalSlides
Keynote: An Investor Perspective on RISC-V, The Opportunities and Challenges AheadGuru Chahal, Partner, Lightspeed Venture Partnersnone
Keynote: Information Revolution, Chips, and OpennessShahin Khan, Founding Partner & Analyst, OrionX.netnone
Keynote: Closing RemarksCalista Redmond, CEO, RISC-V Internationalnone

Technical Presentations

Portable Implementation of GlobalPlatform API for TEEKenta Nakajima & Kuniyasu Suzaki, Technology Research Association of Secure IoT Edge Application Based on RISC-V Open Architecture (TRASIO)Slides
Andes RISC-V Processors for Control and Data PathsCharlie Su, Andes Technology CorporationSlides
PicoRio: An Open-Source, RISC-V Small-Board Computer To Elevate The RISC-V Software EcosystemZhangxi Tan, RIOS Labnone
Support TVM QNN Flow on RISC-V with SIMD ComputationYi-Ru Chen & Jenq-Kuen Lee, National Tsing Hua University, TaiwanSlides
Optimize Openblas by RISC-V "V" Vector ExtensionXianyi Zhang, PerfXLabSlides
An Introduction to RISC-V Vector Programming with C IntrinsicsChih-Mao Chen, Andes Technologynone
ProtoCPU: Modelling an In-Order RISC-V Core in gem5Anuj Justus Rajappa, IIT Madrasnone
Using Formal to Vaccinate RISC-V Designs Against Catastrophic BugsDr. Ashish Darbari, AXIOMISEnone
Optimizing RISC-V Custom Instructions with Software Driven Analysis and ProfilingDuncan Graham & Simon Davidmann, Imperas SoftwareSlides
Trusted Execution State: An Extension for Lightweight Secure Function CallingMark Hill, Huawei Technologies R&D (UK) LtdSlides
The Case for RISC-V in SpaceGianluca Furano, European Space AgencySlides
Riscof - A Risc-V Compliance Framework and MoreNeel Gala, InCore SemiconductorsSlides
Noel-V: A New High-Performance RISC-V Processor FamilyJohan Klockars & Alen Bardizbanyan, Cobham Gaisler ABSlides
Cloud-based Verification of Open Source RISC-V Cores Using the Metrics Cloud Platform and Codasip SweRV Support PackageRoddy Urquhart, Codasip & Dan Ganousis, Metrics Design AutomationSlides
Verifying All the Flexibility of RISC-V within SoC DV Test PlansSimon Davidmann & Lee Moore, Imperas SoftwareSlides
RISC-V True Random Number Generation: Probably Too Important to be Left to ChanceMarkku-Juhani O. Saarinen, PQShield Ltd.Slides
Where Is the 32-Bit Glibc Port?Alistair Francis, Western Digitalnone
An Automated Scalable RISC-V Cache Coherency Verification ProjectAdnan Hamid, Breker Verification Systems, Inc.none
Unlocking Javascript: V8 on RISC-VPeng Wu & Brice Dobry, Futurewei Technologiesnone
Code Size Compiler Optimizations and Techniques for Embedded SystemsAditya Kumar, FacebookSlides
RVfpga: Using A Commercial RISC-V Processor to Teach Computer Architecture for the Next Generation of Engineers and Computer ScientistsSarah L. Harris, University of Nevada, Las Vegas & Daniel A. Chaver Martinez, Associate Professor, University Complutense of MadridSlides