RISC-V Day Tokyo Agenda
Oct. 18, 2018
RISC-V Day Tokyo will be a single-day event on Thursday, Oct. 18 that will feature presentations and keynotes highlighting the RISC-V ecosystem’s growth around the world. At RISC-V Day Tokyo, the RISC-V community will share updates on new projects and implementations from its international membership, with a focus on current and prospective RISC-V projects and implementations that showcase the RISC-V ecosystem across Asia. RISC-V Foundation member companies presenting at RISC-V Day in Tokyo include Andes Technologies, Esperanto Technologies, Microchip Technologies, SiFive, Syntacore and UltraSoC.
RISC-V Day Tokyo is being hosted by Keio University in Yokohama, Kanagawa. At Keio University the event will take place at Fujiwara Hall in the Kyosei Building at the Hiyoshi Campus.
Thursday, Oct. 18, 2018 RISC-V Day Tokyo
| Time | Event | Speaker, Affiliation | Slides & Videos |
| 8:00am | Registration is open from 8:00 a.m. – 9:15 a.m. | ||
| 9:15am | Welcome | Hideharu Amano, Keio University | |
| 9:30am | A Perspective on the Role of Open-Source IP In National AI Chip Electronics Projects | ||
| 9:40am | Introduction of Technologies and People Supporting RISC-V Ecosystem | Msyksphinz, FPGA Diary Author | |
| 9:55am | Fedora on RISC-V – Status and Plan | Wei Fu, Red Hat | |
| 10:10am | RISC-V Architecture Update | Krste Asanovic, UC Berkeley and SiFive | |
| 10:30am | Keynote: RISC-V, AI and Innovation | Dave Ditzel, Esperanto Technologies | |
| 11:00am | Networking Break | ||
| 11:30am | Security and Hypervisor: Hypervisor Extension | Andrew Waterman, SiFive | |
| 11:45am | RISC-V Open-Source Models and Virtual Platforms Coupled with Commercial Grade Simulation Technologies and Tools | Shuzo Tanaka, eSOL TRINITY Co. Ltd. | |
| 12:00pm | Keynote: Making of the RISC-V Reader Japanese Translation | Andrew Waterman, SiFive; Eiji Yokota, Nikkei BP Consulting; Hideya Kawahara, SH Consulting | |
| 12:15pm | Embracing a System Level Approach in the Real World: Combining Arm & RISC-V in Heterogeneous Designs | Gajinder Panesar, UltraSoC | |
| 12:30pm | Implementing 64-bit RISC-V Chip with MMU, L1 and L2 Using Academic Shuttle in Japan | Kesami Hagiwara, University of Electro-Communications | |
| 12:45pm | Lunch | ||
| 14:10pm | RISC-V Asia Pacific Regional Marketing Activities | Alex Guo, Jinglue Semiconductor; Naomi Tsujioka, SH Consulting | |
| 14:25pm | Keynote: The Future of Broadcast and Broadband Services, and Expectation to Processors | ||
| 14:45pm | Keynote:AI-nization of Rakuten, Inc. | ||
| 15:15pm | Networking Break | ||
| 15:45pm | The Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor | Polychronis Xekalakis and Christopher Celio, Esperanto Technologies | |
| 16:00pm | TEE to Run Trusted OS on RISC-V and Related Technologies | ||
| 16:15pm | Extending RISC-V Solutions for AIoT | Charlie Su, Andes Technology Corporation | |
| 16:30pm | Mi-V Embedded Ecosystem | Krishnakumar Ranamoorthi, Microchip Technologies | Slides |
| 16:45pm | The SCR Family of RISC-V Compatible Processor IP | Alexander Redkin, Syntacore | |
| 17:00pm | Networking Break | ||
| 17:25pm | Opportunities and Challenges of Building Silicon in the Cloud | Krste Asanovic, UC Berkeley and SiFive | |
| 17:45pm | CloudBEAR Processor IP Product Line | Alexander Kozlov, CloudBEAR | |
| 18:00pm | FIPS140-2 Compliant Trust Module for RISC-V Core Complex | Shumpei Kawasaki, SH Consulting KK | |
| 18:15pm | OpenWrt Porting for RISC-V | Alex Guo, Jinglue Semiconductor | |
| 18:30pm | Performance and Cost Efficiency of Big-Endian on RISC-V | Kuniyasu Suzaki, AIST: National Institute of Advanced Industrial Science and Technology | |
| 18:45pm | Closing remarks |