RISC-V Foundation Showcases Unprecedented Momentum and Growth at Embedded World 2020 

The RISC-V Foundation booth will include live demonstrations and talks of RISC-V implementations from fourteen members WHERE: Hall 3A, Booth No. 3A-536, NürnbergMesse, Messezentrum 1, 90471 Nürnberg, Germany WHEN: Tuesday, Feb. 25 – Thursday, Feb. 27, 2020 WHAT: At Embedded World 2020, the RISC-V Foundation will be exhibiting at Hall 3A, Booth No. 3A-536, and will feature live demonstrations from co-exhibiting RISC-V Foundation members Andes Technology, CHIPS Alliance, CloudBEAR, Codasip, Embecosm, GreenWaves Technologies, Imperas Software, Intrinsic ID, OneSpin Solutions, OpenHWGroup, SiFive, Syntacore and UltraSoC. Throughout the conference, the booth will feature talks from RISC-V Foundation members. The RISC-V Foundation will also be hosting a scavenger hunt across the show floor, encouraging attendees to visit different booths in the RISC-V ecosystem for the chance to win prizes.  The main conference program will also feature a variety of RISC-V classes and sessions, focusing on how the RISC-V ISA can be leveraged for embedded security, tools and verifications, operating systems, system technologies and so much more. Speaking sessions and classes include the following:

CLASS 5.1: How to Secure RISC-V and Cortex-M Embedded Applications (Feb. 25)

• How to Build & Secure a RISC-V Embedded System
  • When: 14:30 – 16:00 CET
  • Who: Cesare Garlati, Hex Five Security; Prof. Sandro Pinto, Universidade do Minho 
  • Location: Conference Counter NCC Ost
• How to Build Hardware-enforced Software-defined Separation in Cortex-M Devices
  • When: 16:00 – 18:00 CET
  • Who: Cesare Garlati, Hex Five Security; Rangarajan Anand, Microchip Technology Inc.
  • Location: Conference Counter NCC Ost

SESSION 10.3: SoC III – Tools & Verification (Feb. 25)

• Impact of RISC-V Adaptability on SoC Verification Methods
  • When: 14:30 – 15:00 CET
  • Who: Simon Davidmann, Imperas Software
  • Location: Conference Counter NCC Ost
• Verification of RISC-V SoC Designs Using Formal Methods
  • When: 15:00 – 15:30 CET
  • Who: Sven Beyer, OneSpin Solutions
  • Location: Conference Counter NCC Ost

SESSION 3.2: II Embedded OS IV – Linux II (Feb. 26)

• A Clean Slate Approach to Embedded Linux Security: RISC-V Enclaves
  • When: 17:00 – 17:30 CET
  • Who: Cesare Garlati, Hex Five Security
  • Location: Conference Counter NCC Ost

SESSION 10.4: II SoC V – System Technology II (Feb. 26)

• RISC-V Hardware and Software Technology for Industry
  • When: 14:30 – 15:00 CET
  • Who: Prof. Robert Oshana, NXP Semiconductors N.V.; Rick O’Connor, OpenHW Group
  • Location: Conference Counter NCC Ost

• An Enclave-based TEE for SE-in-SoC in RISC-V Industry
  • When: 15:00 – 15:30 CET
  • Who: Vincent Cui, T-HEAD Semiconductor Inc. / Alibaba Group
  • Location: Conference Counter NCC Ost

Exhibitor Forum (Feb. 26) 

• Introducing the World’s First RISC-V based MCU – GD32VF103x
  • When: 13:00 – 13:30 CET
  • Who: Reuben Townsend, GigaDevice Semiconductor Inc.
  • Location: Exhibitor Forum, Hall 3A, 3A-730

SESSION 3.3 II Embedded OS VI – Virtualization & Partitioning II (Feb. 27)

• Multi Zone Security for Cortex-M Devices
  • When: 14:30 – 15:00 CET
  • Who: Cesare Garlati, Hex Five Security
  • Location: Conference Counter NCC Ost

SESSION 5.4 Hardware IV – Applications (Feb. 27)

• Case Study: Embedded RISC-V for Storage
  • When: 9:30 – 10:00 CET
  • Who: Ted Marena, Western Digital
  • Location: Conference Counter NCC Ost

SESSION 5.5 Hardware V – Architectures (Feb. 27)

• Leveraging the Scalability of the RISC-V ISA to Create Optimized MCU Designs
  • When: 13:30 – 14:00 CET
  • Who: Yunsup Lee, SiFive Inc.
  • Location: Conference Counter NCC Ost
• The ParaNut/RISC-V Processor – An Open, Parallel, and Highly Scalable Processor Architecture for FPGA-based Systems
  • When: 14:30 – 15:00 CET
  • Who: Alexander Bahle, University of Applied Sciences Augsburg
  • Location: Conference Counter NCC Ost
• Software PPA for RISC-V: Results from Real-world MCU Security Applications
  • When: 15:30 – 16:00 CET
  • Who: Prof. Robert Oshana, NXP Semiconductors N.V.
  • Location: Conference Counter NCC Ost
• A Cycle-accurate Trace Approach for RISC-V Systems
  • When: 16:00 – 16:30 CET
  • Who: Gajinder Panesar, UltraSoC
  • Location: Conference Counter NCC Ost

Read more about RISC-V activities at Embedded World here: https://riscv.org/2020/02/risc-v-foundation-members-at-embedded-world-2020/. To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: www.risc-v.org. To schedule a meeting at Embedded World, please email RISC-V@racepointglobal.com.  About RISC-V Foundation RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 500 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. Media Contacts: Mark Sinclair Racepoint Global for RISC-V Foundation Phone: +1 (415) 694-6700 risc-v@racepointglobal.com     ]]>