The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies.
The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor IP core. But the processor IP business model is based on one-size-fits-all, which allows chip companies to amortize NRE (non-recurring engineering) across many projects. RISC-V implementations tend to be smaller and more customized, and in many cases significantly different from one project to the next.