Maintain Strict Economic Control of Your SDV Programs with RISC-V

The software-defined vehicle (SDV) has been a disruptor to the traditional automotive commercial model, creating both new opportunities and certain challenges for OEMs. On the one hand, when numerous vehicles all deploy the same operating system (OS) and third-party apps define features, it can be difficult for OEMs to differentiate their vehicles from the competition.

On the other hand, SDVs create new opportunities for accelerated development, quicker time to market, and the ability to continue updating and improving the vehicle long after it has left the factory. This can allow OEMs to significantly improve their development cost base and maximize additional aftermarket revenue.

An open, modular, and extensible ISA is uniquely placed to help automotive OEMs overcome the challenges posed by the switch to SDVs, and positively embrace the opportunities presented. As an industry open standard, there is no license fee or royalty associated with the RISC-V ISA itself.

The financial logic is direct. A chip’s unit cost scales with its silicon area, and its operating cost with the power it draws: every capability a chip carries that its function never uses is paid for three times over, in die cost, in energy, and in the cooling and wiring to support it.

A general-purpose part sized for the hardest job in the vehicle is oversized for most of the others. Workload-specific silicon reverses that: each chip carries the capability its function needs, plus deliberately scoped headroom for the updates and features planned across the vehicle’s life, and nothing else. Across the dozens of processors in a modern vehicle, and the volumes of a platform program, the difference between right-sized and oversized silicon is a permanent, structural cost advantage.

The RISC-V architecture can bring unique and defined benefits to automotive OEMs seeking to differentiate and enhance their commercial value proposition.

Development efficiency is achieved through a single, scalable architecture that spans the entire vehicle, from low-power controllers to high-performance computers. This unified approach simplifies development cycles, ensures code portability across different model tiers, and allows development teams to share toolchains, reducing re-engineering, staffing, and training costs. Additionally, the open ecosystem built around RISC-V provides reusable assets and more eyes for security audits, while a competitive, multi-vendor supply chain encourages innovation and favorable commercial terms.

For vehicle differentiation in the SDV era, RISC-V’s open and modular nature allows OEMs to co-design specialized hardware and software features, moving beyond standardized commercial off-the-shelf (COTS) hardware. RISC-V’s ratified vector extension – with matrix extension ratification work ongoing – supports complex AI-powered features like ADAS. OEMs can select standard extensions such as Vector for real-time tasks like sensor fusion, or add custom instructions where a feature genuinely needs hardware tuned to a single function, and can further differentiate feature sets by scaling the number of active RISC-V cores or clusters, simplifying supply chain planning.

Lastly, RISC-V helps capture aftermarket revenue. Its modularity ensures the underlying hardware remains capable of supporting complex software updates, in-field calibration, and additional features long after the initial sale: a key component of a viable SDV business model that enhances brand reputation and customer loyalty.

Functional safety (ISO 26262) and cybersecurity compliance represent an immense financial outlay over the lifecycle of any SDV platform, often costing OEMs tens of millions of dollars per platform program. When an OEM deploys a fragmented, proprietary hardware stack, every safety-critical workload, diagnostic coverage routine, and hypervisor must be independently re-engineered, re-tested, and re-certified for each chip family.

As vehicle features, characteristics, and performance become increasingly software-defined, OEMs risk losing some of their ability to effectively differentiate their models. The experience in adjacent segments such as smartphones is that consumer demand for premium brands or models can diminish when the feature set and performance are widely determined by a common third-party software platform and a selection of proprietary apps.

Automotive OEMs can still differentiate their product offering in the SDV era by deploying RISC-V solutions to move beyond standardized COTS hardware. Unlike proprietary processor architectures, RISC-V’s open and extensible nature allows OEMs to co-design hardware and software, creating specialized, differentiated features.

Building on a ratified profile such as RVA23, RVB23 or the upcoming RVM23 profile for microcontrollers, OEMs and their silicon partners choose which standard extensions to include: vector processing for AI-driven perception, hypervisor support for mixed-criticality consolidation, and cryptography for secure OTA. Custom instructions remain available for the rare feature that needs hardware tuned to a single function, but most Workload-Specific Silicon is built from standard, ratified building blocks. This gives OEMs a defensible way to differentiate silicon and vehicle performance while keeping software portable across the RISC-V ecosystem.

AI-enhanced functionality is becoming a crucial element of the vehicle’s feature set: Advanced Driver Assistance Systems (ADAS) and other safety features rely on real-time computation and inference to be effective. RISC-V’s ratified vector extension, with matrix extension ratification work ongoing, supports this class of AI-native compute directly. OEMs can use RISC-V’s extensible ISA to build automotive workload-specific accelerators directly into the vehicle’s silicon.

Read more about how RISC-V enables Pervasive AI across the SDV.

OEMs can further differentiate vehicle feature sets by scaling the number of active RISC-V cores or clusters, rather than redesigning the entire electronic control unit (ECU) for each model.

This is a distinct, complementary lever to Workload-Specific Silicon itself: scaling core or cluster count changes how much of a given design is deployed, while Workload-Specific Silicon changes what the design is scoped to do in the first place.

Used together, they can dramatically simplify supply chain planning and reduce inventory cost.

With the introduction of software-defined vehicles, OEMs can change, upgrade, or add new features while the vehicle is in the field. Controlling in-life upgrades allows OEMs to retain aftermarket revenue and strengthen relationships with their customer base. Choosing a RISC-V-based processor solution enhances an OEM’s ability to capitalize on post-sale opportunities.

Software-defined vehicles can change their functionality as part of an OEM’s ongoing aftermarket and service program. RISC-V’s modularity means chip designers can build in headroom: physical capability, such as compute margin, memory bandwidth, or virtualization support, beyond what day-one features require.

That headroom is what allows a vehicle’s software to keep evolving for years after launch without hitting a hardware wall. No OTA update can grant a capability the chip was never designed to have; headroom is what makes future updates possible in the first place. This helps avoid older components being unable to compute workloads as new tasks are added.

In commercial fleet management and vehicle leasing, depreciation is the single largest cost factor. Vehicles built on inflexible, legacy hardware quickly become obsolete, driving down resale prices at lease end and increasing overall fleet Total Cost of Ownership (TCO).

By provisioning RISC-V silicon with deliberate hardware headroom, OEMs ensure vehicles remain capable of accepting complex, feature-rich software updates throughout their operational lifespan.

This protects capital for captive finance organizations, allows OEMs to offer more competitive monthly lease rates, and gives commercial fleet operators a compelling financial reason to standardize on the platform.

Aftermarket revenue depends on hardware that stays supportable and sourceable for as long as the vehicle earns. How much of that an OEM can guarantee comes down to how the silicon was sourced and contracted: what you own determines what you can move, requalify, or hand to another partner.

The ownership models, and what a foundry move actually involves, are covered in Balance Economic Control With Ownership and IP Costs below. For multi-sourcing and vendor continuity, see Supply Chain Resilience.

This benefit isn’t limited to OEMs. Tier 1 suppliers carry the same exposure to a proprietary ISA licensor’s pricing and roadmap decisions, and the same structural advantage from RISC-V’s open licensing applies to them directly. Just as technology roadmap management should sit with the party building the product rather than a proprietary ISA licensor, program economics should not be subject to that owner’s varying strategic priorities, end-of-life decisions, or pricing changes over a 10–15 year horizon.

This is roadmap independence, and its consequence here is financial. Supply Chain Resilience covers how a licensor’s roadmap constrains what an OEM can get built: what matters to margin is that the constraint carries a price, and that price compounds across a 10–15 year program. The RISC-V ISA is openly licensed, so its licensing terms cannot be unilaterally changed by any single party, though commercial silicon and IP terms remain a separate negotiation with each vendor. Capital-allocation flexibility follows: savings and predictability can be reinvested in vehicle performance features and market differentiation, rather than absorbed by upstream costs and constraints.

Automotive platform lifecycles far outlast consumer electronics, spanning 10 to 15 years from initial design to end-of-life support. When proprietary chip vendors deprecate silicon families or alter compiler toolchains mid-program, OEMs are hit with massive “software archaeology” costs: forced to maintain obsolete software toolchains or refactor thousands of lines of legacy assembly code just to keep older fleets supported.

Standardizing on an open, vendor-independent instruction set architecture breaks this expensive debt cycle. Code written today remains portable and compilable decades later, regardless of whether original hardware vendors change business models, raise prices, or phase out specific silicon parts.

An automotive OEM’s ability to manage product differentiation, development efficiency, and aftermarket revenue collectively strengthens the overall customer value proposition and, in turn, the long-term margin position. RISC-V allows a degree of processor customization at the OEM level, ensuring that hardware product differentiation is still feasible in an SDV world. Reduced supply chain volatility risk and a more competitive supplier marketplace are structural margin advantages (see Supply Chain Resilience) that compound over volume.

Finally, RISC-V IP and chip vendors may set their own licensing and royalty terms: there are zero ISA licensing fees or royalties to use the RISC-V ISA itself, unlike with proprietary ISAs. As a single vehicle design typically uses multiple processor implementations, license fees for a proprietary ISA can mount up quickly. Furthermore, the commercial licensing terms for silicon IP are negotiated by the component vendor, and so sit outside the OEM’s direct control.

When an OEM or Tier 1 takes the decision to design its own Workload-Specific Silicon, or to commission that work from a design services company, the output is a blueprint for a new processor implementation: engineering source code known in the industry as RTL (register-transfer level). Any major foundry can turn that blueprint into physical silicon chips.

What the RISC-V open standard changes is the financial shape of this decision. With a proprietary ISA, the instruction set (and in almost every case, the core design) comes from the same company, on that company’s terms.

RISC-V is an open standard: the instruction set itself is freely available. The design and implementation of a chip that meets the RISC-V standard, however, is a separate, competitive decision. OEMs must choose both where the processor design comes from and how much of it to own. This decision might be made at a platform level, or by weighing up the merits of each approach for specific chips within the vehicle.

It is the combination of who designs the chip and who turns that design into physical silicon that determines who owns, and owes, what by the time that chip hits the road.

Taking control of silicon IP does not require designing every single transistor in-house. A pragmatic SDV silicon strategy establishes a clear financial boundary between bespoke differentiation and commercial convenience based on production volume and strategic impact.

High-Volume Central Compute & ADAS (Bespoke / In-House): High-throughput central processors and AI accelerators represent high-cost, high-margin components. For these workloads, the substantial up-front Non-Recurring Engineering (NRE) investment required for custom RTL design is amortized across a platform’s volume, yielding unit cost savings and architectural control.

Commodity Controllers & Microcontrollers (Commercial IP / Open Source): For deeply embedded, low-volume ECUs (e.g., door modules, seat actuators), minimizing initial engineering time outweighs incremental per-unit silicon savings. Here, licensing pre-verified commercial RISC-V IP or utilizing permissive open-source cores may deliver the optimal balance of speed and cost avoidance.