Pervasive AI

The open, AI-native RISC-V ISA carries intelligence to every tier of the vehicle, from experience-led AI in the digital cockpit to bounded, certifiable inference at the safety-critical edge.

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The Speed of Change

AI is Now the Fastest-Moving Part of Your Vehicle.

OEMs and Tier 1s are no longer asking whether artificial intelligence (AI) belongs in the vehicle, but how it can be deployed pervasively throughout it. AI is moving from a handful of headline features to the organizing principle of the software-defined vehicle (SDV), with a growing number of workloads machine-learned rather than hand-coded. These workloads run on purpose-built silicon, at different power budgets, under different safety obligations, in different corners of the vehicle. Some must handle mixed criticality. Some tolerate a round trip to the cloud. Some carry ASIL D consequences if they get it wrong.

That reach now extends across driver assistance, perception, cabin experience, energy management, predictive maintenance, and fleet learning – and it is arriving far faster than the traditional automotive development cycle can absorb. Technology market research company Informa valued the global automotive AI processor market at $5.2 billion in 2025 and expects it to reach $12.6 billion by 2030, a compound annual growth rate (CAGR) of 19.4%.

Each new AI-augmented workload places new demands on the silicon underneath. And those demands are changing far more quickly than the automotive sector has been used to moving. A vehicle program is specified years before start of production, and may stay on the road for decades. Yet the AI we know today is almost unrecognizable from the AI we knew 10 years ago.

When the “Attention Is All You Need” research paper was published by Google engineers in 2017, the AI we knew was fundamentally based on Convolutional Neural Networks (CNNs). Three years later, and in the wake of a global pandemic, everything had changed. The transformer model the paper described was so powerful that it rapidly replaced CNNs, and today almost everything we call ‘AI’ is based on that transformer model. Whatever comes next, the industry expects it to arrive just as quickly and unexpectedly.

This means that silicon decisions taken towards the software-defined vehicle (SDV) today must support at least two generations of AI that have not been invented yet.

Why RISC-V?

RISC-V Enables Pervasive AI in the Software-Defined Vehicle

How does RISC-V enable pervasive AI in the software-defined vehicle?

RISC-V enables pervasive AI by providing a single, open, and AI-native instruction set architecture (ISA) that scales from low-power microcontrollers to zonal controllers and central compute. Its modular architecture enables designers to tailor each processor to its workload, add AI extensions (such as vector or matrix multiply) or accelerators where needed, and retain software and toolchain portability across the vehicle. This reduces power, cost, complexity, and vendor dependency while supporting distributed intelligence at every level.

RISC-V’s modular, extensible instruction set architecture (ISA) gives automotive OEMs and Tier 1s the freedom to design and deploy AI-native, workload-specific silicon across the entire SDV, sized to the demands of particular AI workloads. As intelligence spreads to every corner of the vehicle, compute grows more heterogeneous, not less: AI workloads differ in kind, not merely in scale, and the vehicle has to serve all of them at once, reliably.

While proprietary ISAs offer a similar range, they do it with different instruction sets at different tiers. Only RISC-V enables heterogeneity to be baked-in at the chip level, using a single ISA that scales from high-performance central compute down to a microcontroller at the edge of the E/E architecture and spans application-class SoCs to deterministic, safety-certifiable MCUs.

Intelligence reaching from high-performance central compute down to a microcontroller at the edge of the E/E architecture demands a correspondingly heterogeneous range of workload-specific silicon, from application-class SoCs to deterministic, safety-certifiable MCUs. RISC-V enables OEMs to standardize what should be standard and differentiate what must be differentiated.

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Pervasive AI

Distributing Intelligence from Bumper to Bumper

What kinds of AI run in a software-defined vehicle?

AI in the vehicle spans a rapidly growing range of workloads. Real-time perception and control runs at the sensor and zonal tiers, where physical AI acts on the world with safety consequences. In the digital cockpit, agentic AI delivers personalization. These often serve the same use case, increasingly from the same mixed-criticality chip, via a hypervisor.

Today, two broad categories are emerging in automotive AI. Rather than two ends of a compute spectrum, many chips designed for SDVs need to be capable of both – often at the same time.

Physical AI brings intelligence closer to the sensors, actuators, and real-time control loops that govern how the vehicle behaves on the road. Whether serving a zonal controller / hub or a deterministic microcontroller at the edge, physical AI perceives the physical world and acts on it in real time. Its latency budget is measured in milliseconds and it may need to be guaranteed with deterministic timing and certifiable behavior.

Agentic AI draws on human-centric central compute between cockpit and cloud. It acts as an intermediary between a vehicle and its occupants, personalizing the digital cockpit and enriching the in-car or in-cabin experience through workloads such as conversational voice assistants, intelligent navigation, comfort and orchestration layers. Expectations here are being set by consumer electronics rather than by automotive precedent, and they are rising quickly.

While many agentic AI workloads will be non-safety-critical, often referred to as Quality Management (QM), the boundary is porous. Any feature that can act on the vehicle’s physical state carries a functional-safety dimension, and any agentic AI that monitors a driver – be that their physical interactions with the vehicle or simply drooping eyelids – must work closely with physical AI to ensure safe operation of the vehicle.

Consideration Agentic AI Physical AI
Primary role Interprets intent and acts on the cabin experience Perceives the physical world and acts on vehicle behavior
Typical location Central compute and the digital cockpit Perception and planning stacks, zonal hubs, edge microcontrollers
Timing character Responsive; latency is a quality-of-experience concern Bounded; latency is a safety concern
Tolerance for the cloud Often cloud-assisted, increasingly offline-capable Local inference by necessity
Compute character Large probabilistic models, vector and matrix heavy Mixed: probabilistic perception feeding deterministic control
Example use case Conversing with the driver in natural language when they ask to cool their seat Nudging the steering back over a crossed white line

The Industry Is Embracing the Middle

These capabilities often contribute to the same use case from different angles, increasingly coexisting on the same chip within a mixed-criticality architecture. The models themselves are merging; vision-language-action models integrate perception, natural-language reasoning, and vehicle control in a single policy. A model of this kind may simultaneously drive the most agentic and the most physical workload in an SDV.

Today, the first commercialized SoCs unifying digital cockpit and driver-assistance workloads on one die are shipping, and Tier 1 compute modules are now marketed as serving either domain from one scalable platform. The physical separation between “cockpit chip” and “ADAS chip” is being designed out.

It’s also important to recognize that, as explained above, the field of AI is moving incredibly quickly. As such, the categories of ‘physical AI’ and ‘agentic AI’ should be regarded as a useful simplification rather than industry standard taxonomy. Leading silicon vendors describe these categories as sequential waves rather than opposites, pair them as “embodied and agentic” intelligence delivered across cockpit and driver assistance, and in at least one case argue directly that physical AI is simply agentic AI at the edge.

However you describe it, the important takeaway is that pervasive AI does not mandate the same AI everywhere in the SDV, but a wide range of AI workloads to meet an ever-growing number of use cases. And it’s this that lies at the heart of the opportunity for OEMs and Tier 1s embracing RISC-V for automotive.

AI-Defined Vehicle

A New Paradigm: The AI-Defined Vehicle (AIDV)

What Is an AI-Defined Vehicle (AIDV)?

An AI-defined vehicle is a software-defined vehicle in which AI is architectural rather than optional: threaded through the compute topology from edge sensors to central compute, instead of bolted on as a feature. The AIDV does not replace the SDV. It names what pervasive AI adds to the original software-defined vision.

AI has already proven its value in central compute and the digital cockpit. Now, as workload-specific silicon makes heterogeneous, AI-native compute the norm throughout the vehicle, the next question is what happens when intelligence proliferates out from the center to touch every processor on board?

Chasing that question has produced a paradigm that the industry is beginning to refer to as the AI-defined vehicle (AIDV). This is less a replacement for the SDV than an acknowledgement of what pervasive AI adds to the original software-defined vision. In effect it is a declaration of intent: moving AI from a bolt-on feature to an architectural component threaded through the vehicle’s nervous system, from its traditional home in central compute out to the edge.

“SDV” took the better part of a decade to settle into common lexicon. “AIDV” seems to have progressed from a handful of silicon-vendor keynotes to trade-press explainers, analyst frameworks, and OEM product language within a year, and it dominated the automotive halls at CES 2026 and Auto China in Beijing.

But again, language is fluid. Look to those using the term ‘AIDV’ and you’ll see it applied to three distinct jobs: 1) a vehicle that adapts to its occupants, 2) an E/E architecture that allocates silicon and thermal budget to AI from the outset, and 3) a development process in which vehicle behavior is trained from fleet data rather than frozen at start of production.

Which definition prevails matters commercially, but matters far less to those designing silicon for pervasive AI. All three converge on the same requirement: more AI, at more locations within the vehicle, with headroom reserved for models that do not exist yet.

AI in Functional Safety

Bounded AI at the Safety-Critical Edge

Which standards govern AI for safety-critical vehicle workloads?

There are three key standards today. ISO 26262 covers functional safety from systematic and random faults. ISO 21448 covers safety of the intended functionality, where the system works as specified but the specification is insufficient. ISO/PAS 8800:2024 extends both to AI-specific concerns that neither addresses: model performance limitations, data quality, and the AI lifecycle.

A number of RISC-V members are probing where physical AI belongs in safety-critical microcontrollers. If AI is probabilistic by nature, what can it contribute to workloads that demand deterministic outcomes? Answering that means working through safety islands, control and judgment planes, and the boundaries of safety certifications such as ISO 26262.

At the vehicle’s edge sit the microcontrollers and safety islands responsible for deterministic real-time control, monitoring, and fallback. RISC-V privilege levels, memory protection, and deterministic execution support anomaly detection and predictive maintenance within a safety island, while certified control retains final authority over braking, steering, and power delivery.

This is physical AI at its most constrained: inference at the edge crosses into physical AI at the moment it can act on a motor, a brake, or a steering column, and that is precisely the moment that functional safety obligations attach. The same model running as a diagnostic that never actuates anything sits outside that boundary.

The currently agreed design discipline is to let AI contribute, without ever letting it become the single point of authority. AI informs and monitors through anomaly detection, plausibility checks, and predictive maintenance, while a deterministic mechanism retains final say. The prevailing architectural pattern keeps probabilistic AI outside the highest safety boundary and has a deterministic safety island validate its output before any physical action is taken. Agentic AI stays adjacent to certified control loops, not in charge of them.

Standards Have Caught Up With AI

The safety conversation around automotive AI is often oversimplified to ISO 26262. This is no longer the whole picture, and treating it as such understates how far automotive standards work, particularly in AI, has moved in recent years.

ISO 26262 addresses malfunctioning behavior. Something in the electrical or electronic system fails, systematically or randomly, and the system must detect it and fail safely. ISO 21448, ‘safety of the intended functionality’, addresses a different failure: nothing is broken, the system does exactly what it was specified to do, yet the design implementation itself turns out to be insufficiently robust in its operation. Perception systems fail ISO 21448 certification far more often than they fail ISO 26262.

Meanwhile, the newer ISO/PAS 8800:2024 standard covers what the others do not: specific malfunctions and lifecycle factors for AI and machine-learned models used in safety-related road vehicle elements. It addresses functional insufficiencies arising from model performance limitations, training data quality, and the AI development lifecycle.

Together with ISO/SAE 21434 for cybersecurity and UN R155/R156 for type approval, these form the framework any AI-enabled SDV, or AIDV, must be capable of meeting.

Understanding Certification with RISC-V

It’s important to understand that neither RISC-V nor RISC-V International offers certification for functional safety or cybersecurity. Consider the RISC-V ISA as a set of building blocks; it is up to the builder to construct something capable of meeting such certifications. RISC-V supplies the mechanisms; our members earn the certificates.

These certificates attach at three levels: IP assessed as a Safety Element out of Context, the chip, and the item. Processor IP is certified as a matter of routine, and several RISC-V vendors already hold those certificates at ASIL D. At item level, the deliverable is a safety case – it receives an independent assessment rather than an off-the-shelf certificate, which then belongs to the OEM.

It has long been recognized that applying automotive safety qualifications to open-source software or operating systems such as Linux and LLVM improves the resulting safety argument, because many independent parties review the same code. The same logic applies to the architecture itself. A safety case built on a publicly available specification can be examined directly by an OEM safety team or an independent assessor, rather than through a supplier’s disclosure agreement.

FAQ

Frequently Asked Questions

Pervasive AI means intelligence at every tier of the vehicle rather than in a few headline features. It covers experience-led AI in the digital cockpit, perception and planning in ADAS, and bounded AI inside safety microcontrollers at the edge, all running on silicon shaped to each workload.

An AI-defined vehicle is a software-defined vehicle in which AI is architectural rather than optional, threaded through the compute topology from edge sensors to central compute. AIDV does not replace SDV. It names what pervasive AI adds to the software-defined vision, and signals intent to design AI in from the outset.

No. The SDV describes a vehicle whose functions are defined and updated in software. The AIDV describes what happens when those functions become machine-learned rather than hand-coded. The AIDV is built on SDV foundations: centralized or zonal compute, over-the-air updates, and software portability across silicon generations.

Agentic AI sits between the vehicle and its occupants, personalizing the cockpit through conversational voice, navigation, and orchestration. Physical AI perceives the physical world and acts on vehicle behavior in real time, from perception stacks in central compute down to control loops at the edge, with safety consequences if it fails.

RISC-V is modular and extensible, so AI capability is added at the ISA level and reaches every class of chip. The ratified vector extension is mandatory in the RVA23 profile, matrix extensions are in development, and custom extensions let vendors tune silicon to a specific workload without breaking compatibility.

Three approaches are in progress. The Integrated Matrix Extension (IME) performs matrix arithmetic in the existing vector registers, was frozen for public review in mid-2026, and is targeted for ratification before year end. The Attached Matrix Extension (AME) adds a dedicated matrix register file. The Vector Matrix Extension (VME) was chartered in February 2026.

Yes, within bounds. AI can inform and monitor through anomaly detection, plausibility checks, and predictive maintenance while a deterministic mechanism retains final authority. RISC-V supplies the architectural mechanisms: privilege levels, memory protection, and predictable execution. The safety case belongs to the silicon implementation and the integrator.

No ISA is certified. The ISA is certifiable; implementations are certified. Andes, Nuclei, and SiFive all hold ISO 26262 certifications for RISC-V processor IP, with ASIL D coverage among them, and SiFive was the first IP supplier to achieve ISO/SAE 21434:2021 product certification. Certification responsibility remains with implementers and integrators.

Because a car is not a cloud. Physical AI governs braking, steering, and perception on millisecond timescales, where a round trip to a data center is neither fast enough nor reliable enough. Connectivity fails in tunnels and parking garages. Increasingly, cockpit AI is being specified to work offline too.

No. AI inference can run on scalar processing, on the vector extension, on matrix extensions, or on a dedicated accelerator, depending on the workload. Expressing AI operators through ratified ISA extensions keeps software portable across suppliers, where an accelerator reached by vendor-specific instructions ties that software to one roadmap.

Probabilistic AI produces outputs with a distribution of likely answers rather than one guaranteed result. Safety-critical automotive functions require deterministic, provable behavior. Reconciling the two means bounding where probabilistic components can influence outcomes, using safety islands and deterministic supervision so certified control retains final authority.

RVA23 is the ratified application-class profile mandating both the vector extension for AI workloads and the hypervisor extension for isolating mixed-criticality domains on shared silicon. RVB23 shares the same 64-bit base but makes both optional, trading guaranteed binary portability for smaller, lower-power silicon.

Because the RISC-V ISA is an industry open standard. OEMs and Tier 1s can source AI silicon from multiple vendors within a single architecture, reducing single-vendor lock-in. Because extensions are defined at the ISA level, an OEM can add architectural instructions for a specific workload without stepping outside the standard, or the portability of its software ecosystem.

TOPS measures peak arithmetic throughput, but it’s less useful in the software-defined vehicle (SDV) or AI-defined vehicle (AIDV). Automotive AI is usually limited by memory: single-stream inference waits on weights moving from memory to compute, not on arithmetic. Model architectures also change faster than vehicle programs ship, so headroom, memory bandwidth, and software portability matter more than a headline number.

No. A Safety Element out of Context is a real element: IP or software with failure modes, an FMEDA, and a safety manual of assumptions the integrator must verify. The ISA has none of those. It is the architectural contract an SEooC’s safety argument is written against. Members develop cores as SEooC; the specification itself is never one.

RISC-V Automotive Hub

RISC-V for Automotive

The open standard architecture for smarter and more scalable automotive compute.

Economic Control

Preserve cost competitiveness and roadmap ownership throughout decade-plus vehicle platform programs.

Supply Chain Resilience

Source equivalent implementations from multiple vendors across geographies, without depending on any one price list or roadmap.

Pervasive AI

Deploy intelligence throughout the vehicle, spanning voice assistants in the digital cockpit, ADAS and automated driving, and physical AI in microcontrollers.

Workload-Specific Silicon

Standardize on a single architecture for every workload, with a software stack spanning every purpose-built chip in the vehicle.

Safety and Security

Design certifiable silicon on open, transparent foundations to meet exacting functional safety and cybersecurity standards.