‘V Questions with…’ seeks to uncover the backstory to a RISC-V member’s work in five questions. Today I’m with P R ‘Siva’ Sivakumar, founder and CEO of Bangalore’s leading institute for aspiring semiconductor engineers, Maven Silicon.
India is building its own semiconductor fabs, assembly and test plants and fabless design startups at pace, with government funding behind it through the Indian Semiconductor Mission.
But, as I found out in last week’s V Questions with… Openchip, spurring spurring silicon sovereignty takes more than money and acumen. As Maven’s P R ‘Siva’ Sivakumar puts it: “Design talent is just as important as funding for the long-term growth of any chipmaker.”
Siva founded Maven Silicon as a VLSI (Very Large Scale Integration) finishing school, running career-oriented design verification courses for new graduates. His background spans 28 years in electrical engineering, academia and semiconductors, including recent work as a verification consultant for Synopsys, Cadence and Siemens EDA.
Every VLSI and embedded engineer who comes through the company begins by learning the RISC-V ISA before anything else. It’s the reference point for everything that follows; Siva calls it the “alphabet of the semiconductor systems language.”
The reasoning extends beyond the RISC-V ecosystem. An engineer who learns systems thinking through an open ISA can go on to understand any processor they come across, and Siva argues that this matters more than ever now that AI tools are writing a growing share of the RTL and the testbenches.
To learn more about Maven’s past, present and future, I asked Siva about RISC-V in Five questions…
1Maven chose to collaborate with RISC-V International as a Global RISC-V Training Partner. Why?
Siva:We wanted to build our domain expertise in processors and CPU ISAs because understanding one good processor, especially a Reduced Instruction Set Computer like RISC-V, is essential for young engineers who want to build a long-term career in the VLSI and Embedded Systems design field.
RISC-V, as an open ISA, was a golden opportunity for us to explore the complete ISA and understand everything related to systems – Bare-metal embedded systems, OS-managed SoCs, and Hypervisor-managed server chips.
RISC-V International, as a non-profit organization, supports all kinds of organizations – chipmakers, the EDA industry, and academia – with equal importance. Regular access to its well-updated ISA specifications, open designs/examples/software and toolchains, newsletters, and RISC-V Summit technical session videos on YouTube are always good references. It truly reflects the culture of openness.
Supporting the next-generation engineers with the vision of democratizing chip design through imparting open RISC-V ISA is a driving force for our long-term journey as a Semicon-COE. We are a proud RISC-V Global Training Partner.
2What are the biggest gaps today between academia and industry in semiconductors? How do you address those gaps?
Siva:In this AI era, engineers need systems thinking beyond doing their jobs as skilled coders. Engineers’ careers have been highly driven by the evolution of programming languages, design methodologies, and EDA/toolchains.
In VLSI, we use HDLs such as Verilog HDL and VHDL for RTL design, SystemVerilog and Universal Verification Methodology for design verification, and various methodologies and EDA tools for Design for Testing, Analog Design, and Physical Design.
Now, with AI tools such as copilots and Agentic AI, programming work such as RTL/testbench coding, Python, C, TCL/TK programming, and EDA flow implementation could be highly automated. But it needs engineers’ due diligence and involvement in implementing the design flow and producing bug-free silicon without expensive respins.
Every engineer here starts by learning how we build hardware systems, which gives them the big picture: the complete design cycle, the software stack, and post-silicon validation.
But beyond understanding the big picture, engineers need to be specialized in a specific domain – VLSI: Design, DV, DFT, AMS, PD, etc., and ESD: Firmware, Device Drivers, Bare-metal/RTOS, OS, Applications, etc. Depending on their preference, we train them extensively in a specific domain and make them project-ready.
For example, a DV engineer who uses firmware C test cases to configure the SoC before running any UVM testcase will never understand this verification process without knowing CPUs and systems. If AI tools can generate such SoC testcases, then we need DV engineers as domain experts who can collaborate with designers and architects at the verification planning level to verify the systems. Can they speak the system’s language, beyond writing test cases and using EDA tools?
3How are you planning to build a strong RISC-V engineering community spanning IC design, embedded firmware, and operating systems?
Siva:We are a community-driven organization. As a self-funded company, it is the only powerful way we can continue our long-term journey meaningfully, forever, without losing our relevance in the global semiconductor ecosystem.
At present, we are empowered by our alumni community. The top 10% of our alumni, more than 500 engineers, are today working as tech leads and project managers in the global semiconductor industry. They are part of our advisory board, defining new curricula and updating our existing curricula and pedagogy.
Not everyone will be working on RISC-V CPUs/SoCs, but RISC-V expertise enables them to understand any other proprietary CPU.
Now, with this success, we have introduced our embedded courses with RISC-V ISA as a trailblazer in the embedded software ecosystem. It helps us build a strong VLSI and Embedded engineers community with RISC-V expertise.
India is ambitiously gearing up with semiconductor fabs, ATMPs, OSATs, and VLSI fabless design startups, with good government funding support under the Indian Semiconductor Mission scheme, to build a strong semiconductor ecosystem. Various organizations such as C-DAC and IIT Madras have designed their own RISC-V processors and created a good RISC-V IP design ecosystem for fabless design startups in India. It inspires many Indian design startups to use RISC-V ISA for their IPs and SoCs.
I am also in the process of building my other venture, Aceic Design Technologies, into an automotive chipmaker. We want to collaborate with Tier-1 automotive suppliers and OEMs to design RISC-V SoCs, especially within India, on their journey from domain to zonal architectures in the software-defined vehicle (SDV).Having built good RISC-V domain expertise and a talent ecosystem at Maven Silicon, I have immense confidence in hiring talented VLSI and Embedded engineers into roles at Aceic.
4How do you envision the RISC-V talent community evolving over the next 5 years?
Siva:The Indian semiconductor industry is dominated and driven primarily by design and support services businesses. In VLSI, most of them are DV and PD-skilled engineers who work for global chipmakers. They may be highly skilled in their domain, but their exposure to the complete product development cycle – specification to tapeout to validation – is limited.
Job roles and responsibilities will change/evolve, and some jobs will merge/disappear as chip design embraces AI-powered EDA. In order to address their skill gaps and upskill, we now offer various RISC-V-powered Executive PG degree and certification courses under premier institutes such as iHUB – IIT Roorkee, IIT Madras – Pravartak, and NIELIT for working professionals, beyond our B2B-corporate bootcamp courses. It helps us prepare them for their long-term careers in the AI-driven semiconductor industry. With this in mind, we will soon be offering more online executive courses through the global SEMI University online platform.
5What would you say are the key technical skills engineers must develop to contribute meaningfully to the RISC-V ecosystem in 2026?
Siva:For me, the journey is from RV32EC bare-metal programming to RVB23 for embedded embedded application processors, then RV64GC and RVA23 for high-performance application processors, Linux, and finally virtualization and hypervisors.
Profiles give our engineers a much greater perspective on how the architecture scales from resource-constrained embedded systems to high-performance processors.
A good embedded engineer should know what happens from reset to running firmware – startup code, linker scripts, stack initialization, BSP (Board Support Package) development, memory maps, memory-mapped I/O, bootloaders and peripheral drivers. Interrupts and traps are another area that needs much deeper attention. Engineers should understand exceptions, interrupt handling, trap delegation, CSRs, context saving, and both direct and vectored trap handling, along with the role of CLINT (Core-local Interrupt Controller), PLIC (Platform-Level Interrupt Controller) and the newer RISC-V Advanced Interrupt Architecture (AIA). These become fundamental when moving from simple firmware to RTOS and OS-based systems.
On the SoC side, engineers must also learn an on-chip bus interconnect such as AMBA – AXI, AHB, and APB, and external interface protocols such as SPI, UART, I2C, GPIO and USB.
For embedded programming, strong C and assembly skills, along with RTOS concepts and interfaces such as SPI, UART, I2C, GPIO, timers, DMA and watchdogs, are essential. Engineers should be able to look at a datasheet or reference manual, understand the registers and write the driver themselves.
Then I would move to the OS layer. Studying a simple RISC-V OS such as xv6 is a very good way to understand virtual memory, page tables, system calls, processes, traps and device drivers. From there, engineers should learn how to build and customise Linux for RISC-V using Yocto or Buildroot, including kernel configuration, device trees, root filesystems, drivers and applications for different RVA23-based SoCs.
But the one layer that can really differentiate engineers in the coming years is virtualization. Understanding the RISC-V Hypervisor architecture and eventually being able to build a Type-1 hypervisor for a RISC-V application processor brings together CPU architecture, memory management, interrupts, isolation, device virtualization and operating-system knowledge. It’s vital for industry workloads such as within automotive functional safety.
Once an engineer can move across these layers, they stop being just a firmware programmer and start developing the system-level thinking needed to become a RISC-V systems engineer or architect. I’m pleased to say that Maven Silicon has already led many engineers through this journey.
India’s silicon sovereignty story is a regular feature in my weekly LinkedIn newsletter, and it’s companies like Maven that the country relies upon to deliver the talent to turn vision into reality.
Sovereignty needs engineers who understand the full stack, from bare metal to the application layer that sits atop an upstream Linux OS. Since 2010, more than 6,000 chip designers have passed through Maven’s doors, and they’re now working across Indian and global chipmakers – from startups to multinationals.
A testament to both what an open standard ISA makes possible, and Siva’s decision to build an entire curriculum and training business around it.
The Semiconductor Ecosystem Needs Talent. Maven Is Building It.
Discover Maven Silicon’s role in developing industry-ready VLSI and Embedded Systems talent in India and beyond, and how you can get involved.
