Andes unveiled new A25MP and AX25MP versions of its Linux-friendly A25 CPU cores claimed to be the first RISC-V cores with a “comprehensive” DSP. The 1GHz-plus cores provide cache coherency and support for SMP and up to quad-core designs.
At the RISC-V Workshop Taiwan, Andes Technology announced a second generation of its Linux-friendly, RISC-V ISA compatible A25 (32-bit) and AX25 (64-bit) CPU cores. The 32-bit, 28nm fabricated A25MP and 64-bit AX25MP are the first commercial RISC-V cores with comprehensive DSP instruction extensions, says Andes. Unlike the earlier A25 generation (see farther below), they are also the first to offer cache coherency for supporting multi-core and multi-processor support. The initial products, however, will be single-core designs.
To read more, please visit: http://linuxgizmos.com/multi-core-linux-ready-risc-v-cores-feature-dsp/.
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