MIPS recently announced that the company is pivoting to RISC-V and introduced its first MIPS products based on RISC-V, targeting automotive, 5G and wireless networking, data center and storage, and high-performance embedded applications. This is huge news for the industry as MIPS is one of the pioneers of RISC architecture. RISC-V International CEO Calista Redmond chatted with MIPS CEO Desi Banatao to get some insight into MIPS’ RISC-V strategy, the company’s plans to contribute to the RISC-V ecosystem, and more. Check out the full conversation:
The transcript is also available below:
Calista: Desi, it’s great to see you again. I feel like we are having more one on ones than I have with many of my team members. Welcome to team RISC-V. It has been so fantastic to see all the momentum you guys are getting. Thanks for doing this with us.
Desi: Thanks for welcoming us. We were a little nervous at the start of this, announcing such a major shift for a technology that’s been followed by so many people in the industry for so long and how big of a change it is. But it’s been refreshing to be welcomed by you guys with such open arms, but also people being receptive to this change.
Calista: Fantastic. Well listen, MIPS has been a pioneer in RISC architectures for so long, for decades. What made you consider shifting over to RISC-V in particular?
Desi: When we were looking at this potential pivot, the word “open” gets thrown around a lot with RISC-V. For us, we thought of it more as being modern. The openness does allow for it to not be burdened by legacies or backward compatibilities that proprietary ISAs can be, and MIPS has been in the past. And then, the timing aspect of it has also been pretty important.
The idea of MIPS using RISC-V is not new, it’s not something that I came up with or anything like that. There have been teams that have been talking about this all the way back to when I became involved with the company back in 2017. But the timing now is perfect for MIPS and also for RISC-V in that a lot of the maturity and the new kinds of technologies like multi-threading and hypervisors that are all becoming part of the RISC-V standard now are things that MIPS has been doing for a long time. It’s just a good time for us to be able to intersect into what RISC-V is doing with things that we’ve done in the past.
And, lastly, MIPS has been through a lot in the last decade, changing ownership multiple times, most recently a bankruptcy, which is pretty rare for a technology company. It’s been through a lot. We’re trying to take a little bit of a more pragmatic approach to it. And, at the end of the day, the market wants RISC-V. No matter how bad people are nostalgic about MIPS and love MIPS as an ISA, it’s not something that the market is demanding today. We’re just trying to be pragmatic business people and do what the market says, which today is switching over to the RISC-V platform.
Calista: I love it. At the end of the day, the market wants RISC-V. I’m going to go put that on a t-shirt.
Maybe I’ll put on the front of it “at the beginning of the day, the market wants RISC-V” and then on the back of the t-shirt “and at the end of the day, the market wants RISC-V.” I might have to open source that one right here on this call.
Desi: Yes, totally.
Calista: You said a couple of things in why, first, it was a modern take on RISC architecture. And so that speaks a bit to some of the design flexibility that we have, while we don’t have a lot of backward compatibility topics to tackle, it’s both not brand new. It is RISC after all. But it’s also takes a more modular approach. How much of a factor is that modular design flexibility approach in, as a factor of your choice or where do you see that going? Tell me a little bit more about design flexibility, modern approach to RISC, things like that.
Desi: Sure. And MIPS actually had something similar in their ISA but they called it, Application Specific Extensions, but I think ultimately the idea is the same, which is, despite the fact that we’re trying to make general purpose processors, we need to provide some amount of flexibility for the customers to do performance improvements, have features that enhance their applications. And that was the idea around the MIPS Application Specific Extensions. But that that also lends well to the UDI concepts that’s in the RISC-V. And for us that’s really important. Again, it’s something that was built in the MIPS ISA. It allows us to bring differentiable technologies to the ISA – that again, those things that MIPS has worked on – but also like you said, as the world changes and it’s changing fast, you’re allowed to adapt and come up with new concepts and apply them without having to go through some massive standardization.
Calista: MIPS has announced some incredible new designs on RISC-V, highly scalable general purpose multi-processors, that sounds like the higher end of the market. And you’re coming out with it this year, this is incredible. Where do you see MIPS taking these new general purpose microprocessors and what can you tell us about that?
Desi: The key to what we’re trying to do from a solutions perspective is really apply this idea of high scalability and that means not just clusters and cores, but we’re also trying to do clusters and clusters. And so, where does that play well? It’s definitely going be the high end of the market, right? Automotive, data center, networking and communications, and all those markets. So for us, it’s really trying to take something that MIPS has done well in the past, bring it into RISC-V, and then use that to enable customers and those segments of the market that need it.
Calista: Data centers, automotive, networking. Tell me a little bit more about some of the high-end wireless stuff, the network or telecom, 5G, and CBRS. Where do you see RISC-V fitting into that space?
Desi: Specific to applications like 5G, this is the history of what MIPS has done in that space, the small code, compact instruction sets. On the MIPS side, we have something called nanoMIPS, that in the 5G world, the customers that we had in that space used significantly as they transitioned to 5G. And when we look at RISC-V, things like the C extension are going be pretty important. I’m not exactly sure if the C extension was created specifically for applications like 5G, but we definitely see things like that that are in the standard today that are going to be really important as we try to take our solutions into those applications.
Now, if you get into the networking side of it and the data center side of it, this idea of heterogeneous compute has really come to the forefront. The demands there have really been driven by the hyper-scalers who are enabling all of these different cloud compute companies and there’s a lot of different types of applications, workloads, and what’s unique that’s been happening lately is, as opposed to having three or four silicon vendors face this market, people are bringing teams in-house, which is creating just a massive diversity of solutions. And for us, this is both an opportunity, but also a challenge for RISC-V. How do you build a software ecosystem that’s going to support many, many customers with many, many diverse solutions?
Desi: And so again, for us, it’s what drawn us to RISC-V, I don’t think we could do that on our own, with our own ISA to be able to support something like that. Similar to 5G with things like the C extension, we have to see how the software ecosystem develops, especially around heterogeneous compute architectures that we see, really playing a huge part on where we think the data center is going be at.
Calista: Desi, let’s face it, the game has changed. It used to be you could strategically put all your eggs in one proprietary architecture basket, and really those days are over. When you start to look at heterogeneous compute environments, when you start to think about a multiplicity of architecture options, where good portability and ecosystems that respond well to that, and that can run well, that run optimized on any of those selected architectures, that’s essential. Those are now going to become table stakes for getting a competitive edge regardless of which stakeholder position you have in that community, because we all have a piece to play in that. And I fundamentally believe that taking an open and collaborative approach is starting to see significant traction, just as we saw in grabbing on to global standards or grabbing on to open source software like Linux, those become the base building blocks that we all need to sort of hook into for that long-term future. And so you’re spot on that being part of a community and an open community that collaborates around that is going to be a strategic bet that more and more begin to make. Let’s talk about MIPS some more, where you’re going as a company, where do you see your growth and future with RISC-V?
Desi: Although MIPS has played in a lot of different levels of the CPU market, all the way down to micro-controller space, I definitely feel like where we are today with RISC-V is we really do want to concentrate on the high-end market. And there might be opportunities where we back track and look at opportunities in that microcontroller space, but where we’re intersecting it today and where we look at our roadmaps or our development plans, everything’s pushing us in this direction, of obviously, employing a lot of the technologies that MIPS has historically done: multi-threading, scalability with clusters, things like that. But also, just pushing single-thread performance. And elevating that, what we’re trying to do with this first product that we’re debuting – called the eVocore P8700 – is really setting the bar for single thread performance in the RISC-V space.
It’s something that our customers are asking. This product is being designed specifically for automotive, and as automotive controls and things have gotten more complex, algorithms, all the different types of sensors people are wanting, just having a really fast processor is needed. At least that’s where we see how we’re going to use RISC-V to address what our customers are asking for.
Calista: Automotive is just an exploding realm of opportunity. I started to look around the infotainment and drivetrain and everything else that is really just one large traveling computer that luckily, has all the features for entertainment and safety that one could imagine, but it is incredible the number of growing opportunities there with autonomous and assisted driving and other features and capabilities being added constantly. Any more hints on what’s coming, more broadly or down the line, beyond automotive and data centers? You’ve talked a little bit about network and 5G, any other forums that you see as ripe for RISC-V or MIPS specifically?
Desi: We’re really concentrated on the applications and the customers that we’re engaged with today, but we need to think about roadmap and the future. We really do believe in this idea of heterogeneous compute and RISC-V does too with things like vector extensions and bringing in other AI or ML type of concepts into the standard. We want to help push and support that, and that’s going to be something that we evolve into our roadmap as we progress.
Calista: Lending a hand, or helping out with sort of the greater community is something that is sometimes new for the hardware world, is something that contributor aspect, or taking a leadership role or contributing some of your designs, or just thought leadership within many of our technical communities. That’s something that we’ve been seeing some of the MIPS teams step up and contribute to. How is that part of your strategic future, engaging in communities like RISC-V?
Desi: We think it’s important. Again, there’s a lot of heritage and knowledge that’s in MIPS today. And we’ve talked about this as, these are two ISAs that were born from the same place and could be related as cousins in some way, shape, or form. We do need to be able to keep our differentiable technologies and be able to differentiate ourselves in the market, but we want to be able to bring a lot of the RISC heritage that’s been built in MIPS over the past 35 years and lend it to RISC-V in a way that everybody can benefit from. And that might be the solutions in the products that we put forward, that people can see how we implement certain ideas. But that’s going to be engaging in whatever groups or committees that are available, that we can help affect and in an IEEE type way, where we might have ideas and to help shape the standard in what we think would be a positive way.
Calista: Oh, and we are grateful for it, Desi. Getting to work shoulder to shoulder with the great talent and architects and engineers from your team, as well as fostering that sense of collaboration in the community, is huge. It accelerates all of us. Everyone gets a running start that way, and there’s still so much room to go off and be wildly commercially successful beyond that. We’re really grateful for that. Any closing, thoughts, words, things that you’d like to share?
Desi: It’s been quite an adventure for this last week, debuting MIPS’ plans in the RISC-V space. And thank you again for welcoming us with such open arms, it’s been refreshing. We look forward to great things and a future for MIPS plus RISC-V in a way that the industry will benefit.
Calista: Fantastic. Well, thanks so much. And look forward to chatting again with you next.
Desi: Thanks Calista.