There are plenty of ways to contribute to the RISC-V community. From organizing community events to writing, speaking, building technical communities, and growing RISC-V in new regions, our advocates are…
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And the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up the RISC-V software ecosystem. Grant…
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Verification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances rigour and speed.
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The 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to the ecosystem, this is your…
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We explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
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Author: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we approach designing various electronic products…
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Introduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may overlook corner case and simulation-resistant…
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by Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly every five to six months, but…
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By Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over 4,000 attendees. The main venue…
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