A new technical paper titled “Static Hardware Partitioning on RISC-V — Shortcomings, Limitations, and Prospects” was published by researchers at Technical University of Applied Sciences (Regensburg, Germany) and Siemens AG (Corporate Research).
Abstract
“On embedded processors that are increasingly equipped with multiple CPU cores, static hardware partitioning is an established means of consolidating and isolating workloads onto single chips. This architectural pattern is suitable for mixed-criticality workloads that need to satisfy both, real-time and safety requirements, given suitable hardware properties.
