Stay Connected With RISC-V
We send occasional news about RISC-V technical progress, news, and events.
They are the experts in the community and work together with RISC-V to help drive our global momentum and adoption of RISC-V technologies.
Successful ambassadors include engineers, developers, bloggers, influencers, evangelists who are already engaged with RISC-V in some way, including contributing to work groups, online groups, community events, training, workshops, and more.
The RISC-V Ambassador Program exists to empower community members with tools and resources needed to:
Requirements for a RISC-V Ambassador:
We review applications each quarter, but can only accept a few new RISC-V Ambassadors from the pool of highly-qualified individuals.
We are focused on creating a group of Ambassadors that meet all our requirements and represent our community and geographical diversity.
Once you formally apply you are part of the pool of applicants that get reviewed on a quarterly basis.
We will only follow up if your application is accepted.
Fr. C Rodrigues Institute of Technology
The potential of RISC-V is immense and has fascinated me to work more in this area. I started reading about the subject and have written review articles and LinkedIn articles on ‘SHAKTI-F processor’ and ‘Why RISC-V over several popular ISAs’. I published them through my LinkedIn account with many engagements from the community. I even encouraged students from my college to be part of RISC-V. In India, Bangalore being hub for semiconductor industry, I have encouraged few professionals to be part of RISC-V and contribute. After attending International Conference on Supercomputing 2020, RISC-V (open ISA) is leading the path of SW/HW ecosystem in the world. Being active member with RISC-V, I have also published a blog ‘RISC-V Global Forum: Initiative. Innovate. Impact.’ on RISC-V website.
Senior Researcher, AIST
Akira Tsukamoto works at National Institute of Advanced Industrial Science and Technology (AIST). His main focusing area is software engineering on network, operating system and system security who enthusiastic on any kind of technical development and have worked on products based on Cell/B.E. and ARM. Received M.S in Computer Science from Columbia University in the City of New York.
ASIC Design Engineer, Fraunhofer
Alexander is responsible for the Mixed-Signal ASIC design group at Fraunhofer IMS, a microelectronics research institute located in Duisburg/Germany, which is part of the Fraunhofer society. Alexander had been searching for a license-free computing core suitable for both research work and commercial ASIC development and started the development of RISC-V based systems at Fraunhofer IMS in 2017.
Marketing Director, Mentor
Regular contributor to MWG; Mentor participates in Debug/Trace TWG, organised Bristol and Cambridge meet-ups
Sr. Cloud Architect, Red Hat
I’ve been contributing with the port and test of the Golang language for about an year until it’s release on version 1.14 scheduled for
feb/2020. I’ve also ported many projects and contributed with 30+ pull requests for cloud-native applications like Docker, Kubernetes,
Prometheus, Etcd and many more. The ported projects are tracked on https://github.com/carlosedp/riscv-bringup with instructions on how to build from source for many of them.
Participating actively in the community on Linux tests for the Kernel ecosystem (Kernel, OpenSBI, U-Boot) and creating guides on how to have Linux on SiFive Unleashed board (https://github.com/carlosedp/riscv-bringup/tree/master/unleashed) and Qemu emulator (https://github.com/carlosedp/riscv-bringup/tree/master/Qemu).
Recently have been testing and working together with the community the Linux support on Kendryte K210, another Linux capable board.
Business Consultant, Micro Magic, Inc.
Dr. Huang is an accomplished entrepreneur and philanthropist with thirty-eight years of experience in high-tech start-up, Initial Public Offering (IPO), merger & acquisition (M&A), and executive management of electronic, consumer, and charity business. Dr. Huang is currently representing Micro Magic Inc. for its multi-Billion IP / M&A business. Dr. Huang has MS and BS degree in Electrical & Computer Engineering, Doctorate degree in Acupuncture & Oriental Medicine, and CSS of Administration & Management from Harvard University. Dr. Huang has six USPTO patents granted in hardware / software / free-cancer-drug, with numerous papers published in journals and magazines, and an invited speaker at various Conferences, Newspaper and TV Programs in both USA and abroad.
Fascinated by embedded systems and the Linux kernel. Advocate for Open Source Hardware and Free Software.
Sales Manager, Andes Technology
Last year I have joined the RISC-V Workshop in March in Taiwan Hsinchu, later I went on Roadshow in Europe (on behalf of Andes Technology) to speak about RISC-V and why it is the best ISA in Munich, Berlin, Tallinn, Paris as well as London. I went to Korea and spoke at the IP-SoC Design conference for Andes, as well as with Students of the Computer Science class. Later on I went to Japan and spoke on the KUMICO RISC-V meetup first in Tokyo and later in Osaka. This year I have decided to start a meetup in my hometone Munich and could convince my employer to sponsor snacks (meetup is paid by me) and I plan to setup one more meetup (surprise) in a few months.
I also excessively work on Twitter and Linkedin to keep RISC-V news flowing to all interested (mainly English, sometimes german).
RTL design engineer, Syntacore
I work as an RTL design engineer at Syntacore. As an engineer I participate in the development of a new core based on RISC-V ISA.
I’m also a Ph.D student at National Research University of Electronic Technology (MIET).
Additionally, I assist my colleagues with a teaching of computer architecture course where as a part of lab assignments, students design a RISC-V based processor using the Verilog HDL.
In my free time, I write my technical blog on Twitter and Telegram about computer architecture and RISC-V ecosystem in Russian.
Scientific interests: floating point computing [IEEE-754, Posit], memory hierarchy.
Senior Digital Design Engineer, Qamcom
Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations. Notable work include the FuseSoc IP core package manager; SERV, the award-winning RISC-V CPU and ipyxact, and SweRVolf, a reference platform for the SweRV CPU family. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike.
Senior Software Engineer, Red Hat
Since Dec 2017, I got a chance to make a presentation for “Fedora on RISC-V”. Then I try to follow the latest development status, and make the some presentations in [over a dozen conferences, see “Fu Wei” sheet]. I also try to help some RISC-V companise to understand Fedora/RHEL/CentOS, understand Opensource ecosystem. I have helped to build Fedora on RISC-V desktop Demo, and test UEFI, Fedora image when I prepared my presentation. I am trying my best to help on RISC-V software ecosystem, building connection with/between RISC-V companies and people. Hope someday we can have a software organization for RISC-V to promote the RISC-V ecosystem for IoT/Enterprise/Edge. I always think RISC-V ISA is the most meaningful work for me and my career. it’s my honor to be a RISC-V Ambassador, and go on working on it.
Co-founder & Project Director, PLCT Lab, ISCAS
Wei Wu is the co-founder and project director of the PLCT Lab. Under his leadership, the PLCT Lab is contributing to RISC-V ecosystem, especially in GNU Toolchain, LLVM, V8, QEMU and AOSP. He is the chairman of the OSDT working group, which is an active community focusing on open source developer tools and projects. He is passionate about pushing the boundary of the RISC-V ecosystem.
Student, Usman Institute of Technology
Zeeshan Rafique is a final year student of Computer System Engineering at Usman Institute of Technology, Karachi, Pakistan. For the past one and a half years, he has been working on RISC-V at Micro-Electronics Research Laboratory (community member of RISC-V ). At present, he is learning RISC-V deep and along with that, schooling computer architecture course to his junior enthusiasts too. Through teaching, he aims to convey his knowledge to others. Under his guidance, two batches of 10 students each, from computer science and computer engineering designed their cores and IDEs to automate the process of verification (https://github.com/merledu). Besides, he has attended two webinars on RISC-V as a guest speaker and currently, is writing a book for RISC-V beginners. It will help them to get started with basic gates and reach till 5-stage pipelined core along with SDK and FPGA flow. Furthermore, he is working on GDS and SoC designing to model his RV32IMC core. He is willing to complete the design before December to avail of the opportunity of the SkyWater-130nm shuttle program for fabrication. After tape-out, he plans to write a series of articles on RISC-V basics and advances. This all includes in his Final Year Project. In terms of co-curricular activities, he is an active member of societies (IEEE, ACM, DICE) in his university and a lead organizer of Karachi RISC-V Group.
We send occasional news about RISC-V technical progress, news, and events.