RISC-V Design Contest Calls On Embedded Designers To Push The Limits Of Innovation

RISC-V SoftCPU Contest, sponsored by Google, Antmicro and Microchip, encourages designers to tinker with FPGA solutions based on the free and open RISC-V ISA

Berkeley, Calif. – Oct. 8, 2018 – The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the call for submissions for the RISC-V SoftCPU Contest. The aim of the contest is to further promote the use of the vendor-independent, modular and reusable RISC-V ISA in FPGA applications, and push the limits of state-of-the-art design by encouraging designers to create innovative FPGA soft CPU implementations with the RISC-V ISA. The contest is sponsored by Google, Antmicro and Microchip Technology, through its Microsemi subsidiary, which are Founding Platinum members of the RISC-V Foundation. “As the RISC-V ecosystem has grown, we’ve already seen a wide variety of cutting-edge RISC-V designs in FPGAs as companies and designers take advantage of the free and open model of RISC-V and the flexibility, scalability and extensibility advantages the ISA offers,” said Rick O’Connor, executive director of the non-profit RISC-V Foundation. “This contest is a great opportunity for designers around the world to experiment with creating ultra-small and high-performance FPGA soft CPU implementations with the RISC-V ISA.” The contest targets two FPGA platforms from RISC-V Foundation members Microsemi and Lattice Semiconductor. Participants have the option of using the larger 25K LUT Microsemi IGLOO™2 or SmartFusion™2, or the 5K LUT Lattice iCE40 UltraPlus™. The contest challenges designers to build extremely small, or extremely powerful, softcore RISC-V implementations, with additional points awarded for novel approaches to the implementation itself. The entries will be RV32I-compliant soft CPUs. The core can support other standard RISC-V extensions if the designer decides to do so. There are four categories the entries will compete in:

• Smallest Microsemi SmartFusion®2 or IGLOO®2 implementation
• Smallest Lattice iCE40 UltraPlus™ implementation
• Highest-performance Microsemi SmartFusion®2 or IGLOO®2 implementation
• Highest-performance Lattice iCE40 UltraPlus™ implementation

Microsemi will provide 25 free Future Electronics Creative IGLOO2 boards and 25 free Creative SmartFusion2 boards (free shipping worldwide) to contest participants on a first come, first served basis. The company is also providing kits based on the 300K LUT PolarFire FPGA to second and third place prize winners, giving them the opportunity to implement their RISC-V designs in a much larger device. Interested participants can write to softcpu-contest@riscv.org with their name, surname, address, phone number and GitHub account name to sign up for a board (maximum one per person) and by doing so, commit to submitting an entry to the contest [Update: As of Oct. 15, all free boards have been claimed]. If the number of Microsemi-related entries exceeds 50, additional SmartFusion2 boards can be purchased from Future Electronics for $99.95. The judges will evaluate the nominations across each category and then select the top three winners overall. The prizes that will be awarded are:

• First place prize: $6,000 USD
• Second place prize: $3,000 USD + Splash Kit+ iCE40 UltraPlus MDP
• Third place prize: $1,000 USD + PolarFire Evaluation Kit+ iCE40 UltraPlus Breakout Board

The deadline for entries is Nov. 26, 2018 at 11:59 p.m. PST. To submit, contest participants need to email softcpu-contest@riscv.org with links to their relevant GitHub repositories. To read more about the contest details and rules, please visit: https://riscv.org/2018contest. The contest results will be announced at the first annual RISC-V Summit taking place in Santa Clara, Calif. from Dec. 3-6, 2018. To learn more about the RISC-V Summit and register, please visit: https://tmt.knect365.com/risc-v-summit/. About RISC-V Foundation RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. Media Contacts: Allison DeLeo Racepoint Global for RISC-V Foundation Phone: +1 (415) 694-6700 risc-v@racepointglobal.com    ]]>