RISC-V EMEA Roadshow Spotlight: Imperas

The RISC-V Foundation, in collaboration with the Linux Foundation, is hosting free, half-day “Getting Started with RISC-V” events in Tel Aviv, Munich, Berlin, Tallinn, Paris and London from Sept. 16-26. RISC-V Foundation members will give presentations and live demonstrations showcasing innovation RISC-V solutions and implementations. Register today to save your spot! Imperas is one of the featured RISC-V Foundation members in the EMEA roadshow, presenting the session, “Verification and Customization of RISC-V Cores and SoCs.” Imperas provides methodologies, technologies and products to enable the efficient and effective development, debug and test of software for embedded systems. Imperas virtual platform based products use models built with the Open Virtual Platforms (OVP) APIs, and support over 160 different processor cores, including RISC-V cores. Read on to learn more about the company and what it will be showcasing at the events. What applications or problems does your company’s technology solve for engineers?

• Imperas supports the debug and analysis of complex multi-core heterogeneous designs with full programmer view models and debug/analysis tools.
• Users can develop and test RISC-V extensions with profile and analysis tools to fine tune applications.
• Boot full operating systems and applications (e.g. SiFive FU540 model gets to linux prompt in under 7 seconds on a standard PC host machine).
• Start early software development before hardware prototypes are available.
• Verification of RISC-V Cores based on flow using Google RISC-V Instruction Stream Generator, Metrics cloud based tools with comparison to Imperas RISC-V reference model.

What does your company do regarding RISC-V? 

• We are involved in several activities within the RISC-V Foundation:
  • Supporting the working group on compliance and have donated the free reference simulator riscvOVPsim (details in the link below)
  • Working with the new extensions for Vectors and Bit Manipulation (see press release in the link below)

• Imperas is a founding member of the OpenHW group and a contributing member to the Chips Alliance verification working group.
• For customers, we are working with developers of new RISC-V cores as well as designers using off the shelf RISC-V IP cores from the ecosystem for complex SoCs.

 What will attendees learn from your presentation?

• RISC-V offers designers the flexibility and possibilities to implement, extend and adapt a processor for a target application. Using Imperas virtual platforms and models for analysis of extensions that can be profiled under full OS and application workloads
• Key steps in the Verification of a RISC-V processor based on the open source Instruction Steam Generator developed by Google

• Reference platforms based on cores from Andes, SiFive and others that can be used for OS porting, driver and early software development

General info on RISC-V support from Imperas at this link: http://www.imperas.com/imperas-riscv-solutions More detailed information on riscvOVPsim at this link: http://www.imperas.com/riscvovpsim-free-imperas-riscv-instruction-set-simulator Recent press releases

• http://www.imperas.com/articles/imperas-delivers-first-risc-v-simulator-for-new-vector-and-bit-manipulation-specifications
• http://www.imperas.com/articles/imperas-and-metrics-collaborate-to-jump-start-risc-v-core-design-verification-using-open
• http://www.imperas.com/articles/chips-alliance-builds-momentum-and-community-with-newest-members-imperas-software-and
• http://www.imperas.com/articles/openhw-group-created-and-announces-core-v-family-of-open-source-cores-for-use-in-high

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