Business Insider Intelligence forecasts that there will be more than 64 billion IoT devices installed around the globe by 2026, with companies and consumers spending nearly $15 trillion on IoT devices, solutions and supporting systems. Looking forward, the industry will experience even more growth with the worldwide adoption of 5G which will deliver higher speeds with much more capacity to support networks of connected devices.
Rapid urbanization is leading to smarter cities that improve the lives of citizens through technology. Many cities are leveraging a plethora of connected devices and different types of IoT sensors to collect data and then use insights gained from that data to manage assets, resources and services more efficiently. These types of IoT applications are ushering in more complex design requirements, forcing the industry to adapt by designing solutions that can new perform specialized tasks such as AI and ML processing in real time at the edge. The free and open RISC-V instruction set architecture (ISA) is fostering a new era of IoT processor innovation through open standard collaboration. Leveraging the flexibility, extensibility and scalability of RISC-V, companies can accelerate the development time of IoT devices, while reducing strategic risk and overall costs, opening up the door for unprecedented innovations for the IoT.
IoT Day was launched in 2010 as an open invitation to the IoT Community to gather and share their thoughts on what IoT is and what it means in everyday life. To celebrate IoT Day 2020, RISC-V members Andes Technology, Antmicro, Codasip, GreenWaves Technologies, Imperas, OneSpin Solutions, SiFive and Western Digital reflected on how the free and open RISC-V ISA enables them to innovate for the IoT.
“The open source RISC-V ISA fosters IoT innovation by making it easier for companies to develop custom IoT processors optimized for cutting-edge workloads like AI and machine learning. The layered and extensible ISA gives companies the flexibility to design solutions to meet specific requirements for IoT devices like low power operation. Additionally, the RISC-V ecosystem’s common IP building blocks and set of shared tools help reduce companies’ risk and investment in developing new IoT solutions. We look forward to seeing how the ecosystem will continue to grow as companies develop exciting new IoT implementations, driving the next phase of IoT innovation for our connected world.” – RISC-V International CEO Calista Redmond
“The proliferation of AI-enabled smart devices such as home assistants provides an ideal platform for deploying highly compact deep learning models into daily life. Due to the compute and power requirements of complex AI models, most smart devices rely on the cloud for AI processing, then return the results to the smart devices. Andes Technology and AI startup Deeplite, Inc., have collaborated to deploy highly optimized deep learning models on Andes RISC-V CPU cores based on AndeStar™ V5 architecture.” – Andes Technology President Frankwell Lin
“Owing to its flexibility and scalability, RISC-V paves the way towards an innovative approach to hardware/software co-design of complex IoT applications. Antmicro’s open source Renode framework allows you to simulate complex systems, giving you full control over each and every aspect of the simulation: the flow of time, wired and wireless communication, behavior of peripherals, sensor input etc. The ability to run unmodified software one would normally use on hardware, combined with transparent debugging and extensive automatic testing capabilities, makes Renode an ideal tool to enhance your RISC-V based IoT development.” – Antmicro Engineering Manager Peter Zierhoffer
“Embecosm enables companies to optimize computational power through compilers for the 'edge' and
the Internet of Things. RISC-V provides a flexible computing platform and enables innovation and novel
development and applications for the IoT and AIoT world. Embecosm’s expertise on compilers,
toolchain, optimization, machine learning and AI engineering offers a unique blend of engineering
technology to accelerate market propositions in start-ups and new product offerings.” – Embecosm Commercial Director Ian Loveless
“The Internet of Things is enormously varied because of the sheer diversity of sensor types, communication links and algorithms used. When designing integrated circuits for the IoT, it is desirable to create optimized processors to efficiently run IoT algorithms with minimal power consumed. The RISC-V ISA enables designers to create custom instructions which are targeted at critical algorithms such as DSP, cryptography or artificial intelligence. Ideally, such instructions should be executed as an integral part of the processor pipeline rather than as a loosely coupled accelerator. Codasip provides a range of Bk RISC-V processor cores as well as the Codasip Studio tool which can extend the Bk core with custom instructions and automatically generate the corresponding hardware and software design kits. This enables you to match your processor precisely to the needs of your IoT application.” – Codasip Senior Marketing Director Roddy Urquhart
“Over the past few years there has been a growing interest in moving AI processing to the edge for a wide range of intelligent devices. Now we’re seeing a new wave of IoT devices that require processing at the very edge to capture rich data sources like images, sounds, radar, infra-red or vibration; the challenge is that these devices are very power constrained. To meet this need, we created our GAP IoT application processor family which is based on the RISC-V and PULP (Parallel Ultra-Low-Power Processing Platform) platforms. The extensibility of the RISC-V ISA enabled us to design our GAP solutions for ultra-low power operation, enabling companies to embed machine learning and signal processing capabilities into the next generation of connected consumer, medical and industrial applications.” – GreenWaves Technologies Vice President of Marketing Martin Croome
“The open ISA flexibility of RISC-V allows system designers to explore new approaches for AIoT (Artificial Intelligence of Things) for both edge devices and datacenter accelerators. Using Imperas’ tools, virtual platforms and RISC-V models offers AIoT developers the key insights for multi-core architectural analysis and to explore the right-fit for RISC-V custom instructions for target applications. To support the AIoT design teams to first pass silicon success, the Imperas golden RISC-V reference model supports design verification (DV) with the industry standard UVM flows with SystemVerilog encapsulation. With its efficiency and reliability, the simulation-based approach offers the fastest path to address the time critical AIoT markets.” – Imperas Vice President of Marketing Kevin McDermott
“The flexibility and low cost of the RISC-V architecture has unleashed engineering creativity: going from an idea to a prototype driven by a low-power, AI-capable IoT chip is easier than ever. The growing ecosystem of RISC-V design automation solutions provides a smooth path from ideas to successful products. OneSpin is the leader in off-the-shelf, comprehensive RISC-V assurance solutions providing evidence that IoT chips are free from bugs, security vulnerabilities and malicious circuitry. Our customers create innovative products that people can trust and use with peace of mind.” – OneSpin Solutions President and CEO Raik Brinkmann
“The Internet of Things is becoming the Intelligence of Things; new generations of products are being developed that don’t have legacy carry over from previous designs, as new functions for on-device data processing and decision making are needed. RISC-V enables these new product lines to be more efficient, more powerful and configured to the needs of the designer in a simple, scalable manner. SiFive’s unique idea to silicon methodology and expertise in RISC-V and SoC development enables rapid time to market, democratizing access to silicon for companies worldwide to be part of the IoT growth moment that’s happening right now.” – SiFive President and CEO Dr. Naveed Sherwani
“The rising volume, variety and velocity of data driven by autonomous cars, AI and other Internet of Things are increasingly demanding purpose-built technologies. Open-source RISC-V cores, in particular SweRV Cores hosted at the CHIPS Alliance GitHub, are a compelling option for a wide range of IoT applications. Offering both open source and commercial support, SweRV Cores are able to meet the rigorous power-performance requirements often demanded by the IoT. The ability to freely extend RISC-V instructions with either standardized or proprietary instructions allows for ease of rapid customization, the quick addition of many different hardware modules and fast time to market.” – Western Digital Senior Director of Next Gen Platforms Dr. Zvonimir Z. Bandic
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