The EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT platform powered by deep learning algorithms. VEDLIoT comprises 12 partners from 5 countries, including Strategic Founding RISC-V International member Antmicro as well as research institutions such as our partner RISE and industry heavyweights like Veoneer or Siemens. Antmicro’s role will focus on bringing the strengths of the RISC-V ISA and their open source simulation framework Renode to the project coordinated by Bielefeld University’s CoR-Lab.
Teaching IoT to learn with RISC-V and Renode
Smart cities, smart vehicles, smart factories – systems of interconnected devices play an increasingly important role in various industries where they perform complex tasks such as tracking and object detection, inspection, navigation, sorting. VEDLIoT’s goal is to further enhance such systems with distributed AI and deep learning algorithms that will enable them to learn autonomously in order to achieve better performance and higher energy efficiency.
Leveraging its position and experience in RISC-V, machine learning and simulation, as part of the project Antmicro is building a portable open-source RISC-V-based soft SoC infrastructure for system control and AI acceleration in FPGA, as well as developing a simulated model of the FPGA SoC platform in their flagship framework for hardwareless development, Renode. Antmicro’s simulator will provide a virtual and deterministic environment for software/hardware co-development, metrics for measuring the efficiency of workloads including ML, as well as CI-driven testing capabilities, and will be available to all project members and future users of VEDLIoT.
Building on strong foundations
The VEDLIoT project will aim to research the landscape of edge machine learning technologies, spanning CPU, GPU, FPGA and dedicated ML ASICs and map it onto real use cases and needs. Actively participating in the architecture exploration tasks of the project Antmicro is proud to be showing how RISC-V is transforming all of those spaces, and how emerging RISC-V based ML platforms coupled with simulation and performance analytics can offer unprecedented openness which leads to more innovation and SW/HW co-design capabilities which are so important in enabling optimum power/performance ratio for edge AI.w
Antmicro’s contribution to VEDLIoT will build on their previous work around RISC-V support in Renode, open source SoC generators, machine learning and relevant tooling, which they have been actively developing. Some of the recent projects include creating open source FPGA tools and Renode support for the exciting, ML-oriented Core-V MCU, and enabling enabling hybrid cloud infrastructure for ASIC and FPGA flows involving RISC-V.
Designing ML the modern way
Both RISC-V and Renode have proven to constitute a great platform for architectural exploration and rapid system development, including machine learning applications. That is why platform companies and education institutions are adopting Renode for their machine learning and computer architecture courses. A tight collaboration with Google’s TensorFlow Lite Micro team has resulted last year’s demo of TF Lite Micro running on a virtual RISC-V MCU and a physical RISC-V-based board, and since then we have been enabling the TF Lite team with simulation capabilities to enable them and their user base to test and develop ML models effectively, with performance metrics analysis features, HDL co-simulation and more.
Other organizations offering machine learning solutions that have benefited from the openness of both Renode and RISC-V include fellow RISC-V members Microchip, whose first mass-market Linux-capable RISC-V implementation, PolarFire FPGA SoC, had been made available through Renode even before the release of the physical board. There’s also
QuickLogic who, having jumped onboard of RISC-V a few years back, recently became the first FPGA vendor to officially support open-source FPGA tooling, Renode and other technologies from Antmicro, increasing the reach of their products this way.
At the recent London RISC-V Meetup Antmicro’s Michael Gielda spoke about the advantages of using Renode and RISC-V on FPGAs in a machine learning context, demonstrating the flexibility and robustness of the architecture as well as the wide-ranging capabilities of Renode, and the VEDLIoT project, which is still open to additional contributors as part of the “open calls” program, will certainly benefit from these groundbreaking open-source technologies as well.