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RISC-V has been a very popular choice for embedded processor designs. Western Digital’s existing SweRV Core family is among the highest performance, area optimized embedded RISC-V Cores available today. The openness of RISC-V enabled the SweRV Core EH2 to offer dual threaded capability. It was the first commercial RISC-V core and it has notched an impressive CoreMarks/Mhz score of 7.8 in dual threaded mode.

At the RISC-V Summit on Dec 8, 2021 at 11am Zvonimir Bandic will unveil the new SweRV Core EH3. The SweRV EH3 ratchets up the capabilities and significantly broadens the applications which can be run. Register for the RISC-V Summit and attend the SweRV EH3 presentation to learn the technical details of the SweRV EH3. In addition, details on how to engage with Western Digital to access this next generation RISC-V core will be shared.

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