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Everything RISC-V at the Design Automation Conference! | RISC-V International

By July 11, 2022July 13th, 2022No Comments

The Design Automation Conference is here and we’re thrilled to share look at all the RISC-V happenings during the show.

If you are interested in getting involved with the RISC-V community, please visit our community landing page. Doing a press article or industry coverage? Let us know at or and we’ll set you up with the newsmakers.

At the RISC-V Pavillion (Booth 2332)

  • RISC-V proponents including Amazon Web Services, Imperas, Siemens, Tactical Computing Laboratories and Zero ASIC. 

At the RISC-V Open Source Central Theater (Booth 2238, full schedule here, bottom of the webpage)

  • Monday, 11 July
    • Analog IP The Way You Want It Speaker, Agile Analog at 11:30 a.m. 
    • Accelerating Time to Market: Open and Collaborative Innovation in the Hardware Development Ecosystem, CHIPS Alliance /Linux Foundation at 12:30 p.m.
    • What’s New with FreeRTOS, AWS at 1:30 p.m. 
    • Introduction to RISC-V Verification with new open standard RVVI (RISC-V Verification Interface),  Imperas Software at 2:30 p.m.
  • Tuesday 12 July
    • RISC-V and HPC, Tactical Computing Laboratories at 10:30 a.m.
    • RISC-V Models for Verification, Software Development and Architectural Exploration  Speaker, Imperas Software at 1:30 p.m.
    • CORE-V MCU Devkit Teardown, OpenHW Group and GroupGets at 2:30 p.m. 
    • Addressing the challenges of RISC-V adoption – live panel discussion at DAC 2022, Siemens, Tessent and Questa Design & Verification Technologies at 3:30 p.m.
    • CORE-V MCU DevKit Fleet Sensors in AWS IoT Cloud, OpenHW Group at 4:30 p.m.
  • Wednesday 13 July 
    • SiliconCompiler: Automating translation from Code to Silicon, Zero ASIC at 10:30 a.m. 
    • CORE-V MCU DevKit Fleet Sensors in AWS IoT Cloud, OpenHW Group at 11:30 a.m. 
    • RiVAI RVV Vector Processor Solution  Speaker,  RiVAI Technology at 2:30 p.m. 

At the Cadence Design Systems Theater (Booth 1511)

  • Taming the Beast: RISC-V Formal Verification Made Easy, Dr. Asish Darbar, Axiomise, Monday 11 July at 4 p.m. and Tuesday 12 July at 1:30 p.m.

At the Intel Foundry Systems (IFS) Theater (Booth 2325)

  • RISC-V sessions featuring Andes, Esperanto, SiFive, Synopsys, and Ventana
    • Enabling the RISC-V Ecosystem with Horse Creek, Monday 11 July at 3:30 p.m.
    • Highest-Performance RISC-V Cores, Rapid Productization with Chiplets, Tuesday 12 July at 10:30 a.m., Ventana
    • Accelerating AI and Beyond-AI with >1000 RISC-V Cores on a Single Chip(let?), Tuesday, 12 July at 11 a.m., Esperanto Technologies 
    • Synopsys & IFS: Enabling RISC-V Design Solutions, Tuesday, 12 July at 1 p.m.
    • Andes Technology RISC-V Solutions, Tuesday, July 12 at 4 p.m.

In the OpenHW Group Pavilion (Booth 2340)

  • Demos | Tuesday, 12 July at 2:30 p.m. and 4:30 p.m.
    • CORE-V MCU DevKit Fleet Sensors in AWS IoT Cloud, OpenHW Group 
    • CORE-V MCU Devkit Teardown, OpenHW Group and GroupGets

In the Conference Sessions (full conference tracks here, select RISC-V in topic to refine search results)

Get in on the Action

  • Visit the Imperas booth 2336 to play Quake on RISC-V virtual platforms and win real prizes! Free daily raffle for Apple AirPods

Be Connected

Have a great show!

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