Skip to main content

Registration for the In-person RVfpga Session at the 2022 RISC-V Summit is Open. Space is Limited! | Imagination Technologies

By November 2, 2022January 4th, 2023No Comments

Online is convenient and it has saved us during the pandemic, but you can’t beat in-person class!  That immersive feeling of hands-on and the shared mission with colleagues all trying to master the same subject. As part of our global series of workshops to “train the teachers” how to use RISC-V in computer architecture courses and the design of systems on chip (SoCs) we are thrilled to present a free training on December 15, 2022 as part of the 2022 RISC-V Summit. Our RVfpga partners, including Digi-Key are working with us to make this possible!

To do this, we are asking for a day of your time so that you can empower the next generation of computer science and engineering students to get real-world expertise in computer architecture and the RISC-V instruction set architecture. 

What is RVfpga about?

This RVfpga workshop presents a commercial RISC-V system targeted to an FPGA, discusses the theory, architecture, and course structure, and shows how to use the hands-on labs as part of the complete RVfpga course. The course explores the fundamentals of computer architecture using Western Digital’s open-source, fully verified, already in-silicon, SweRV EH1 RISC-V core targeted to a Xilinx Artix 7 FPGA on Digilent’s Nexys A7 development board.

Everyone will get hands-on experience with the FPGA platform and the software tools, enabling a fast start when you return to your university. The SweRV is not an “education core” it’s real-world, used inside Imagination’s GPUs and Western Digital’s solid-state drives.

What will you learn?

  • The workshop shows how to quickly get the RISC-V FPGA system and RISC-V tools up and running.
  • We describe each of the labs and work through a selection of them hands-on.
  • We will also discuss how to integrate RVfpga into your curriculum.

Specific topics include

  • Installing the tools (which we encourage before the workshop)
  • Targeting the SweRV EH1 RISC-V core and SoC to an FPGA
  • Programming the RISC-V SoC
  • Adding more functionality to the RISC-V SoC
  • Analyzing and modifying the RISC-V-core and memory hierarchy

Who should attend?

It’s primarily a “Train the Teacher” event, of greatest value to EE, CS and CE Teachers who want to teach Computer Architecture.  Trainers in commercial companies and postgrads who are considering a career in teaching, or becoming a chip designer will also find it useful. It’s a great opportunity to make new and refresh existing links to fellow Professors who are keen to keep their courses up-to-date. Help us spread the word and bring your colleagues.

What attendees say about the event

“The in-person RISC-V fpga Computer Architecture Workshop provided a hands-on intensive course-based opportunity to examine the resources offered by Imagination Technologies.  The courses are given by University Professors who have a deep appreciation for the ways that these systems can be integrated into a university programme.

The workshops are particularly timely, since the return to University classrooms and labs affords us the chance to re-imagine and upgrade existing curricula.  This is contemporaneous with the international movement towards the RISC-V architectural model, which can be integrated easily in an Academic setting — facilitated by affordable hardware, convenient RISC-V fpga software and tools, and accessible University teaching materials. 

The Imagination University Program workshops and online lectures provide a curated and comfortable walk through a massive amount of resources. I have returned to my University with a clear plan for transforming my lectures and labs on Hardware/Software Co-Design, and Computer Architectures.” 

Roy Eagleson, PhD, PEng,
Professor of Computer and Software Engineering
The University of Western Ontario

About Our Trainer

Dr. Sarah Harris, professor of electrical and computer engineering at the University of Nevada, Las Vegas.  Sarah Harris earned her M.S. and Ph.D. at Stanford University. She is the co-author of three popular textbooks: Digital Design and Computer Architecture, 2nd Edition (2007), ARM Edition (2015), and RISC-V Edition (2021). Her research interests include computer architecture and applications of embedded systems and machine learning to biomedical engineering and robotics.

More information

About the IUP and RVfpga.


Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.