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Announcing The First International Workshop for HPC based on RISC-V

By February 14, 2023No Comments

RISC-V has seen phenomenal growth in recent years across a range of applications. One of the most exciting areas of development is High Performance Computing (HPC) where computational horsepower is used by scientists and engineers to tackle some of the grand challenges faced by society, ranging from improving the accuracy of weather forecasts to designing more fuel efficient aircraft engines. There are a huge range of potential workloads, and the explosion of machine learning in recent years means that the world’s supercomputers are currently busier than they have ever been, gaining the ability to address an even wider range of problems!

The RISC-V HPC Special Interest Group is organising a workshop at ISC23, one of the leading High Performance Computing (HPC) conferences. The workshop will run on the 25th of May in Hamburg Germany, and the call for papers is open!

Currently, HPC tends to rely heavily on commodity hardware CPUs which are often paired with GPU accelerators. However, it is our belief that the open nature of RISC-V can significantly benefit the HPC community by providing many more opportunities for specialisation. RISC-V can deliver increased choice around the architecture for supercomputing centres, with CPUs tuned for specific workloads, and benefits around integration where these CPUs can be combined with application specific accelerators to deliver a highly optimized overall solution.

Indeed, there are efforts already underway in these areas, and if you attended the RISC-V Summit in December last year then you will have heard about many exciting technologies being developed across the community. Furthermore, we are also seeing the emergence of RISC-V testbeds which enable free access to the technology for high performance workloads. However, there is much still to be done, especially on the software side, to ensure that the process of embracing RISC-V for HPC is as painless as possible for the end users, many of whom just want their code to run as quickly as possible!

The purpose of the workshop at ISC is to bring together those already involved in RISC-V with the supercomputing community at-large. The success of Birds of a Feather collaborative sessions at previous HPC conferences demonstrates that there is the appetite here, so our objective is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators.

We hope to have a diverse set of RISC-V based HPC topics at the workshop, ranging from application porting and lessons learnt, to tool and hardware development. This is where we need your support.  If you have done work in this area that you think could be topical and interesting to such an audience then please consider submitting a paper. We are accepting both full papers on mature work and also work-in-progress papers on more embryonic activities.

The deadline for submitting papers is 24th March 2023 (AoE) with more details on our website at

We hope to see you at the worksop and share in the amazing possibilities of High Performance Computing based on RISC-V.

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