By: Thomas Böhm – SVP Automotive Microcontroller, Infineon
One of the megatrends in the automotive industry is the Software Defined Vehicle (SDV), where major innovations and new vehicle features are driven by the power of software, running on reduced numbers of more powerful in-car computers. SDV is an important development, but does this mean the end of automotive microcontroller development? Infineon is a global semiconductor company that has been designing automotive MCUs for over 20 years and we believe that the next phase of automotive development will bring a new wave of innovation with advances in dependability, affordability, safety, security, AI and more. We see the RISC-V ISA as a key technology that will address these challenges and enable us to deliver future generations of automotive MCUs powering an amazing range of in-car experiences from electrification to increased self-driving capability.
The evolution of Automotive MCU
Automotive MCUs have changed a lot in the last 20 years. From 2000 to 2010 the most important factor was increasing performance, with a move from 8 to 16, then 32bit, as well as the first multi-core devices being developed, with real-time capability, and low interrupt latency being key performance considerations. Raw performance is always important, but throughout the 2010s, safety also came into focus with the introduction of the ISO26262 standard, as well as security, with new instructions and Hardware Security Modules (HSM) added. Since 2020, software and AI have been new considerations, with added features for virtualization and acceleration.
The next wave of MCU innovation will bring further disruption with a move to AI algorithms, a higher focus on cost to enable more affordable cars, and increased development speed with a vehicle design cycle of 2 years replacing the 5-7 years cycles of the past. Performance continues to be important, as more workloads run together on a single automotive controller. Real time capabilities of determinism and low latency, reliability and availability are key considerations in a future of high voltage electrical charging systems and motor control, as are safety capabilities to detect and deal with faults, and security in a world which will require post-quantum cryptography. Finally, a focus on reuse and scalability is important to make sure that the investment of our customers in software components can scale across different vehicle architectures and cost levels
Traditionally, a microcontroller has two jobs to do, system management including reset management and power mode handling, and real-time control including low latency interrupt handling and task scheduling. Now, alongside those requirements, there are new jobs the controller needs to do. Embedded accelerators provide the performance for security and specific application workloads such as radar. Data processing blocks deal with high performance, complex processing tasks and memory management, while the increase in AI workloads also requires specialized acceleration.
Why RISC-V?
This breadth of capabilities means that a modern automotive MCU requires a lot of different processing cores with different capabilities. Rather than implementing these cores with different architectures, we see RISC-V as a lean, scalable, cost efficient way of implementing the diverse computing requirements required by future microcontrollers.
- The amazing value proposition of RISC-V is that we can implement all of these specific cores using the same architecture. This is valuable for us, but also for our customers, who can use the same programming environment and toolchains for their development.
- Automotive applications have a requirement for dependability, that the system can maintain its availability when parts of it break down. The RISC-V ISA gives a good basis to enable graceful degradation, to reset parts of the system that are going wrong and maintaining functionality.
- The range of capabilities and performance mentioned previously makes scalability a key challenge. This is addressed by the RISC-V architecture through the use of extensions. We can add capabilities for security, real time processing, data processing and ML on top of the same base ISA to address all our different processing requirements.
- The inclusive and open nature of the RISC-V ISA drives knowledge sharing within the ecosystem, in turn creating a community, and that drives innovation. We want to be part of an ecosystem with new ideas, creating new features, as it allows us to focus on how we can differentiate for our customers.
The power of the RISC-V Ecosystem
Infineon is harnessing the strong and highly capable RISC-V ecosystem. We are partnering with Synopsys on IP development for a brand new architecture, to work out the features and extensions we need to support future applications. The first result of this will be a virtual prototype of our next generation RISC-V MCU, made available at the end of 2024. This prototype will enable our customers to start their software development and evaluation before silicon availability, and allows us to gather valuable feedback. We are also working with tool vendors to ensure that ecosystem support exists for this new architecture, and that this support is qualified for important safety standards like ISO26262.
To further adoption of RISC-V, we are collaborating with Bosch, Nordic Semiconductor, NXP and Qualcomm to form Quintauris with a mission to accelerate standardization for the automotive market. This will enable the software tools community to provide the investment and support to drive adoption at scale.
RISC-V powering the future of Automotive MCU
As the world’s number one automotive microcontroller company, Infineon sees huge potential for future MCU innovation and is investing in a RISC-V based platform as an expansion of our product portfolio, and a key part of our strategy for the future. We see RISC-V as a lean and cost efficient starting point for future high performance, dependable and scalable products addressing new automotive challenges and applications of the next 5 – 10 years and beyond.
This blog is based on Thomas’ presentation at RISC-V Summit Europe 2024. For more detail, view the whole session below.