Silicon Valley, CA – August 6th, 2025 – Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK.
RiscFree provides comprehensive visibility and control across the entire software stack—from low-level drivers to highlevel application code. With features including breakpoints, step/continue execution, register and memory inspection, realtime trace, and multi-core support (both homogeneous and heterogeneous), RiscFree enables efficient debugging, tracing and performance tuning of complex embedded systems. This collaboration ensures that developers targeting Tenstorrent’s high-performance Ascalon RISC-V cores can now rely on a robust and proven tool chain to accelerate development, debugging, and system validation.
