SiFive Expands Its RISC-V Intelligence Family To Address Exploding AI Workloads
SiFive just announced an array of new additions to its product stack that run the gamut, from tiny, ultra lower-power designs for far edge IoT devices, to more powerful... Read more.
Quintauris and TASKING join forces to power RISC-V in automotive
Quintauris and TASKING have announced a new partnership to strengthen RISC-V development for the automotive industry. As part of this collaboration, Quintauris... Read more.
Design Approaches and Architectures of RISC-V SoCs
Author: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s... Read more.
Leveraging Formal Verification to find critical RTL bugs in a RISC-V core – a LUBIS EDA best practice
In an industry where missed corner cases can delay products by weeks or even months, LUBIS EDA recently demonstrated how formal verification can catch critical design... Read more.
From Simulation Bottlenecks to Formal Confidence: Leveraging Formal for Exhaustive RISC-V Verification
Introduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective... Read more.
RISC-V basics: The truth about custom extensions
The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications... Read more.
Arteris’ Multi-Die Solution for the RISC-V Ecosystem
by Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly every five... Read more.
EE Times: China Unyielding Ascent in RISC-V
As a participant at the recent RISC-V Summit in Shanghai, I witnessed firsthand the sheer scale and unwavering resolve with which China is strategically investing... Read more.
Ashling Announces RiscFree™ Debug and Trace Support for Tenstorrent TT-Ascalon™ RISC-V CPUs
Silicon Valley, CA – August 6th, 2025 – Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK.... Read more.
S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China
Shanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes... Read more.