Power, automotive and AI markets highly interested in RISC-V
At the recent SiFive RISC-V China Technology Forum that took place in Shenzhen, China, SiFive chief architect and the chairman of RISC-V International Krste Asanović... Read more.
It’s all about RISC-V code size
Here at Codasip we’re passionate about reducing the code size of our RISC-V cores for our customers, but why? Are we not making the core larger and more complex... Read more.
Bluespec’s MCUX RISC-V Processor Ideal for FPGAs and ASICs
Framingham, Massachusetts. Bluespec Inc. released its MCUX RISC-V processor designed to simplify the integration of customize protocols and add accelerators to... Read more.
VIDEO: EUPILOT: Europe’s HPC and AI pre-exascale accelerator demonstrator
The EUPILOT project aims to establish a European-based accelerator platform for high-performance computing (HPC) and AI. It seeks to achieve European digital... Read more.
Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests
Grenoble, France – July 3, 2023 – Tiempo Secure’s latest TESIC design, a Secure Element targeting applications such as iSIM, eSE, Payment, UWB, Digital ID,... Read more.
VMware join hands with Samsung, AMD, RISC-V for confidential computing
VMware recently announced at the Confidential Computing Summit 2023 that it is partnering with chipmakers Samsung, AMD, and the RISC-V Keystone community for... Read more.
Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests
Grenoble, France – July 3, 2023 – Tiempo Secure’s latest TESIC design, a Secure Element targeting applications such as iSIM, eSE, Payment, UWB, Digital ID,... Read more.
VMware, Other Tech Giants Announce Push for Confidential Computing Standards
In conjunction with the 2023 Confidential Computing Summit last week, VMware announced a partnership with tech giants to accelerate the development of confidential... Read more.
Customizable RISC-V processor is vendor-independent
Bluespec’s MCUX RISC-V processor allows developers to implement custom instructions and add accelerators to FPGAs and ASICs. MCUX joins the company’s MCU RISC-V... Read more.
Chinese Researchers Used AI to Design RISC-V CPU in Under 5 Hours
A group of Chinese scientists has published (PDF) a paper titled “Pushing the Limits of Machine Design: Automated CPU Design with AI.” The paper details... Read more.