GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors | Nazareno Bruschi∗ , Germain Haugou†‡, Giuseppe Tagliavini∗ , Francesco Conti∗ , Luca Benini∗†, and Davide Rossi∗ (∗University of Bologna, †ETH, ‡GreenWaves-Technologies)
Abstract—The last few years have seen the emergence of IoT processors: ultra-low power systems-on-chips (SoCs) combining lightweight and flexible micro-controller... Read more.
SiFive Preps Next-Gen HiFive Unmatched RISC-V Boards | Anton Shilov, Tom’s Hardware
SiFive is ending production of current-generation Unmatched boards for RISC-V developers.
SiFive this week announced that due to challenges with components supply,... Read more.
Google Research Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning | Gareth Halfacree, AB Open
Google Research has released the source code for a chip floor-plan generate based on deep reinforcement learning – after publishing a paper demonstrating how effective... Read more.
NSITEXE and Green Hills Software Partner on RISC-V Solutions | Design & Reuse
NSITEXE, Inc., a wholly owned subsidiary of Denso Corporation that develops and sells high efficiency processor IP for embedded systems, and Green Hills Software,... Read more.
ASIC roundup of open source RISC-V CPU cores | Oguz Meteer, BitlogIT
While waiting for simulation results for my final paper, I thought I’d synthesize and do place & route of several open source RISC-V CPU cores for fun. Some... Read more.
RISC-V SoC + AI – Run a demo of the ncnn inference framework using Allwinner’s D1 “Nezha” Development Board | Verimake
D1 is Allwinner's first SoC based on the RISC-V ISA,which has a 64-bit Xuantie C906 core from T-Head. The "Nezha" Development Board is an AIoT development board... Read more.
The State of the RISC-V Union, part II | Paul McLellan, Cadence Design Systems
This is part 2 of my post on DAC and RISC-V from December. The first post is here. This post will cover Krste's presentation and then Calista back at the end to... Read more.
First impression on Nezha RISC-V SBC | 3mdeb
Nezha board is a development board that is designed by an AWOL. This project uses a D1 SoC from Allwinner which is used for the first time by the general public.... Read more.
SEGGER J-Link – Performance analysis on RISC-V | SEGGER
Watch how to do a performance analysis on a RISC-V device using SEGGER's market-leading J-Link, Ozone and SystemView to tap into SiFive's insight debug and trace... Read more.
At CES2022 Bouffalo Shows its Matter Turnkey Solution | Bouffalo Lab, EE Times
With a comprehensive lineup of wireless SOCs, Bouffalo Lab fully supports Matter, the wireless and interoperability standard for smart home devices, offering a complete... Read more.