Interview With Dirk Koch and Nguyen Dao | Matt Venn, Zero To ASIC
Read the full article and watch the interview.
"One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi... Read more.
Introduction & Developer Tips for Zephyr RTOS | Zephyr Project
What is Zephyr RTOS? Why would I chose Zephyr over Linux? How is it open source? What is the Zephyr Project and how does it relate to the RTOS?
These are a few... Read more.
Video: Pineapple One: An Open-Source Discrete 32-Bit RISC-V CPU
This talk will be about a 32-bit homemade RISC-V CPU, made only out of discrete logic components and memories. There are no FPGAs nor any microcontrollers used and... Read more.
CAES Receives Contract from Vinnova to Advance High Performance RISC-V Space Computing
CAES, a leader in advanced mission-critical electronics for aerospace and defense, announced today that it has been awarded a contract from Vinnova, a Swedish government... Read more.
Agile Analog brings analog IP to RISC-V International | Jean-Pierre Joosting, Design & Reuse
As a strategic member, Agile Analog expects to widen access to its application- and process-optimised analog IP for smart and IoT devices.
Agile Analog, a supplier... Read more.
René Rebe Patches the Linux Kernel for “World’s First” Look at a Radeon RX 6700XT on a RISC-V PC | Gareth Halfacree, Hackster.io
Computer scientist René Rebe has patched the Linux kernel to bring support for AMD's RDNA2-based Radeon RX 6700XT graphics card to RISC-V systems — starting with... Read more.
WARP-V: A RISC-V CPU Core Generator Supporting MIPS ISA | Abhishek Jadhav, CNX Software
If you have been working on open standard RISC-V ISA CPU cores, there is a high chance that you have come across WARP-V. For newbies, WARP-V is a RISC-V CPU core... Read more.
Previewing the Beagle V | Mender.io
Beagleboard.org has joined forces with Seeed and StarFive to launch the Beagle V . The Beagle V has the advantage of being a low cost board that allows developers... Read more.
Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites
Imperas Software Ltd., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified... Read more.
Case Study: SiFive Launches Unmatched Board Remotely | Blue Clover Devices
The Challenge
A guiding light in the RISC-V community, SiFive was preparing to launch a new quad-core processor and evaluation board. Preorders were accumulating... Read more.