Tenstorrent Selects SiFive Intelligence X280 for Next-Generation AI Processors
SiFive Intelligence IP integral component of future Tenstorrent AI architectures
SAN MATEO, Calif., April 22, 2021 – SiFive, Inc., the industry leader in RISC-V... Read more.
Video: De-RISC project
The De-RISC (Dependable Real-time Infrastructure for Safety-critical Computer) project addresses computer systems within the space and aviation domains. De-RISC... Read more.
RISC-V Targets Data Centers | ANN STEFFORA MUTSCHLER, Semiconductor Engineering
RISC-V vendors are beginning to aim much higher in the compute hierarchy, targeting data centers and supercomputers rather than just simple embedded applications... Read more.
Jim Keller-Led Tenstorrent Licenses RISC-V for AI | Anton Shilov, Tom’s Hardware
Ex-AMD engineers chose RISC-V CPU for their AI SoC design.
Tenstorrent, a developer of heterogeneous processors for AI applications led by ex-AMD engineers Ljubisa... Read more.
What is the RISC-V ecosystem? | Jeff Shepard, EE World
n its most basic form, RISC-V is an open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) design principles. RISC-V is... Read more.
Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications
SiFive to License Industry-Leading RISC-V Core IP Portfolio to Renesas
TOKYO, Japan, and SAN MATEO, Calif., April 21, 2021 – Renesas Electronics Corporation (TSE:6723),... Read more.
Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications
SiFive to License Industry-Leading RISC-V Core IP Portfolio to Renesas
TOKYO, Japan, and SAN MATEO, Calif. – Renesas Electronics Corporation (TSE:6723),... Read more.
Getting Started with BeagleV™ – StarLight | Seeed
BeagleV™ - StarLight is the first affordable RISC-V computer designed to run Linux. It is fully open-source with open-source software, open hardware design and... Read more.
RISC-V User space access Oops | Ben Dooks, Codethink
As part of Codethink's interest in RISC-V I have been following the RISC-V kernel list. Whilst looking through the postings the following bug (more information here)... Read more.
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform | Journal of Systems Architecture
Abstract
Recently, Virtual Prototypes (VPs) were introduced for the emerging RISC-V Instruction Set Architecture (ISA) and become an important part of the growing... Read more.