RISC-V-Enabled SOM Aids Embedded Development | Susan Nordyk, EDN
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OpenRISC + RISC-V Improvements Come for Linux 5.11 | Michael Larabel, Phoronix
LiteX is a Migen/MiSoC CPU/SoC builder for deployments on FPGAs. LiteX already supports soft-core implementations of PicoRV32, VexRISCV, and others. Read the full... Read more.
Digital Storage Projections for 2021, Part 1 | Thomas Coughlin, Forbes
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Cmsemicon ANT32RV56xx is a RISC-V microcontroller for wireless charging | Jean-Luc Aufranc, CNX Software
general-purpose microcontrollers, AIoT processors, as well as WiFi and Bluetooth IoT SoC’s such as ESP32-C3 and BL602. Allwinner is also prepping a RISC-V... Read more.
Spatial : Cobham Gaisler et l’éditeur espagnol fentISS collaborent autour de l’architecture de processeur RISC-V (French) | Pierrick Arlot, L’embarqué
Cobham Gaisler élargit sa collaboration avec l’éditeur espagnol fentISS afin de promouvoir en commun le cœur de processeur Leon5 et le cœur compatible RISC-V... Read more.
Micro Magic details its 1GHz RISC-V processor | Peter Clarke, ee News Europe
eeNews Europe Mark Santoro, CEO of Micro Magic, said the processor core had also been designed so that it can operate down to at least 350mV, near the threshold... Read more.
Linux 5.10 LTS release – Main changes, Arm, MIPS and RISC-V architectures | Jean-Luc Aufranc, CNX Software
has just released Linux 5.10: Ok, here it is – 5.10 is tagged and pushed out. I pretty much always wish that the last week was even calmer than it was,...... Read more.
ET-SoC-1 Chip with More Than 1,000 RISC-V Cores Aimed at Accelerating Machine Learning | Abhishek Jadhav, hackster.io
At the RISC-V Summit 2020, Art Swift, CEO of Esperanto Technologies, announced the development of a chip based on the open source RISC-V architecture with more than... Read more.