Betrusted’s Precursor and Renode – a user story | Antmicro
Xobs, one of the lead engineers behind the Precursor project, at the last Hackaday Superconference – back in the seemingly distant past when we still had... Read more.
SiFive与赛昉科技携手加强以数据为中心的人工智能运算在存储领域上的应用
Read the full article]]>... Read more.
Codasip Announces Three New RISC-V Application Processor Cores Providing Multi-Core and SIMD Capability | Codasip
Munich, Germany – December 4th, 2020 – Codasip, the leading supplier of customizable RISC-V® processor IP, today announces three new 64-bit RISC-V application... Read more.
#519 – Simulating Embedded Hardware with Michael Gielda | The AMP Hour
Michael Gielda of Antmicro and the CHIPS Alliance! Listen to the podcast.]]>... Read more.
New RISC-V CPU claims record breaking performance per watt | Micro Magic Inc
Micro Magic Inc.—a small electronic design firm in Sunnyvale, California—has produced a prototype CPU that is several times more efficient than world-leading... Read more.
Imperas Extends free riscvOVPsimPlus Simulator for RISC-V | Imperas
riscvOVPsimPlus™ includes latest reference model and now offers expanded simulation features for debug & trace for early software development and hardware... Read more.
RISC-V Summit 2020 – virtual booth, keynote session and talks | Antmicro
keynote session including our partners and RISC-V International members, and giving talks describing our efforts aimed at improving the RISC-V tooling ecosystem.... Read more.
RISC-V for ultra-low power processing and AI on the edge | Jeff Shepard, Microcontroller Tips
PULP Platform The Parallel Ultra Low Power (PULP) Platform started as a joint effort between the Integrated Systems Laboratory (IIS) of ETH Zürich and the Energy-Efficient... Read more.
