Qualcomm to Bring RISC-V Based Wearable Platform to Wear OS by Google
Highlights: Qualcomm and Google are extending their collaboration on wearables by developing a RISC-V Snapdragon Wear™ platform that will power next-generation... Read more.
Qualcomm Adopts RISC-V for Next-Gen Snapdragon Wear Platform
Qualcomm and Google announced that they had agreed to expand their partnership to development of a Snapdragon Wear platform based on the RISC-V instruction set architecture... Read more.
SharpRISCV Overview: A Browser-Based RISC-V Assembler for Seamless Learning and Exploration
In the ever-evolving landscape of computer architecture, RISC-V stands out as an open-source instruction set architecture that offers flexibility and adaptability.... Read more.
Codasip announces next-generation RISC-V processor family for Custom Compute
Munich, Germany — October 17, 2023 – Codasip®, the leader in RISC-V Custom Compute, announced today a new highly configurable family of RISC-V baseline... Read more.
Codasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyone
Today, technology innovators must have new ways to create differentiated products. How are they supposed to meet the demand for more computational performance when... Read more.
SiFive Rolls Out RISC-V Cores Aimed at Generative AI and ML
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC. The RISC-V movement is one of the hottest... Read more.
SiFive unveils two new high-performance RISC-V processors
SiFive, a RISC-V processor design firm, unveiled two new chip designs aimed at bringing a high-performance computing solution to various industries. The announcement... Read more.
SiFive Announces Differentiated Solutions for Generative AI and ML Applications Leading RISC-V into a New Era of High-Performance Innovation
Santa Clara, Calif., Oct. 11, 2023 –SiFive, Inc., the pioneer and leader of RISC-V computing today announced two new products designed to address new requirements... Read more.
DPI support in Renode for HDL co-simulation with Verilator and Questa
Author: Antmicro Hardware Description Languages (HDLs), such as Verilog and SystemVerilog, are used to express the behavior of digital electronic circuits for field-programmable... Read more.
Semidynamics and Signature IP Expand Multi-Core RISC-V and CHI Options
Two relatively new players in the CPU world, Semidynamics and Signature IP, have announced multi-core RISC-V and CHI interconnect IP for compute-intensive applications... Read more.