RISC-V Community News Archives

In the Media

UltraSoC appoints Jonathan Lucas as VP of Software

by RISC-V Community News May 18, 2020 0

Former director of Icera and Five.AI brings real-time embedded and ML experience UltraSoC has announced the appointment of Jonathan Lucas as VP of Software. His... Read more.

In the Media

CHIPS Alliance’s Newly Enhanced SweRV Cores Available to All for Free | CHIPS Alliance

by RISC-V Community News May 18, 2020 0

SAN FRANCISCO, May 14, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced... Read more.

In the Media

Power Side-channel Leakage Evaluation of a RISC-V Microprocessor | Muhammad Arsath

by RISC-V Community News May 16, 2020 0

In the Media

Foundries.Io Bringing Secure Linux Solutions For Arm, Intel & Risc-V Based Hardware

by RISC-V Community News May 16, 2020 0

In the Media

SiFive: “Vectors are History”: 30 Years Later | Randy Allen, The Linley Group

by RISC-V Community News May 15, 2020 0

In the Media

SiFive: The Direction and Magnitude of SiFive Intelligence | Nick Knight, The Linley Group

by RISC-V Community News May 15, 2020 0

In the Media

2020 RISC-V CON Series: The Next Generation RISC-V Processors AndesCore™ 27, 45 Series | Jason Lin & KY Hsieh, Andes Technology

by RISC-V Community News May 11, 2020 0

In the Media

(中) 2020 RISC-V CON Series: The Next Generation RISC-V Processors AndesCore™ 27, 45 Series | Jason Lin & KY Hsieh, Andes Technology (Chinese)

by RISC-V Community News May 11, 2020 0

In the Media

Xvisor: Embedded Hypervisor for RISC-V – Anup Patel, Western Digital

by RISC-V Community News May 10, 2020 0

In the Media

RISC-V Munich Meetup

by RISC-V Community News May 9, 2020 0

Author: RISC-V Community News

UltraSoC appoints Jonathan Lucas as VP of Software

CHIPS Alliance’s Newly Enhanced SweRV Cores Available to All for Free | CHIPS Alliance

Power Side-channel Leakage Evaluation of a RISC-V Microprocessor | Muhammad Arsath

Foundries.Io Bringing Secure Linux Solutions For Arm, Intel & Risc-V Based Hardware

SiFive: “Vectors are History”: 30 Years Later | Randy Allen, The Linley Group

SiFive: The Direction and Magnitude of SiFive Intelligence | Nick Knight, The Linley Group

2020 RISC-V CON Series: The Next Generation RISC-V Processors AndesCore™ 27, 45 Series | Jason Lin & KY Hsieh, Andes Technology

(中) 2020 RISC-V CON Series: The Next Generation RISC-V Processors AndesCore™ 27, 45 Series | Jason Lin & KY Hsieh, Andes Technology (Chinese)

Xvisor: Embedded Hypervisor for RISC-V – Anup Patel, Western Digital

RISC-V Munich Meetup

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Author: RISC-V Community News

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About

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Resources

Join RISC-V International

Becoming a member of RISC-V International allows companies and individuals to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs.