Webinar: Multicore RISC-V Designs in AI & Machine Learning Applications | Imperas
Two meetings hosted on Wednesday May 6 to learn about Multicore RISC-V Designs in AI & Machine Learning Applications Imperas, Andes, and UltraSoC invite... Read more.
Senior Project Spotlight: Anthony Kenny | Harvard University
https://www.seas.harvard.edu/news/2020/04/senior-project-spotlight-anthony-kenny]]>... Read more.
Linux 5.8 Seeing The Preliminary Changes Ahead Of RISC-V EFI Support | Michael Larabel, Phoronix
RISC-V architecture’s Linux kernel support is EFI handling. The preliminary work for supporting EFI on RISC-V is set to land for the Linux 5.8 kernel. article:... Read more.
Embedded Linux Conference Goes Virtual At $50 A Pop | Eric Brown, LinuxGizmos
RISC-V and co-founder of SiFive, as well as the LF’s Kate Stewart, Director of Strategic Programs, on “Open Source in Safety Critical Systems.” On opening... Read more.
SystemVerilog linting and formatting with FuseSoC – Verible integration | Antmicro
CHIPS Alliance, which we are members of, have been working together with the lowRISC project to address this issue by implementing relevant tools and useful integrations... Read more.