Introduction to RISC V and Assembly Language for Beginners | Bahadir Balban, Dev.to
Learn what RISC V is, and basic assembly language in 15 minutes This is a gentle introduction to the RISC V open source instruction set architecture (ISA) for beginners.... Read more.
GD32 MCU wins Embedded Award 2020 International Top Award | Wei Yuning, Digitimes
北京兆易創新GD32 MCU於德國紐倫堡參加Embedded World 2020，GD32VF103系列RISC-V內核MCU在硬體領域提名中脫穎而出並贏得冠軍，獲得年度最佳硬體產品大獎。... Read more.
Andes Custom Extensions to the RISC-V V5 CPU Core for Creating Highly Competitive True Wireless Stereo SoC Designs | Global Newswire
RISC-V CON Online webinar series. The first will feature Advanced Engineer Tung Wei describing how using Andes Custom Extensions (ACE) with Andes RISC-V CPU cores... Read more.
RISC-V processor trace now standardized: Even open source needs agreed specs
After eighteen months of hard work, it’s done: the RISC-V processor trace spec is ratified. This is excellent news and everyone involved should congratulate... Read more.
Can China Foster Open Source Hardware Innovation? | Gu Zhengshu, EE Times China
https://www.eettaiwan.com/news/article/20200303NT61-could-China-build-the-open-hardware-platform]]>... Read more.
Calista in Conversation with Iris Stroh on the VIP Stage at Embedded World 2020 | Markt & Technik, Elektroniknet.de
https://www.elektroniknet.de/embedded/alle-videos-von-der-vip-buehne-2020-im-ueberblick-174130-Seite-6.html]]>... Read more.
Emerging Technology Analysis: Opportunities of Open Instruction Set Architecture RISC-V | Amy Teng and Roger Sheng, Gartner
https://www.gartner.com/en/documents/3981573/emerging-technology-analysis-opportunities-of-open-instr]]>... Read more.