Cybersecurity meetup tackles risks and legislation
On the 30th January, UltraSoC sponsored the first meeting of the Bristol Cybersecurity Innovators Group, and it’s fair to say it was a resounding success.... Read more.
Bavarian RISC-V Security Chip With seL4 Microkernel | Christof Windeck, Heise
https://www.heise.de/newsticker/meldung/Bayrischer-RISC-V-Sicherheitschip-mit-seL4-Microkernel-4654021.html]]>... Read more.
Oreboot Continues Advancing For Open-Source, Rust-Based Booting On RISC-V | Michael Larabel, Phoronix
an open-source focused, Rustlang-based downstream of Coreboot. Oreboot continues advancing in its own right concurrent to the wonderful Coreboot advancements. article:... Read more.
Create A Research Network To Boost The Development Of Open Source Hardware | La Vanguardia
https://www.lavanguardia.com/vida/20200204/473288654546/catalunya-crean-una-red-de-investigacion-para-impulsar-el-desarrollo-de-hardware-de-codigo-abierto.html]]>... Read more.
seL4 Microkernel Being Ported To RISC-V | Michael Larabel, Phoronix
https://www.phoronix.com/scan.php?page=news_item&px=seL4-Coming-To-RISC-V]]>... Read more.
System-On-Module Integrates Multi-Core RISC-V SoC FPGA | Alex Lynn, Electronics Specifier
ARIES Embedded has announced that it will present their new System-on-Module (SoM) M100PFS at Embedded World 2020, stand 441 in hall 3A from February 25th to 27th,... Read more.
High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V | Shubu Mukherjee, SiFive
https://www.sifive.com/blog/high-bandwidth-accelerator-access-to-memory-enabling-optimized-data-transfers-with-risc-v]]>... Read more.