Ultra-Low Power AI Chip Ups The Ante | Sally Ward-Foxton, EE Times
https://www.eetimes.com/ultra-low-power-ai-chip-ups-the-ante/]]>... Read more.
AndesCore 27-Series Linux RISC-V SoC Features A Vector Processing Unit | Stephen Vicinanza, CNX Software
https://www.cnx-software.com/2019/12/13/andescore-27-series-linux-risc-v-soc-features-a-vector-processing-unit/]]>... Read more.
Samsung To Use SiFive RISC-V Cores For SoCs, Automotive, 5G Applications | Anton Shilov, AnandTech
https://www.anandtech.com/show/15228/samsung-to-use-riscv-cores]]>... Read more.
Veridify Security To Demonstrate DOME A Zero-Touch Onboarding And Device Management Solution For RISC-V Processors | Tiera Oliver, Embedded Computing Design
https://www.embedded-computing.com/hardware/veridify-security-to-demonstrate-dome-a-zero-touch-onboarding-and-device-management-solution-for-risc-v-processors]]>... Read more.
RISC-V Summit: Silicon Labs Q&A On IoT Hardware | Brian Buntz, IoT World Today
Silicon Labs’ chief technology officer shares his thoughts on what RISC-V technology means for IoT hardware and why the industry needs more Renaissance people. ... Read more.
Linux-Driven RISC-V Core To Debut On An NXP i.MX SoC | Eric Brown, LinuxGizmos
http://linuxgizmos.com/linux-driven-risc-v-core-to-debut-on-an-nxp-i-mx-soc/]]>... Read more.
Support For RISC-V Expands At Summit | Chris Edwards, Tech Design Forum
https://www.techdesignforums.com/blog/2019/12/11/risc-v-support-expands-at-summit/]]>... Read more.
RISC-V and Arm – signs of an open heterogeneous world
I’m back in San Jose for the second time in just a couple of months, it’s been interesting to compare the two events I’ve attended here recently... Read more.
Driving To Data-Centric Architectures And 1B RISC-V Cores | Office of the CTO, Western Digital
transition over one billion cores per year to RISC-V. As a founding member of the 150+ organization-strong RISC-V Foundation, our commitment hasn’t wavered and... Read more.